233 lines
6.5 KiB
C
233 lines
6.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PWM device driver for SUNPLUS SP7021 SoC
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*
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* Links:
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* Reference Manual:
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* https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
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*
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* Reference Manual(PWM module):
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* https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM
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*
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* Limitations:
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* - Only supports normal polarity.
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* - It output low when PWM channel disabled.
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* - When the parameters change, current running period will not be completed
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* and run new settings immediately.
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* - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
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* done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
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*
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* Author: Hammer Hsieh <hammerh0314@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#define SP7021_PWM_MODE0 0x000
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#define SP7021_PWM_MODE0_PWMEN(ch) BIT(ch)
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#define SP7021_PWM_MODE0_BYPASS(ch) BIT(8 + (ch))
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#define SP7021_PWM_MODE1 0x004
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#define SP7021_PWM_MODE1_CNT_EN(ch) BIT(ch)
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#define SP7021_PWM_FREQ(ch) (0x008 + 4 * (ch))
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#define SP7021_PWM_FREQ_MAX GENMASK(15, 0)
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#define SP7021_PWM_DUTY(ch) (0x018 + 4 * (ch))
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#define SP7021_PWM_DUTY_DD_SEL(ch) FIELD_PREP(GENMASK(9, 8), ch)
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#define SP7021_PWM_DUTY_MAX GENMASK(7, 0)
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#define SP7021_PWM_DUTY_MASK SP7021_PWM_DUTY_MAX
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#define SP7021_PWM_FREQ_SCALER 256
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#define SP7021_PWM_NUM 4
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struct sunplus_pwm {
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struct pwm_chip chip;
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void __iomem *base;
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struct clk *clk;
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};
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static inline struct sunplus_pwm *to_sunplus_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct sunplus_pwm, chip);
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}
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static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct sunplus_pwm *priv = to_sunplus_pwm(chip);
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u32 dd_freq, duty, mode0, mode1;
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u64 clk_rate;
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if (state->polarity != pwm->state.polarity)
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return -EINVAL;
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if (!state->enabled) {
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/* disable pwm channel output */
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mode0 = readl(priv->base + SP7021_PWM_MODE0);
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mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);
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writel(mode0, priv->base + SP7021_PWM_MODE0);
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/* disable pwm channel clk source */
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mode1 = readl(priv->base + SP7021_PWM_MODE1);
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mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);
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writel(mode1, priv->base + SP7021_PWM_MODE1);
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return 0;
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}
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clk_rate = clk_get_rate(priv->clk);
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/*
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* The following calculations might overflow if clk is bigger
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* than 256 GHz. In practise it's 202.5MHz, so this limitation
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* is only theoretic.
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*/
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if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC)
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return -EINVAL;
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/*
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* With clk_rate limited above we have dd_freq <= state->period,
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* so this cannot overflow.
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*/
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dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER
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* NSEC_PER_SEC);
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if (dd_freq == 0)
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return -EINVAL;
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if (dd_freq > SP7021_PWM_FREQ_MAX)
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dd_freq = SP7021_PWM_FREQ_MAX;
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writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
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/* cal and set pwm duty */
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mode0 = readl(priv->base + SP7021_PWM_MODE0);
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mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);
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mode1 = readl(priv->base + SP7021_PWM_MODE1);
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mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);
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if (state->duty_cycle == state->period) {
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/* PWM channel output = high */
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mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);
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duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX;
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} else {
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mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);
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/*
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* duty_ns <= period_ns 27 bits, clk_rate 28 bits, won't overflow.
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*/
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duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,
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(u64)dd_freq * NSEC_PER_SEC);
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duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty;
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}
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writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
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writel(mode1, priv->base + SP7021_PWM_MODE1);
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writel(mode0, priv->base + SP7021_PWM_MODE0);
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return 0;
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}
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static void sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sunplus_pwm *priv = to_sunplus_pwm(chip);
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u32 mode0, dd_freq, duty;
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u64 clk_rate;
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mode0 = readl(priv->base + SP7021_PWM_MODE0);
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if (mode0 & BIT(pwm->hwpwm)) {
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clk_rate = clk_get_rate(priv->clk);
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dd_freq = readl(priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
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duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
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duty = FIELD_GET(SP7021_PWM_DUTY_MASK, duty);
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/*
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* dd_freq 16 bits, SP7021_PWM_FREQ_SCALER 8 bits
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* NSEC_PER_SEC 30 bits, won't overflow.
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*/
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state->period = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)SP7021_PWM_FREQ_SCALER
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* NSEC_PER_SEC, clk_rate);
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/*
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* dd_freq 16 bits, duty 8 bits, NSEC_PER_SEC 30 bits, won't overflow.
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*/
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state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,
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clk_rate);
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state->enabled = true;
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} else {
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state->enabled = false;
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}
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state->polarity = PWM_POLARITY_NORMAL;
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}
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static const struct pwm_ops sunplus_pwm_ops = {
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.apply = sunplus_pwm_apply,
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.get_state = sunplus_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static void sunplus_pwm_clk_release(void *data)
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{
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struct clk *clk = data;
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clk_disable_unprepare(clk);
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}
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static int sunplus_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sunplus_pwm *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk))
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return dev_err_probe(dev, PTR_ERR(priv->clk),
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"get pwm clock failed\n");
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ret = clk_prepare_enable(priv->clk);
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if (ret < 0) {
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dev_err(dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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ret = devm_add_action_or_reset(dev, sunplus_pwm_clk_release, priv->clk);
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if (ret < 0) {
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dev_err(dev, "failed to release clock: %d\n", ret);
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return ret;
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}
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priv->chip.dev = dev;
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priv->chip.ops = &sunplus_pwm_ops;
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priv->chip.npwm = SP7021_PWM_NUM;
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ret = devm_pwmchip_add(dev, &priv->chip);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Cannot register sunplus PWM\n");
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return 0;
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}
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static const struct of_device_id sunplus_pwm_of_match[] = {
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{ .compatible = "sunplus,sp7021-pwm", },
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{}
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};
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MODULE_DEVICE_TABLE(of, sunplus_pwm_of_match);
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static struct platform_driver sunplus_pwm_driver = {
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.probe = sunplus_pwm_probe,
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.driver = {
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.name = "sunplus-pwm",
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.of_match_table = sunplus_pwm_of_match,
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},
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};
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module_platform_driver(sunplus_pwm_driver);
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MODULE_DESCRIPTION("Sunplus SoC PWM Driver");
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MODULE_AUTHOR("Hammer Hsieh <hammerh0314@gmail.com>");
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MODULE_LICENSE("GPL");
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