2018-12-12 01:57:48 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2014-05-15 21:40:25 +08:00
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/*
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* Copyright (C) 2014 Intel Corporation
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*
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* Adjustable fractional divider clock implementation.
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2015-09-22 23:54:11 +08:00
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* Uses rational best approximation algorithm.
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2021-08-13 01:00:25 +08:00
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*
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* Output is calculated as
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*
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* rate = (m / n) * parent_rate (1)
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*
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* This is useful when we have a prescaler block which asks for
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* m (numerator) and n (denominator) values to be provided to satisfy
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* the (1) as much as possible.
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*
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* Since m and n have the limitation by a range, e.g.
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*
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* n >= 1, n < N_width, where N_width = 2^nwidth (2)
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*
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* for some cases the output may be saturated. Hence, from (1) and (2),
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* assuming the worst case when m = 1, the inequality
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*
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* floor(log2(parent_rate / rate)) <= nwidth (3)
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*
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* may be derived. Thus, in cases when
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*
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* (parent_rate / rate) >> N_width (4)
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*
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* we might scale up the rate by 2^scale (see the description of
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* CLK_FRAC_DIVIDER_POWER_OF_TWO_PS for additional information), where
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*
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* scale = floor(log2(parent_rate / rate)) - nwidth (5)
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*
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* and assume that the IP, that needs m and n, has also its own
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* prescaler, which is capable to divide by 2^scale. In this way
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* we get the denominator to satisfy the desired range (2) and
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2022-02-23 03:51:53 +08:00
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* at the same time a much better result of m and n than simple
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2021-08-13 01:00:25 +08:00
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* saturated values.
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2014-05-15 21:40:25 +08:00
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*/
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#include <linux/clk-provider.h>
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2019-04-19 06:20:22 +08:00
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#include <linux/io.h>
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2014-05-15 21:40:25 +08:00
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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2015-09-22 23:54:11 +08:00
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#include <linux/rational.h>
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2014-05-15 21:40:25 +08:00
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2021-08-13 01:00:22 +08:00
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#include "clk-fractional-divider.h"
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2019-04-18 19:12:05 +08:00
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static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
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{
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if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
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return ioread32be(fd->reg);
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2019-04-18 19:12:11 +08:00
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return readl(fd->reg);
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2019-04-18 19:12:05 +08:00
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}
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static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
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{
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if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
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iowrite32be(val, fd->reg);
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else
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2019-04-18 19:12:11 +08:00
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writel(val, fd->reg);
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2019-04-18 19:12:05 +08:00
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}
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2014-05-15 21:40:25 +08:00
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static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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2015-09-22 23:54:11 +08:00
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unsigned long m, n;
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u32 val;
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2014-05-15 21:40:25 +08:00
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u64 ret;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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2015-07-25 03:21:12 +08:00
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else
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__acquire(fd->lock);
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2014-05-15 21:40:25 +08:00
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2019-04-18 19:12:05 +08:00
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val = clk_fd_readl(fd);
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2014-05-15 21:40:25 +08:00
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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2015-07-25 03:21:12 +08:00
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else
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__release(fd->lock);
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2014-05-15 21:40:25 +08:00
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m = (val & fd->mmask) >> fd->mshift;
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n = (val & fd->nmask) >> fd->nshift;
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2018-11-14 21:01:39 +08:00
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if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
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m++;
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n++;
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}
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2015-02-02 21:37:04 +08:00
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if (!n || !m)
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return parent_rate;
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2014-08-28 18:46:10 +08:00
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ret = (u64)parent_rate * m;
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2014-05-15 21:40:25 +08:00
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do_div(ret, n);
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return ret;
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}
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2021-08-13 01:00:22 +08:00
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void clk_fractional_divider_general_approximation(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate,
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unsigned long *m, unsigned long *n)
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2014-05-15 21:40:25 +08:00
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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2015-09-22 23:54:11 +08:00
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/*
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* Get rate closer to *parent_rate to guarantee there is no overflow
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* for m and n. In the result it will be the nearest rate left shifted
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* by (scale - fd->nwidth) bits.
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2021-08-13 01:00:25 +08:00
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*
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* For the detailed explanation see the top comment in this file.
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2015-09-22 23:54:11 +08:00
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*/
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2021-08-13 01:00:24 +08:00
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if (fd->flags & CLK_FRAC_DIVIDER_POWER_OF_TWO_PS) {
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unsigned long scale = fls_long(*parent_rate / rate - 1);
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if (scale > fd->nwidth)
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rate <<= scale - fd->nwidth;
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}
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2014-05-15 21:40:25 +08:00
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2015-09-22 23:54:11 +08:00
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rational_best_approximation(rate, *parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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2017-08-02 00:21:22 +08:00
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m, n);
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}
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static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long m, n;
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u64 ret;
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clk: fractional-divider: check parent rate only if flag is set
Custom approximation of fractional-divider may not need parent clock
rate checking. For example Rockchip SoCs work fine using grand parent
clock rate even if target rate is greater than parent.
This patch checks parent clock rate only if CLK_SET_RATE_PARENT flag
is set.
For detailed example, clock tree of Rockchip I2S audio hardware.
- Clock rate of CPLL is 1.2GHz, GPLL is 491.52MHz.
- i2s1_div is integer divider can divide N (N is 1~128).
Input clock is CPLL or GPLL. Initial divider value is N = 1.
Ex) PLL = CPLL, N = 10, i2s1_div output rate is
CPLL / 10 = 1.2GHz / 10 = 120MHz
- i2s1_frac is fractional divider can divide input to x/y, x and
y are 16bit integer.
CPLL --> | selector | ---> i2s1_div -+--> | selector | --> I2S1 MCLK
GPLL --> | | ,--------------' | |
`--> i2s1_frac ---> | |
Clock mux system try to choose suitable one from i2s1_div and
i2s1_frac for master clock (MCLK) of I2S1.
Bad scenario as follows:
- Try to set MCLK to 8.192MHz (32kHz audio replay)
Candidate setting is
- i2s1_div: GPLL / 60 = 8.192MHz
i2s1_div candidate is exactly same as target clock rate, so mux
choose this clock source. i2s1_div output rate is changed
491.52MHz -> 8.192MHz
- After that try to set to 11.2896MHz (44.1kHz audio replay)
Candidate settings are
- i2s1_div : CPLL / 107 = 11.214945MHz
- i2s1_frac: i2s1_div = 8.192MHz
This is because clk_fd_round_rate() thinks target rate
(11.2896MHz) is higher than parent rate (i2s1_div = 8.192MHz)
and returns parent clock rate.
Above is current upstreamed behavior. Clock mux system choose
i2s1_div, but this clock rate is not acceptable for I2S driver, so
users cannot replay audio.
Expected behavior is:
- Try to set master clock to 11.2896MHz (44.1kHz audio replay)
Candidate settings are
- i2s1_div : CPLL / 107 = 11.214945MHz
- i2s1_frac: i2s1_div * 147/6400 = 11.2896MHz
Change i2s1_div to GPLL / 1 = 491.52MHz at same
time.
If apply this commit, clk_fd_round_rate() calls custom approximate
function of Rockchip even if target rate is higher than parent.
Custom function changes both grand parent (i2s1_div) and parent
(i2s_frac) settings at same time. Clock mux system can choose
i2s1_frac and audio works fine.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@kernel.org: Make function into a macro instead]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-10 23:38:06 +08:00
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if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate))
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2017-08-02 00:21:22 +08:00
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return *parent_rate;
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if (fd->approximation)
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fd->approximation(hw, rate, parent_rate, &m, &n);
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else
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2021-08-13 01:00:22 +08:00
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clk_fractional_divider_general_approximation(hw, rate, parent_rate, &m, &n);
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2014-05-15 21:40:25 +08:00
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2015-09-22 23:54:11 +08:00
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ret = (u64)*parent_rate * m;
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do_div(ret, n);
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return ret;
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2014-05-15 21:40:25 +08:00
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}
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static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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2015-09-22 23:54:11 +08:00
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unsigned long m, n;
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2014-05-15 21:40:25 +08:00
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u32 val;
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2015-09-22 23:54:11 +08:00
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rational_best_approximation(rate, parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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&m, &n);
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2014-05-15 21:40:25 +08:00
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2018-11-14 21:01:39 +08:00
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if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
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m--;
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n--;
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}
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2014-05-15 21:40:25 +08:00
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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2015-07-25 03:21:12 +08:00
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else
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__acquire(fd->lock);
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2014-05-15 21:40:25 +08:00
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2019-04-18 19:12:05 +08:00
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val = clk_fd_readl(fd);
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2014-05-15 21:40:25 +08:00
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val &= ~(fd->mmask | fd->nmask);
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val |= (m << fd->mshift) | (n << fd->nshift);
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2019-04-18 19:12:05 +08:00
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clk_fd_writel(fd, val);
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2014-05-15 21:40:25 +08:00
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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2015-07-25 03:21:12 +08:00
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else
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__release(fd->lock);
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2014-05-15 21:40:25 +08:00
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return 0;
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}
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const struct clk_ops clk_fractional_divider_ops = {
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.recalc_rate = clk_fd_recalc_rate,
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.round_rate = clk_fd_round_rate,
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.set_rate = clk_fd_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
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2016-02-07 16:15:09 +08:00
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struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
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2014-05-15 21:40:25 +08:00
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_fractional_divider *fd;
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struct clk_init_data init;
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2016-02-07 16:15:09 +08:00
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struct clk_hw *hw;
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int ret;
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2014-05-15 21:40:25 +08:00
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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2015-05-15 07:47:10 +08:00
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if (!fd)
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2014-05-15 21:40:25 +08:00
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_fractional_divider_ops;
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2019-04-26 01:57:37 +08:00
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init.flags = flags;
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2014-05-15 21:40:25 +08:00
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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fd->reg = reg;
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fd->mshift = mshift;
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2015-09-22 23:54:09 +08:00
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fd->mwidth = mwidth;
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fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
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2014-05-15 21:40:25 +08:00
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fd->nshift = nshift;
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2015-09-22 23:54:09 +08:00
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fd->nwidth = nwidth;
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fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
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2014-05-15 21:40:25 +08:00
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fd->flags = clk_divider_flags;
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fd->lock = lock;
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fd->hw.init = &init;
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2016-02-07 16:15:09 +08:00
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hw = &fd->hw;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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2014-05-15 21:40:25 +08:00
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kfree(fd);
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2016-02-07 16:15:09 +08:00
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
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2014-05-15 21:40:25 +08:00
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2016-02-07 16:15:09 +08:00
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struct clk *clk_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
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reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
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lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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2014-05-15 21:40:25 +08:00
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}
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EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
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2016-02-07 16:15:09 +08:00
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void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
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{
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struct clk_fractional_divider *fd;
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fd = to_clk_fd(hw);
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clk_hw_unregister(hw);
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kfree(fd);
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}
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