2012-10-26 00:41:39 +08:00
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/*
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* Copyright 2012 Pavel Machek <pavel@denx.de>
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2015-06-05 21:24:52 +08:00
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* Copyright (C) 2012-2015 Altera Corporation
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2012-10-26 00:41:39 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __MACH_CORE_H
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#define __MACH_CORE_H
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2013-04-11 23:55:24 +08:00
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#define SOCFPGA_RSTMGR_CTRL 0x04
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2014-10-15 03:33:38 +08:00
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#define SOCFPGA_RSTMGR_MODMPURST 0x10
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2013-04-11 23:55:24 +08:00
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#define SOCFPGA_RSTMGR_MODPERRST 0x14
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#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
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2015-07-21 00:23:13 +08:00
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#define SOCFPGA_A10_RSTMGR_CTRL 0xC
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2015-06-03 10:14:02 +08:00
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#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
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2013-04-11 23:55:24 +08:00
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/* System Manager bits */
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#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
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#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
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2014-10-15 03:33:38 +08:00
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#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
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2012-10-26 00:41:39 +08:00
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extern void socfpga_init_clocks(void);
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extern void socfpga_sysmgr_init(void);
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2016-02-11 03:26:23 +08:00
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void socfpga_init_l2_ecc(void);
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2016-02-11 03:26:24 +08:00
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void socfpga_init_ocram_ecc(void);
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2016-03-22 00:01:45 +08:00
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void socfpga_init_arria10_l2_ecc(void);
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2016-04-12 01:01:34 +08:00
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void socfpga_init_arria10_ocram_ecc(void);
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2012-10-26 00:41:39 +08:00
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2013-04-11 23:55:24 +08:00
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extern void __iomem *sys_manager_base_addr;
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extern void __iomem *rst_manager_base_addr;
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2015-06-05 21:24:52 +08:00
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extern void __iomem *sdr_ctl_base_addr;
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u32 socfpga_sdram_self_refresh(u32 sdr_base);
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extern unsigned int socfpga_sdram_self_refresh_sz;
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2013-04-11 23:55:24 +08:00
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2012-10-26 00:41:39 +08:00
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extern char secondary_trampoline, secondary_trampoline_end;
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arm: socfpga: fix fetching cpu1start_addr for SMP
When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will
only be able to use physical addresses. For systems with that have the
MMU page configured for 0xC0000000, 0x80000000, or 0x40000000
"BIC 0x40000000" will work just fine, as it was just converting the
virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000
became 0x80000000. So for systems where the SDRAM controller was able to do a
wrap-around access, this was working fine, as it was just dropping the MSB,
but for systems where out of bounds memory access is not allowed, this would
not allow CPU1 to correctly fetch &cpu1start_addr.
This patch fixes the secondary_trampoline code to correctly fetch the
physical address of cpu1start_addr directly. The patch will subtract the
correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the
physical memory will always start at 0x0, subtracting PAGE_OFFSET from
&cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr.
While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr
to avoid any future naming collisions for multiplatform image.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and
add comments to the same effect.
v3: Used PAGE_OFFSET to get the physical address
v2: Correctly get the physical address instead of just a BIC hack.
2014-10-01 18:44:48 +08:00
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extern unsigned long socfpga_cpu1start_addr;
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2013-02-12 07:30:33 +08:00
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2015-02-12 02:34:25 +08:00
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#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
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2012-10-26 00:41:39 +08:00
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#endif
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