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OpenCloudOS-Kernel/drivers/usb/dwc3/debugfs.c

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USB: add SPDX identifiers to all remaining files in drivers/usb/ It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the drivers/usb/ and include/linux/usb* files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kate Stewart <kstewart@linuxfoundation.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Acked-by: Johan Hovold <johan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-03 18:28:30 +08:00
// SPDX-License-Identifier: GPL-2.0
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
/**
* debugfs.c - DesignWare USB3 DRD Controller DebugFS file
*
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/ptrace.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/delay.h>
usb: dwc3: fix few coding style problems There were a few coding style issues with this driver which are now fixed: drivers/usb/dwc3/debugfs.c:48: WARNING: Use #include \ <linux/uaccess.h> instead of <asm/uaccess.h> drivers/usb/dwc3/debugfs.c:484: ERROR: space required \ before the open brace '{' drivers/usb/dwc3/ep0.c:261: WARNING: line over 80 characters drivers/usb/dwc3/ep0.c:287: WARNING: suspect code indent \ for conditional statements (16, 23) drivers/usb/dwc3/gadget.c:749: WARNING: line over 80 characters drivers/usb/dwc3/gadget.c:1267: WARNING: line over 80 characters drivers/usb/dwc3/gadget.h:116: WARNING: line over 80 characters drivers/usb/dwc3/io.h:42: WARNING: Use #include \ <linux/io.h> instead of <asm/io.h> Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-11-04 18:32:47 +08:00
#include <linux/uaccess.h>
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
usb: dwc3: gadget: allow testmodes changes via debugfs This is very useful for low level Link Testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 00:38:30 +08:00
#include <linux/usb/ch9.h>
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
#include "core.h"
#include "gadget.h"
#include "io.h"
usb: dwc3: fix sparse errors sparse caught three mistakes on this driver, fix them: drivers/usb/dwc3/ep0.c:806:29: warning: duplicate const drivers/usb/dwc3/debugfs.c:481:15: warning: symbol 'dwc3_debugfs_init' \ was not declared. Should it be static? drivers/usb/dwc3/debugfs.c:518:16: warning: symbol 'dwc3_debugfs_exit' \ was not declared. Should it be static? Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-11-04 18:40:05 +08:00
#include "debug.h"
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
#define DWC3_LSP_MUX_UNSELECTED 0xfffff
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
#define dump_register(nm) \
{ \
.name = __stringify(nm), \
usb: dwc3: gadget: add a pointer to endpoint registers By adding a pointer to endpoint registers' base address, we can avoid using our controller-wide struct dwc3 pointer for everything. At some point this will allow us to have per-endpoint locks which will, in turn, let us queue requests to separate endpoints in parallel. Because of this change our debugfs interface and io accessors need to be changed accordingly. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 21:53:39 +08:00
.offset = DWC3_ ##nm, \
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
}
usb: dwc3: gadget: add a pointer to endpoint registers By adding a pointer to endpoint registers' base address, we can avoid using our controller-wide struct dwc3 pointer for everything. At some point this will allow us to have per-endpoint locks which will, in turn, let us queue requests to separate endpoints in parallel. Because of this change our debugfs interface and io accessors need to be changed accordingly. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 21:53:39 +08:00
#define dump_ep_register_set(n) \
{ \
.name = "DEPCMDPAR2("__stringify(n)")", \
.offset = DWC3_DEP_BASE(n) + \
DWC3_DEPCMDPAR2, \
}, \
{ \
.name = "DEPCMDPAR1("__stringify(n)")", \
.offset = DWC3_DEP_BASE(n) + \
DWC3_DEPCMDPAR1, \
}, \
{ \
.name = "DEPCMDPAR0("__stringify(n)")", \
.offset = DWC3_DEP_BASE(n) + \
DWC3_DEPCMDPAR0, \
}, \
{ \
.name = "DEPCMD("__stringify(n)")", \
.offset = DWC3_DEP_BASE(n) + \
DWC3_DEPCMD, \
}
usb: dwc3: debugfs: mark our regset structure const nobody should be modifying that structure and debugfs has already being fixed to take const arguments, so we won't cause any new compile warnings. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-02-22 22:17:31 +08:00
static const struct debugfs_reg32 dwc3_regs[] = {
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
dump_register(GSBUSCFG0),
dump_register(GSBUSCFG1),
dump_register(GTXTHRCFG),
dump_register(GRXTHRCFG),
dump_register(GCTL),
dump_register(GEVTEN),
dump_register(GSTS),
usb: dwc3: add DWC3_GUCTL1 reg for debug GUCTL1 reg has some useful functions which can be written by user. For rockchip platform, we set GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK (bit26, applicable for the core is programmed to operate in 2.0 device only) to 1 in bootrom, and after start the kernel, we want to check whether this bit can be reset to default 0 after the core reset. Dump GUCTL1 reg from debugfs is more convenient for us. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-05-13 18:13:46 +08:00
dump_register(GUCTL1),
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
dump_register(GSNPSID),
dump_register(GGPIO),
dump_register(GUID),
dump_register(GUCTL),
dump_register(GBUSERRADDR0),
dump_register(GBUSERRADDR1),
dump_register(GPRTBIMAP0),
dump_register(GPRTBIMAP1),
dump_register(GHWPARAMS0),
dump_register(GHWPARAMS1),
dump_register(GHWPARAMS2),
dump_register(GHWPARAMS3),
dump_register(GHWPARAMS4),
dump_register(GHWPARAMS5),
dump_register(GHWPARAMS6),
dump_register(GHWPARAMS7),
dump_register(GDBGFIFOSPACE),
dump_register(GDBGLTSSM),
usb: dwc3: Dump LSP and BMU debug info Dump LSP and BMU debug info. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-17 06:35:51 +08:00
dump_register(GDBGBMU),
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
dump_register(GPRTBIMAP_HS0),
dump_register(GPRTBIMAP_HS1),
dump_register(GPRTBIMAP_FS0),
dump_register(GPRTBIMAP_FS1),
dump_register(GUSB2PHYCFG(0)),
dump_register(GUSB2PHYCFG(1)),
dump_register(GUSB2PHYCFG(2)),
dump_register(GUSB2PHYCFG(3)),
dump_register(GUSB2PHYCFG(4)),
dump_register(GUSB2PHYCFG(5)),
dump_register(GUSB2PHYCFG(6)),
dump_register(GUSB2PHYCFG(7)),
dump_register(GUSB2PHYCFG(8)),
dump_register(GUSB2PHYCFG(9)),
dump_register(GUSB2PHYCFG(10)),
dump_register(GUSB2PHYCFG(11)),
dump_register(GUSB2PHYCFG(12)),
dump_register(GUSB2PHYCFG(13)),
dump_register(GUSB2PHYCFG(14)),
dump_register(GUSB2PHYCFG(15)),
dump_register(GUSB2I2CCTL(0)),
dump_register(GUSB2I2CCTL(1)),
dump_register(GUSB2I2CCTL(2)),
dump_register(GUSB2I2CCTL(3)),
dump_register(GUSB2I2CCTL(4)),
dump_register(GUSB2I2CCTL(5)),
dump_register(GUSB2I2CCTL(6)),
dump_register(GUSB2I2CCTL(7)),
dump_register(GUSB2I2CCTL(8)),
dump_register(GUSB2I2CCTL(9)),
dump_register(GUSB2I2CCTL(10)),
dump_register(GUSB2I2CCTL(11)),
dump_register(GUSB2I2CCTL(12)),
dump_register(GUSB2I2CCTL(13)),
dump_register(GUSB2I2CCTL(14)),
dump_register(GUSB2I2CCTL(15)),
dump_register(GUSB2PHYACC(0)),
dump_register(GUSB2PHYACC(1)),
dump_register(GUSB2PHYACC(2)),
dump_register(GUSB2PHYACC(3)),
dump_register(GUSB2PHYACC(4)),
dump_register(GUSB2PHYACC(5)),
dump_register(GUSB2PHYACC(6)),
dump_register(GUSB2PHYACC(7)),
dump_register(GUSB2PHYACC(8)),
dump_register(GUSB2PHYACC(9)),
dump_register(GUSB2PHYACC(10)),
dump_register(GUSB2PHYACC(11)),
dump_register(GUSB2PHYACC(12)),
dump_register(GUSB2PHYACC(13)),
dump_register(GUSB2PHYACC(14)),
dump_register(GUSB2PHYACC(15)),
dump_register(GUSB3PIPECTL(0)),
dump_register(GUSB3PIPECTL(1)),
dump_register(GUSB3PIPECTL(2)),
dump_register(GUSB3PIPECTL(3)),
dump_register(GUSB3PIPECTL(4)),
dump_register(GUSB3PIPECTL(5)),
dump_register(GUSB3PIPECTL(6)),
dump_register(GUSB3PIPECTL(7)),
dump_register(GUSB3PIPECTL(8)),
dump_register(GUSB3PIPECTL(9)),
dump_register(GUSB3PIPECTL(10)),
dump_register(GUSB3PIPECTL(11)),
dump_register(GUSB3PIPECTL(12)),
dump_register(GUSB3PIPECTL(13)),
dump_register(GUSB3PIPECTL(14)),
dump_register(GUSB3PIPECTL(15)),
dump_register(GTXFIFOSIZ(0)),
dump_register(GTXFIFOSIZ(1)),
dump_register(GTXFIFOSIZ(2)),
dump_register(GTXFIFOSIZ(3)),
dump_register(GTXFIFOSIZ(4)),
dump_register(GTXFIFOSIZ(5)),
dump_register(GTXFIFOSIZ(6)),
dump_register(GTXFIFOSIZ(7)),
dump_register(GTXFIFOSIZ(8)),
dump_register(GTXFIFOSIZ(9)),
dump_register(GTXFIFOSIZ(10)),
dump_register(GTXFIFOSIZ(11)),
dump_register(GTXFIFOSIZ(12)),
dump_register(GTXFIFOSIZ(13)),
dump_register(GTXFIFOSIZ(14)),
dump_register(GTXFIFOSIZ(15)),
dump_register(GTXFIFOSIZ(16)),
dump_register(GTXFIFOSIZ(17)),
dump_register(GTXFIFOSIZ(18)),
dump_register(GTXFIFOSIZ(19)),
dump_register(GTXFIFOSIZ(20)),
dump_register(GTXFIFOSIZ(21)),
dump_register(GTXFIFOSIZ(22)),
dump_register(GTXFIFOSIZ(23)),
dump_register(GTXFIFOSIZ(24)),
dump_register(GTXFIFOSIZ(25)),
dump_register(GTXFIFOSIZ(26)),
dump_register(GTXFIFOSIZ(27)),
dump_register(GTXFIFOSIZ(28)),
dump_register(GTXFIFOSIZ(29)),
dump_register(GTXFIFOSIZ(30)),
dump_register(GTXFIFOSIZ(31)),
dump_register(GRXFIFOSIZ(0)),
dump_register(GRXFIFOSIZ(1)),
dump_register(GRXFIFOSIZ(2)),
dump_register(GRXFIFOSIZ(3)),
dump_register(GRXFIFOSIZ(4)),
dump_register(GRXFIFOSIZ(5)),
dump_register(GRXFIFOSIZ(6)),
dump_register(GRXFIFOSIZ(7)),
dump_register(GRXFIFOSIZ(8)),
dump_register(GRXFIFOSIZ(9)),
dump_register(GRXFIFOSIZ(10)),
dump_register(GRXFIFOSIZ(11)),
dump_register(GRXFIFOSIZ(12)),
dump_register(GRXFIFOSIZ(13)),
dump_register(GRXFIFOSIZ(14)),
dump_register(GRXFIFOSIZ(15)),
dump_register(GRXFIFOSIZ(16)),
dump_register(GRXFIFOSIZ(17)),
dump_register(GRXFIFOSIZ(18)),
dump_register(GRXFIFOSIZ(19)),
dump_register(GRXFIFOSIZ(20)),
dump_register(GRXFIFOSIZ(21)),
dump_register(GRXFIFOSIZ(22)),
dump_register(GRXFIFOSIZ(23)),
dump_register(GRXFIFOSIZ(24)),
dump_register(GRXFIFOSIZ(25)),
dump_register(GRXFIFOSIZ(26)),
dump_register(GRXFIFOSIZ(27)),
dump_register(GRXFIFOSIZ(28)),
dump_register(GRXFIFOSIZ(29)),
dump_register(GRXFIFOSIZ(30)),
dump_register(GRXFIFOSIZ(31)),
dump_register(GEVNTADRLO(0)),
dump_register(GEVNTADRHI(0)),
dump_register(GEVNTSIZ(0)),
dump_register(GEVNTCOUNT(0)),
dump_register(GHWPARAMS8),
dump_register(DCFG),
dump_register(DCTL),
dump_register(DEVTEN),
dump_register(DSTS),
dump_register(DGCMDPAR),
dump_register(DGCMD),
dump_register(DALEPENA),
usb: dwc3: gadget: add a pointer to endpoint registers By adding a pointer to endpoint registers' base address, we can avoid using our controller-wide struct dwc3 pointer for everything. At some point this will allow us to have per-endpoint locks which will, in turn, let us queue requests to separate endpoints in parallel. Because of this change our debugfs interface and io accessors need to be changed accordingly. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 21:53:39 +08:00
dump_ep_register_set(0),
dump_ep_register_set(1),
dump_ep_register_set(2),
dump_ep_register_set(3),
dump_ep_register_set(4),
dump_ep_register_set(5),
dump_ep_register_set(6),
dump_ep_register_set(7),
dump_ep_register_set(8),
dump_ep_register_set(9),
dump_ep_register_set(10),
dump_ep_register_set(11),
dump_ep_register_set(12),
dump_ep_register_set(13),
dump_ep_register_set(14),
dump_ep_register_set(15),
dump_ep_register_set(16),
dump_ep_register_set(17),
dump_ep_register_set(18),
dump_ep_register_set(19),
dump_ep_register_set(20),
dump_ep_register_set(21),
dump_ep_register_set(22),
dump_ep_register_set(23),
dump_ep_register_set(24),
dump_ep_register_set(25),
dump_ep_register_set(26),
dump_ep_register_set(27),
dump_ep_register_set(28),
dump_ep_register_set(29),
dump_ep_register_set(30),
dump_ep_register_set(31),
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
dump_register(OCFG),
dump_register(OCTL),
usb: dwc3: core: fix wrong OTG event regitser offset This patch fixes the wrong OTG_EVT,OTG_EVTEN and OTG_STS register offsets. While at that, also add a missing register to debugfs regdump utility. Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-03-14 18:35:24 +08:00
dump_register(OEVT),
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
dump_register(OEVTEN),
dump_register(OSTS),
};
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
static void dwc3_host_lsp(struct seq_file *s)
{
struct dwc3 *dwc = s->private;
bool dbc_enabled;
u32 sel;
u32 reg;
u32 val;
dbc_enabled = !!(dwc->hwparams.hwparams1 & DWC3_GHWPARAMS1_ENDBC);
sel = dwc->dbg_lsp_select;
if (sel == DWC3_LSP_MUX_UNSELECTED) {
seq_puts(s, "Write LSP selection to print for host\n");
return;
}
reg = DWC3_GDBGLSPMUX_HOSTSELECT(sel);
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", sel, val);
if (dbc_enabled && sel < 256) {
reg |= DWC3_GDBGLSPMUX_ENDBC;
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
seq_printf(s, "GDBGLSP_DBC[%d] = 0x%08x\n", sel, val);
}
}
static void dwc3_gadget_lsp(struct seq_file *s)
{
struct dwc3 *dwc = s->private;
int i;
u32 reg;
for (i = 0; i < 16; i++) {
reg = DWC3_GDBGLSPMUX_DEVSELECT(i);
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", i, reg);
}
}
static int dwc3_lsp_show(struct seq_file *s, void *unused)
{
struct dwc3 *dwc = s->private;
unsigned int current_mode;
unsigned long flags;
u32 reg;
spin_lock_irqsave(&dwc->lock, flags);
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
current_mode = DWC3_GSTS_CURMOD(reg);
switch (current_mode) {
case DWC3_GSTS_CURMOD_HOST:
dwc3_host_lsp(s);
break;
case DWC3_GSTS_CURMOD_DEVICE:
dwc3_gadget_lsp(s);
break;
default:
seq_puts(s, "Mode is unknown, no LSP register printed\n");
break;
}
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
static int dwc3_lsp_open(struct inode *inode, struct file *file)
{
return single_open(file, dwc3_lsp_show, inode->i_private);
}
static ssize_t dwc3_lsp_write(struct file *file, const char __user *ubuf,
size_t count, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct dwc3 *dwc = s->private;
unsigned long flags;
char buf[32] = { 0 };
u32 sel;
int ret;
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
ret = kstrtouint(buf, 0, &sel);
if (ret)
return ret;
spin_lock_irqsave(&dwc->lock, flags);
dwc->dbg_lsp_select = sel;
spin_unlock_irqrestore(&dwc->lock, flags);
return count;
}
static const struct file_operations dwc3_lsp_fops = {
.open = dwc3_lsp_open,
.write = dwc3_lsp_write,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
static int dwc3_mode_show(struct seq_file *s, void *unused)
{
struct dwc3 *dwc = s->private;
unsigned long flags;
u32 reg;
spin_lock_irqsave(&dwc->lock, flags);
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
spin_unlock_irqrestore(&dwc->lock, flags);
switch (DWC3_GCTL_PRTCAP(reg)) {
case DWC3_GCTL_PRTCAP_HOST:
seq_printf(s, "host\n");
break;
case DWC3_GCTL_PRTCAP_DEVICE:
seq_printf(s, "device\n");
break;
case DWC3_GCTL_PRTCAP_OTG:
usb: dwc3: debugfs: downcase OTG on 'mode' file When writing, we expect the "otg" string. When showing, we return "OTG". Let's downcase that word to avoid confusion. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-03-31 19:10:40 +08:00
seq_printf(s, "otg\n");
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
break;
default:
seq_printf(s, "UNKNOWN %08x\n", DWC3_GCTL_PRTCAP(reg));
}
return 0;
}
static int dwc3_mode_open(struct inode *inode, struct file *file)
{
return single_open(file, dwc3_mode_show, inode->i_private);
}
static ssize_t dwc3_mode_write(struct file *file,
const char __user *ubuf, size_t count, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct dwc3 *dwc = s->private;
usb: dwc3: use a helper function for operation mode setting There are two where need to set operational mode: - during initialization while we decide to run in host,device or DRD mode - at runtime via the debugfs interface. This patch provides a new function which sets the operational mode and moves its initialiation to the mode switch instead in the gadget code itself. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-11-01 05:25:40 +08:00
u32 mode = 0;
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
char buf[32];
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
if (!strncmp(buf, "host", 4))
usb: dwc3: debugfs: remove unnecessary | operator Each role is mutually exclusive, the | operator is unnecessary. Remove it. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-04 16:27:57 +08:00
mode = DWC3_GCTL_PRTCAP_HOST;
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
if (!strncmp(buf, "device", 6))
usb: dwc3: debugfs: remove unnecessary | operator Each role is mutually exclusive, the | operator is unnecessary. Remove it. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-04 16:27:57 +08:00
mode = DWC3_GCTL_PRTCAP_DEVICE;
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
if (!strncmp(buf, "otg", 3))
usb: dwc3: debugfs: remove unnecessary | operator Each role is mutually exclusive, the | operator is unnecessary. Remove it. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-04 16:27:57 +08:00
mode = DWC3_GCTL_PRTCAP_OTG;
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
usb: dwc3: core: make dwc3_set_mode() work properly We can't have both Host and Peripheral roles active at the same time because of one detail on DWC3: it shares the same memory area for both Host and Peripheral registers. When swapping roles we must reinitialize the new role every time. Let's make sure this works for our debugfs interface. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-04 17:49:18 +08:00
dwc3_set_mode(dwc, mode);
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
return count;
}
static const struct file_operations dwc3_mode_fops = {
.open = dwc3_mode_open,
.write = dwc3_mode_write,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
usb: dwc3: gadget: allow testmodes changes via debugfs This is very useful for low level Link Testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 00:38:30 +08:00
static int dwc3_testmode_show(struct seq_file *s, void *unused)
{
struct dwc3 *dwc = s->private;
unsigned long flags;
u32 reg;
spin_lock_irqsave(&dwc->lock, flags);
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= DWC3_DCTL_TSTCTRL_MASK;
reg >>= 1;
spin_unlock_irqrestore(&dwc->lock, flags);
switch (reg) {
case 0:
seq_printf(s, "no test\n");
break;
case TEST_J:
seq_printf(s, "test_j\n");
break;
case TEST_K:
seq_printf(s, "test_k\n");
break;
case TEST_SE0_NAK:
seq_printf(s, "test_se0_nak\n");
break;
case TEST_PACKET:
seq_printf(s, "test_packet\n");
break;
case TEST_FORCE_EN:
seq_printf(s, "test_force_enable\n");
break;
default:
seq_printf(s, "UNKNOWN %d\n", reg);
}
return 0;
}
static int dwc3_testmode_open(struct inode *inode, struct file *file)
{
return single_open(file, dwc3_testmode_show, inode->i_private);
}
static ssize_t dwc3_testmode_write(struct file *file,
const char __user *ubuf, size_t count, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct dwc3 *dwc = s->private;
unsigned long flags;
u32 testmode = 0;
char buf[32];
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
if (!strncmp(buf, "test_j", 6))
testmode = TEST_J;
else if (!strncmp(buf, "test_k", 6))
testmode = TEST_K;
usb: dwc3: debugfs: fix off by one when entering testmode When implementing the USB2 testmode support via debugfs, Felipe has committed a mistake when counting the number of letters of some of the strings, resulting on an off by one error which prevented some of the Test modes to be entered properly. This patch, fixes that mistake. Signed-off-by: Gerard Cauvy <g-cauvy1@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-02-10 18:14:53 +08:00
else if (!strncmp(buf, "test_se0_nak", 12))
usb: dwc3: gadget: allow testmodes changes via debugfs This is very useful for low level Link Testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 00:38:30 +08:00
testmode = TEST_SE0_NAK;
usb: dwc3: debugfs: fix off by one when entering testmode When implementing the USB2 testmode support via debugfs, Felipe has committed a mistake when counting the number of letters of some of the strings, resulting on an off by one error which prevented some of the Test modes to be entered properly. This patch, fixes that mistake. Signed-off-by: Gerard Cauvy <g-cauvy1@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-02-10 18:14:53 +08:00
else if (!strncmp(buf, "test_packet", 11))
usb: dwc3: gadget: allow testmodes changes via debugfs This is very useful for low level Link Testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 00:38:30 +08:00
testmode = TEST_PACKET;
usb: dwc3: debugfs: fix off by one when entering testmode When implementing the USB2 testmode support via debugfs, Felipe has committed a mistake when counting the number of letters of some of the strings, resulting on an off by one error which prevented some of the Test modes to be entered properly. This patch, fixes that mistake. Signed-off-by: Gerard Cauvy <g-cauvy1@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-02-10 18:14:53 +08:00
else if (!strncmp(buf, "test_force_enable", 17))
usb: dwc3: gadget: allow testmodes changes via debugfs This is very useful for low level Link Testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 00:38:30 +08:00
testmode = TEST_FORCE_EN;
else
testmode = 0;
spin_lock_irqsave(&dwc->lock, flags);
dwc3_gadget_set_test_mode(dwc, testmode);
spin_unlock_irqrestore(&dwc->lock, flags);
return count;
}
static const struct file_operations dwc3_testmode_fops = {
.open = dwc3_testmode_open,
.write = dwc3_testmode_write,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
static int dwc3_link_state_show(struct seq_file *s, void *unused)
{
struct dwc3 *dwc = s->private;
unsigned long flags;
enum dwc3_link_state state;
u32 reg;
usb: dwc3: debugfs: Properly print/set link state for HS Highspeed device and below has different state names than superspeed and higher. Add proper checks and printouts of link states for highspeed and below. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:19 +08:00
u8 speed;
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
spin_lock_irqsave(&dwc->lock, flags);
usb: dwc3: debugfs: Print/set link state for peripheral mode Current implementation only prints/sets the link state for peripheral mode only. Check and prevent printing bogus link state if the current mode of operation is not peripheral. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:56:23 +08:00
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {
seq_puts(s, "Not available\n");
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
state = DWC3_DSTS_USBLNKST(reg);
usb: dwc3: debugfs: Properly print/set link state for HS Highspeed device and below has different state names than superspeed and higher. Add proper checks and printouts of link states for highspeed and below. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:19 +08:00
speed = reg & DWC3_DSTS_CONNECTSPD;
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
usb: dwc3: debugfs: Properly print/set link state for HS Highspeed device and below has different state names than superspeed and higher. Add proper checks and printouts of link states for highspeed and below. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:19 +08:00
seq_printf(s, "%s\n", (speed >= DWC3_DSTS_SUPERSPEED) ?
dwc3_gadget_link_string(state) :
dwc3_gadget_hs_link_string(state));
spin_unlock_irqrestore(&dwc->lock, flags);
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
return 0;
}
static int dwc3_link_state_open(struct inode *inode, struct file *file)
{
return single_open(file, dwc3_link_state_show, inode->i_private);
}
static ssize_t dwc3_link_state_write(struct file *file,
const char __user *ubuf, size_t count, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct dwc3 *dwc = s->private;
unsigned long flags;
enum dwc3_link_state state = 0;
char buf[32];
usb: dwc3: debugfs: Properly print/set link state for HS Highspeed device and below has different state names than superspeed and higher. Add proper checks and printouts of link states for highspeed and below. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:19 +08:00
u32 reg;
u8 speed;
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
if (!strncmp(buf, "SS.Disabled", 11))
state = DWC3_LINK_STATE_SS_DIS;
else if (!strncmp(buf, "Rx.Detect", 9))
state = DWC3_LINK_STATE_RX_DET;
else if (!strncmp(buf, "SS.Inactive", 11))
state = DWC3_LINK_STATE_SS_INACT;
else if (!strncmp(buf, "Recovery", 8))
state = DWC3_LINK_STATE_RECOV;
else if (!strncmp(buf, "Compliance", 10))
state = DWC3_LINK_STATE_CMPLY;
else if (!strncmp(buf, "Loopback", 8))
state = DWC3_LINK_STATE_LPBK;
else
return -EINVAL;
spin_lock_irqsave(&dwc->lock, flags);
usb: dwc3: debugfs: Print/set link state for peripheral mode Current implementation only prints/sets the link state for peripheral mode only. Check and prevent printing bogus link state if the current mode of operation is not peripheral. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:56:23 +08:00
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {
spin_unlock_irqrestore(&dwc->lock, flags);
return -EINVAL;
}
usb: dwc3: debugfs: Properly print/set link state for HS Highspeed device and below has different state names than superspeed and higher. Add proper checks and printouts of link states for highspeed and below. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:19 +08:00
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
speed = reg & DWC3_DSTS_CONNECTSPD;
if (speed < DWC3_DSTS_SUPERSPEED &&
state != DWC3_LINK_STATE_RECOV) {
spin_unlock_irqrestore(&dwc->lock, flags);
return -EINVAL;
}
usb: dwc3: gadget: allow Link state changes via debugfs This is very useful for low level link testing where we might not have a USB Host stack, only a scope to verify signal integrity. Signed-off-by: Felipe Balbi <balbi@ti.com>
2012-01-03 01:25:16 +08:00
dwc3_gadget_set_link_state(dwc, state);
spin_unlock_irqrestore(&dwc->lock, flags);
return count;
}
static const struct file_operations dwc3_link_state_fops = {
.open = dwc3_link_state_open,
.write = dwc3_link_state_write,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
struct dwc3_ep_file_map {
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
const char name[25];
const struct file_operations *const fops;
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
};
usb: dwc3: debugfs: Properly name Tx/RxFIFO The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:00 +08:00
static int dwc3_tx_fifo_size_show(struct seq_file *s, void *unused)
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
usb: dwc3: debugfs: Properly name Tx/RxFIFO The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:00 +08:00
val = dwc3_core_fifo_space(dep, DWC3_TXFIFO);
usb: dwc3: debugfs: Print eps Tx/RxFIFO in bytes TxFIFO and RxFIFO from GDBGFIFOSPACE are fifo depths in MDWIDTH. Convert them into bytes for easier read. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:06 +08:00
/* Convert to bytes */
val *= DWC3_MDWIDTH(dwc->hwparams.hwparams0);
val >>= 3;
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
usb: dwc3: debugfs: Properly name Tx/RxFIFO The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:00 +08:00
static int dwc3_rx_fifo_size_show(struct seq_file *s, void *unused)
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
usb: dwc3: debugfs: Properly name Tx/RxFIFO The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:00 +08:00
val = dwc3_core_fifo_space(dep, DWC3_RXFIFO);
usb: dwc3: debugfs: Print eps Tx/RxFIFO in bytes TxFIFO and RxFIFO from GDBGFIFOSPACE are fifo depths in MDWIDTH. Convert them into bytes for easier read. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:06 +08:00
/* Convert to bytes */
val *= DWC3_MDWIDTH(dwc->hwparams.hwparams0);
val >>= 3;
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
static int dwc3_tx_request_queue_show(struct seq_file *s, void *unused)
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
val = dwc3_core_fifo_space(dep, DWC3_TXREQQ);
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
static int dwc3_rx_request_queue_show(struct seq_file *s, void *unused)
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
val = dwc3_core_fifo_space(dep, DWC3_RXREQQ);
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
static int dwc3_rx_info_queue_show(struct seq_file *s, void *unused)
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
val = dwc3_core_fifo_space(dep, DWC3_RXINFOQ);
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
static int dwc3_descriptor_fetch_queue_show(struct seq_file *s, void *unused)
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
val = dwc3_core_fifo_space(dep, DWC3_DESCFETCHQ);
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
static int dwc3_event_queue_show(struct seq_file *s, void *unused)
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&dwc->lock, flags);
val = dwc3_core_fifo_space(dep, DWC3_EVENTQ);
seq_printf(s, "%u\n", val);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
static int dwc3_transfer_type_show(struct seq_file *s, void *unused)
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
spin_lock_irqsave(&dwc->lock, flags);
if (!(dep->flags & DWC3_EP_ENABLED) ||
!dep->endpoint.desc) {
seq_printf(s, "--\n");
goto out;
}
switch (usb_endpoint_type(dep->endpoint.desc)) {
case USB_ENDPOINT_XFER_CONTROL:
seq_printf(s, "control\n");
break;
case USB_ENDPOINT_XFER_ISOC:
seq_printf(s, "isochronous\n");
break;
case USB_ENDPOINT_XFER_BULK:
seq_printf(s, "bulk\n");
break;
case USB_ENDPOINT_XFER_INT:
seq_printf(s, "interrupt\n");
break;
default:
seq_printf(s, "--\n");
}
out:
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
static int dwc3_trb_ring_show(struct seq_file *s, void *unused)
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
int i;
spin_lock_irqsave(&dwc->lock, flags);
if (dep->number <= 1) {
seq_printf(s, "--\n");
goto out;
}
seq_printf(s, "buffer_addr,size,type,ioc,isp_imi,csp,chn,lst,hwo\n");
for (i = 0; i < DWC3_TRB_NUM; i++) {
struct dwc3_trb *trb = &dep->trb_pool[i];
usb: dwc3: expose dwc3_trb_type_string() That helper can be used from our tracepoint interface with very minor edits. Let's do so. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-03-31 19:44:09 +08:00
unsigned int type = DWC3_TRBCTL_TYPE(trb->ctrl);
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
usb: dwc3: debugfs: slightly improve output of trb_ring Instead of printing out enqueue and dequeue pointer value as a header to the output, let's mark the TRBs in question with 'E' and 'D'. The output looks slightly easier to read. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-20 20:21:27 +08:00
seq_printf(s, "%08x%08x,%d,%s,%d,%d,%d,%d,%d,%d %c%c\n",
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
trb->bph, trb->bpl, trb->size,
usb: dwc3: expose dwc3_trb_type_string() That helper can be used from our tracepoint interface with very minor edits. Let's do so. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-03-31 19:44:09 +08:00
dwc3_trb_type_string(type),
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
!!(trb->ctrl & DWC3_TRB_CTRL_IOC),
!!(trb->ctrl & DWC3_TRB_CTRL_ISP_IMI),
!!(trb->ctrl & DWC3_TRB_CTRL_CSP),
!!(trb->ctrl & DWC3_TRB_CTRL_CHN),
!!(trb->ctrl & DWC3_TRB_CTRL_LST),
usb: dwc3: debugfs: slightly improve output of trb_ring Instead of printing out enqueue and dequeue pointer value as a header to the output, let's mark the TRBs in question with 'E' and 'D'. The output looks slightly easier to read. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-20 20:21:27 +08:00
!!(trb->ctrl & DWC3_TRB_CTRL_HWO),
dep->trb_enqueue == i ? 'E' : ' ',
dep->trb_dequeue == i ? 'D' : ' ');
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
}
out:
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
static int dwc3_ep_info_register_show(struct seq_file *s, void *unused)
{
struct dwc3_ep *dep = s->private;
struct dwc3 *dwc = dep->dwc;
unsigned long flags;
u64 ep_info;
u32 lower_32_bits;
u32 upper_32_bits;
u32 reg;
spin_lock_irqsave(&dwc->lock, flags);
reg = DWC3_GDBGLSPMUX_EPSELECT(dep->number);
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
lower_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO0);
upper_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1);
ep_info = ((u64)upper_32_bits << 32) | lower_32_bits;
seq_printf(s, "0x%016llx\n", ep_info);
spin_unlock_irqrestore(&dwc->lock, flags);
return 0;
}
usb: dwc3: debugfs: Properly name Tx/RxFIFO The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:00 +08:00
DEFINE_SHOW_ATTRIBUTE(dwc3_tx_fifo_size);
DEFINE_SHOW_ATTRIBUTE(dwc3_rx_fifo_size);
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
DEFINE_SHOW_ATTRIBUTE(dwc3_tx_request_queue);
DEFINE_SHOW_ATTRIBUTE(dwc3_rx_request_queue);
DEFINE_SHOW_ATTRIBUTE(dwc3_rx_info_queue);
DEFINE_SHOW_ATTRIBUTE(dwc3_descriptor_fetch_queue);
DEFINE_SHOW_ATTRIBUTE(dwc3_event_queue);
DEFINE_SHOW_ATTRIBUTE(dwc3_transfer_type);
DEFINE_SHOW_ATTRIBUTE(dwc3_trb_ring);
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
DEFINE_SHOW_ATTRIBUTE(dwc3_ep_info_register);
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
static const struct dwc3_ep_file_map dwc3_ep_file_map[] = {
usb: dwc3: debugfs: Properly name Tx/RxFIFO The Tx/RxFIFO types in the GDBGFIFOSPACE.FIFO_QUEUE_SELECT are not queue. Properly rename them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:00 +08:00
{ "tx_fifo_size", &dwc3_tx_fifo_size_fops, },
{ "rx_fifo_size", &dwc3_rx_fifo_size_fops, },
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
{ "tx_request_queue", &dwc3_tx_request_queue_fops, },
{ "rx_request_queue", &dwc3_rx_request_queue_fops, },
{ "rx_info_queue", &dwc3_rx_info_queue_fops, },
{ "descriptor_fetch_queue", &dwc3_descriptor_fetch_queue_fops, },
{ "event_queue", &dwc3_event_queue_fops, },
{ "transfer_type", &dwc3_transfer_type_fops, },
{ "trb_ring", &dwc3_trb_ring_fops, },
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
{ "GDBGEPINFO", &dwc3_ep_info_register_fops, },
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
};
static void dwc3_debugfs_create_endpoint_files(struct dwc3_ep *dep,
struct dentry *parent)
{
int i;
usb: dwc3: debugfs: Re-use DEFINE_SHOW_ATTRIBUTE() macro ...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-02-15 19:03:38 +08:00
for (i = 0; i < ARRAY_SIZE(dwc3_ep_file_map); i++) {
const struct file_operations *fops = dwc3_ep_file_map[i].fops;
const char *name = dwc3_ep_file_map[i].name;
debugfs_create_file(name, S_IRUGO, parent, dep, fops);
}
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
}
static void dwc3_debugfs_create_endpoint_dir(struct dwc3_ep *dep,
struct dentry *parent)
{
struct dentry *dir;
dir = debugfs_create_dir(dep->name, parent);
dwc3_debugfs_create_endpoint_files(dep, dir);
}
static void dwc3_debugfs_create_endpoint_dirs(struct dwc3 *dwc,
struct dentry *parent)
{
int i;
usb: dwc3: refactor gadget endpoint count calculation - DWC_USB3_NUM indicates the number of Device mode single directional endpoints, including OUT and IN endpoint 0. - DWC_USB3_NUM_IN_EPS indicates the maximum number of Device mode IN endpoints active at any time, including control endpoint 0. It's possible to configure RTL such that DWC_USB3_NUM_EPS is equal to DWC_USB3_NUM_IN_EPS. dwc3-core calculates the number of OUT endpoints as DWC_USB3_NUM minus DWC_USB3_NUM_IN_EPS. If RTL has been configured with DWC_USB3_NUM_IN_EPS equal to DWC_USB3_NUM then dwc3-core will calculate the number of OUT endpoints as zero. For example a from dwc3_core_num_eps() shows: [ 1.565000] /usb0@f01d0000: found 8 IN and 0 OUT endpoints This patch refactors the endpoint calculation down to one variable dwc->num_eps taking care to maintain the current mapping of endpoints for fixed FPGA configurations as described in Table 4-7 of version 2.60a of the DWC USB3 databook. The endpoint mapping will then be EP-OUT, EP-IN etc, up to DWC_USB3_NUM. If DWC_USB3_NUM is odd then OUT will take the extra endpoint. Suggested-by: Felipe Balbi <balbi@kernel.org> Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-02-01 04:58:10 +08:00
for (i = 0; i < dwc->num_eps; i++) {
struct dwc3_ep *dep = dwc->eps[i];
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
if (!dep)
continue;
dwc3_debugfs_create_endpoint_dir(dep, parent);
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
}
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
}
usb: dwc3: make dwc3_debugfs_init return value be void Debugfs init failure is not so important. We can continue our job on this failure. Also no break need for debugfs_create_file call failure. Signed-off-by: Du, Changbin <changbin.du@intel.com> [felipe.balbi@linux.intel.com : - remove out-of-memory message, we get that from OOM. - switch dev_err() to dev_dbg() ] Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 19:10:18 +08:00
void dwc3_debugfs_init(struct dwc3 *dwc)
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
{
struct dentry *root;
usb: dwc3: debugfs: convert our regdump to use regsets regset is a generic implementation of regdump utility through debugfs. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-01-18 16:21:34 +08:00
dwc->regset = kzalloc(sizeof(*dwc->regset), GFP_KERNEL);
USB: dwc3: no need to check return value of debugfs_create functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Felipe Balbi <balbi@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-05-29 23:31:01 +08:00
if (!dwc->regset)
usb: dwc3: make dwc3_debugfs_init return value be void Debugfs init failure is not so important. We can continue our job on this failure. Also no break need for debugfs_create_file call failure. Signed-off-by: Du, Changbin <changbin.du@intel.com> [felipe.balbi@linux.intel.com : - remove out-of-memory message, we get that from OOM. - switch dev_err() to dev_dbg() ] Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 19:10:18 +08:00
return;
usb: dwc3: debugfs: convert our regdump to use regsets regset is a generic implementation of regdump utility through debugfs. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-01-18 16:21:34 +08:00
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
dwc->dbg_lsp_select = DWC3_LSP_MUX_UNSELECTED;
usb: dwc3: debugfs: convert our regdump to use regsets regset is a generic implementation of regdump utility through debugfs. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-01-18 16:21:34 +08:00
dwc->regset->regs = dwc3_regs;
dwc->regset->nregs = ARRAY_SIZE(dwc3_regs);
usb: dwc3: gadget: add a pointer to endpoint registers By adding a pointer to endpoint registers' base address, we can avoid using our controller-wide struct dwc3 pointer for everything. At some point this will allow us to have per-endpoint locks which will, in turn, let us queue requests to separate endpoints in parallel. Because of this change our debugfs interface and io accessors need to be changed accordingly. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 21:53:39 +08:00
dwc->regset->base = dwc->regs - DWC3_GLOBALS_REGS_START;
usb: dwc3: debugfs: convert our regdump to use regsets regset is a generic implementation of regdump utility through debugfs. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-01-18 16:21:34 +08:00
usb: dwc3: create debugfs directory under usb root Now the USB gadget subsystem can use the USB debugfs root directory, so move dwc3's directory from the root of the debugfs filesystem into the root of usb Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1573541519-28488-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-11-12 14:51:50 +08:00
root = debugfs_create_dir(dev_name(dwc->dev), usb_debug_root);
USB: dwc3: no need to check return value of debugfs_create functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Felipe Balbi <balbi@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-05-29 23:31:01 +08:00
dwc->root = root;
debugfs_create_regset32("regdump", S_IRUGO, root, dwc->regset);
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
usb: dwc3: debugfs: Dump internal LSP and ep registers To dump internal LSP and endpoint state debug registers, we must write to GDBGLSPMUX register. This patch correctly dump LSP and endpoint states from the debug registers. If the controller is in device mode, all LSP and endpoint state registers will be dumped via the debugfs attribute "lsp_dump". In host mode, the user has to write the LSP number to "lsp_dump" to dump a specific LSP selection. Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-11-08 09:55:13 +08:00
debugfs_create_file("lsp_dump", S_IRUGO | S_IWUSR, root, dwc,
&dwc3_lsp_fops);
usb: dwc3: debugfs: improve debugfs file creation when commit 388e5c5 (usb: dwc3: remove dwc3 dependency on host AND gadget.) changed the way debugfs files are created, it failed to note that 'mode' is necessary in Dual Role mode only while 'testmode' and 'link_state' are valid in Dual Role and Peripheral-only builds. Fix this while also converting pre- processor conditional to C conditionals. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-02-22 22:24:49 +08:00
if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)) {
USB: dwc3: no need to check return value of debugfs_create functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Felipe Balbi <balbi@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-05-29 23:31:01 +08:00
debugfs_create_file("mode", S_IRUGO | S_IWUSR, root, dwc,
&dwc3_mode_fops);
usb: dwc3: debugfs: add support for changing port mode This makes testing a lot easier when trying to switch between host and device modes. Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-17 13:50:39 +08:00
}
usb: dwc3: debugfs: improve debugfs file creation when commit 388e5c5 (usb: dwc3: remove dwc3 dependency on host AND gadget.) changed the way debugfs files are created, it failed to note that 'mode' is necessary in Dual Role mode only while 'testmode' and 'link_state' are valid in Dual Role and Peripheral-only builds. Fix this while also converting pre- processor conditional to C conditionals. Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-02-22 22:24:49 +08:00
if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) ||
IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
USB: dwc3: no need to check return value of debugfs_create functions When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Felipe Balbi <balbi@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-05-29 23:31:01 +08:00
debugfs_create_file("testmode", S_IRUGO | S_IWUSR, root, dwc,
&dwc3_testmode_fops);
debugfs_create_file("link_state", S_IRUGO | S_IWUSR, root, dwc,
&dwc3_link_state_fops);
usb: dwc3: debugfs: dump out endpoint details There's a bunch of information in the debug register set from dwc3 which is useful in some debugging scenarios. Let's dump them out in endpoint-specific directories and designated files. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-14 19:53:44 +08:00
dwc3_debugfs_create_endpoint_dirs(dwc, root);
usb: dwc3: make dwc3_debugfs_init return value be void Debugfs init failure is not so important. We can continue our job on this failure. Also no break need for debugfs_create_file call failure. Signed-off-by: Du, Changbin <changbin.du@intel.com> [felipe.balbi@linux.intel.com : - remove out-of-memory message, we get that from OOM. - switch dev_err() to dev_dbg() ] Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 19:10:18 +08:00
}
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
}
usb: remove use of __devexit CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Peter Korsgaard <jacmet@sunsite.dk> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Acked-by: Felipe Balbi <balbi@ti.com> Cc: Li Yang <leoli@freescale.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Wan ZongShun <mcuos.com@gmail.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-20 02:26:20 +08:00
void dwc3_debugfs_exit(struct dwc3 *dwc)
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
{
debugfs_remove_recursive(dwc->root);
usb: dwc3: fix memory leak of dwc->regset dwc->regset is allocated on dwc3_debugfs_init, and should be released on init failure or dwc3_debugfs_exit. Btw, The line "dwc->root = NULL" is unnecessary, so remove it. Signed-off-by: Du, Changbin <changbin.du@intel.com> [ felipe.balbi@linux.intel.com : add another err label for the new error condition ] Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-04-12 16:24:34 +08:00
kfree(dwc->regset);
usb: Introduce DesignWare USB3 DRD Driver The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
}