102 lines
2.3 KiB
Plaintext
102 lines
2.3 KiB
Plaintext
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/ {
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compatible = "snps,nsimosci_hs";
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clock-frequency = <5000000>; /* 5 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&core_intc>;
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chosen {
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/* this is for console on serial */
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bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug";
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};
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aliases {
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serial0 = &uart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/*
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* upstream irqs to core intc - downstream these are
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* "COMMON" irq 0,1..
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*/
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interrupts = <24 25 26 27 28 29 30 31>;
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};
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uart0: serial@f0000000 {
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compatible = "ns8250";
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reg = <0xf0000000 0x2000>;
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interrupt-parent = <&idu_intc>;
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interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
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RR distribute to all cpus */
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clock-frequency = <3686400>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test = <1>;
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};
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pgu0: pgu@f9000000 {
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compatible = "snps,arcpgufb";
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reg = <0xf9000000 0x400>;
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};
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ps2: ps2@f9001000 {
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compatible = "snps,arc_ps2";
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reg = <0xf9000400 0x14>;
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interrupts = <3 0>;
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interrupt-parent = <&idu_intc>;
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interrupt-names = "arc_ps2_irq";
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};
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eth0: ethernet@f0003000 {
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compatible = "snps,oscilan";
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reg = <0xf0003000 0x44>;
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interrupt-parent = <&idu_intc>;
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interrupts = <1 2>, <2 2>;
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interrupt-names = "rx", "tx";
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupts = <20>;
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};
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};
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};
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