2005-04-17 06:20:36 +08:00
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/*
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* linux/arch/arm/mach-pxa/pxa27x.c
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*
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* Author: Nicolas Pitre
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* Created: Nov 05, 2002
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA27x aka Bulverde.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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2007-10-18 18:04:39 +08:00
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#include <linux/suspend.h>
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2005-10-30 02:07:23 +08:00
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#include <linux/platform_device.h>
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2008-01-29 07:00:02 +08:00
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#include <linux/sysdev.h>
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2010-11-03 23:29:35 +08:00
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#include <linux/io.h>
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2010-11-29 18:18:26 +08:00
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#include <linux/irq.h>
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2011-02-23 19:38:16 +08:00
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#include <linux/i2c/pxa-i2c.h>
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2005-04-17 06:20:36 +08:00
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2010-10-11 08:20:19 +08:00
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#include <asm/mach/map.h>
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2008-08-05 23:14:15 +08:00
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#include <mach/hardware.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/irq.h>
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2008-08-05 23:14:15 +08:00
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#include <mach/irqs.h>
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2009-01-06 17:37:37 +08:00
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#include <mach/gpio.h>
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2009-01-02 23:17:22 +08:00
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#include <mach/pxa27x.h>
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2008-08-07 18:05:25 +08:00
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#include <mach/reset.h>
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2008-08-05 23:14:15 +08:00
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#include <mach/ohci.h>
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#include <mach/pm.h>
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#include <mach/dma.h>
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2010-11-03 23:29:35 +08:00
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#include <mach/smemc.h>
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2005-04-17 06:20:36 +08:00
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#include "generic.h"
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2007-05-15 22:39:36 +08:00
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#include "devices.h"
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2007-08-20 17:18:02 +08:00
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#include "clock.h"
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2005-04-17 06:20:36 +08:00
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2008-10-04 12:45:39 +08:00
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void pxa27x_clear_otgph(void)
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{
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if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
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PSSR |= PSSR_OTGPH;
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}
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EXPORT_SYMBOL(pxa27x_clear_otgph);
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2010-01-04 16:30:58 +08:00
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static unsigned long ac97_reset_config[] = {
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GPIO113_GPIO,
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2010-07-13 09:41:28 +08:00
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GPIO113_AC97_nRESET,
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GPIO95_GPIO,
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GPIO95_AC97_nRESET,
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2010-01-04 16:30:58 +08:00
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};
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void pxa27x_assert_ac97reset(int reset_gpio, int on)
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{
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if (reset_gpio == 113)
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pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
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&ac97_reset_config[1], 1);
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if (reset_gpio == 95)
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pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
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&ac97_reset_config[3], 1);
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}
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EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
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2005-04-17 06:20:36 +08:00
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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2007-08-20 17:07:44 +08:00
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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2005-04-17 06:20:36 +08:00
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M, n2, N, S;
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int cccr_a, t, ht, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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2006-02-02 03:25:59 +08:00
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t = clkcfg & (1 << 0);
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2005-04-17 06:20:36 +08:00
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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n2 = (ccsr>>7) & 0xf;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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N = (L * n2) / 2;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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S = (b) ? L : (L/2);
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if (info) {
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
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(t) ? "" : "in" );
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printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
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S / 1000000, (S % 1000000) / 10000 );
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}
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return (t) ? (N/1000) : (L/1000);
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}
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/*
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2010-11-22 22:48:49 +08:00
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* Return the current mem clock frequency as reflected by CCCR[A], B, and L
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2005-04-17 06:20:36 +08:00
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*/
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2010-11-22 22:48:49 +08:00
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static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
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2005-04-17 06:20:36 +08:00
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M;
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int cccr_a, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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2010-11-22 22:48:49 +08:00
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return M;
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2005-04-17 06:20:36 +08:00
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}
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2010-11-22 22:48:49 +08:00
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static const struct clkops clk_pxa27x_mem_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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.getrate = clk_pxa27x_mem_getrate,
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};
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2005-04-17 06:20:36 +08:00
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/*
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* Return the current LCD clock frequency in units of 10kHz as
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*/
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2007-08-20 17:34:37 +08:00
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static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
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2005-04-17 06:20:36 +08:00
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{
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unsigned long ccsr;
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unsigned int l, L, k, K;
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ccsr = CCSR;
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l = ccsr & 0x1f;
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k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
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L = l * BASE_CLK;
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K = L / k;
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return (K / 10000);
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}
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2007-08-20 17:18:02 +08:00
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static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
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{
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return pxa27x_get_lcdclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa27x_lcd_ops = {
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2010-11-22 10:49:55 +08:00
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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2007-08-20 17:18:02 +08:00
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.getrate = clk_pxa27x_lcd_getrate,
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};
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2010-11-22 10:49:55 +08:00
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static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
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static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
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static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
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2008-11-09 04:25:21 +08:00
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static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
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static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
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2010-11-22 22:48:49 +08:00
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static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
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2008-11-09 04:25:21 +08:00
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static struct clk_lookup pxa27x_clkregs[] = {
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INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
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INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
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INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
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INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
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INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
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INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
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INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
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INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
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INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
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INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
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INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
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INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
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INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
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INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
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INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
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INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
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INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
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INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
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2010-11-22 22:48:49 +08:00
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INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
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2007-08-20 17:18:02 +08:00
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};
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2005-06-14 05:35:41 +08:00
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#ifdef CONFIG_PM
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2007-07-18 18:38:45 +08:00
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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2009-05-26 14:10:18 +08:00
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/*
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* allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
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*/
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static unsigned int pwrmode = PWRMODE_SLEEP;
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int __init pxa27x_set_pwrmode(unsigned int mode)
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{
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switch (mode) {
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case PWRMODE_SLEEP:
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case PWRMODE_DEEPSLEEP:
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pwrmode = mode;
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return 0;
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}
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return -EINVAL;
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}
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2007-07-18 18:38:45 +08:00
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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2008-09-03 18:06:34 +08:00
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enum {
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2007-07-18 18:38:45 +08:00
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_MDREFR,
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2008-09-03 18:06:34 +08:00
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SLEEP_SAVE_PCFR,
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2008-05-03 04:17:06 +08:00
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SLEEP_SAVE_COUNT
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2007-07-18 18:38:45 +08:00
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};
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void pxa27x_cpu_pm_save(unsigned long *sleep_save)
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{
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2010-11-03 23:29:35 +08:00
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sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
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2008-09-03 18:06:34 +08:00
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SAVE(PCFR);
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2007-07-18 18:38:45 +08:00
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SAVE(PSTR);
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}
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void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
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{
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2010-11-03 23:29:35 +08:00
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__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
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2008-09-03 18:06:34 +08:00
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RESTORE(PCFR);
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2007-07-18 18:38:45 +08:00
|
|
|
|
|
|
|
PSSR = PSSR_RDH | PSSR_PH;
|
|
|
|
|
|
|
|
RESTORE(PSTR);
|
|
|
|
}
|
|
|
|
|
|
|
|
void pxa27x_cpu_pm_enter(suspend_state_t state)
|
2005-06-04 03:52:27 +08:00
|
|
|
{
|
|
|
|
extern void pxa_cpu_standby(void);
|
|
|
|
|
|
|
|
/* ensure voltage-change sequencer not initiated, which hangs */
|
|
|
|
PCFR &= ~PCFR_FVC;
|
|
|
|
|
|
|
|
/* Clear edge-detect status register. */
|
|
|
|
PEDR = 0xDF12FE1B;
|
|
|
|
|
2008-05-08 23:50:39 +08:00
|
|
|
/* Clear reset status */
|
|
|
|
RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
|
|
|
|
|
2005-06-04 03:52:27 +08:00
|
|
|
switch (state) {
|
2005-07-01 18:27:05 +08:00
|
|
|
case PM_SUSPEND_STANDBY:
|
|
|
|
pxa_cpu_standby();
|
|
|
|
break;
|
2005-06-04 03:52:27 +08:00
|
|
|
case PM_SUSPEND_MEM:
|
2011-02-07 01:41:26 +08:00
|
|
|
pxa27x_cpu_suspend(pwrmode, PLAT_PHYS_OFFSET - PAGE_OFFSET);
|
2005-06-04 03:52:27 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-07-18 18:38:45 +08:00
|
|
|
static int pxa27x_cpu_pm_valid(suspend_state_t state)
|
2007-05-15 18:22:48 +08:00
|
|
|
{
|
|
|
|
return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
|
|
|
|
}
|
|
|
|
|
2008-08-27 19:55:04 +08:00
|
|
|
static int pxa27x_cpu_pm_prepare(void)
|
|
|
|
{
|
|
|
|
/* set resume return address */
|
2011-02-07 01:41:26 +08:00
|
|
|
PSPR = virt_to_phys(cpu_resume);
|
2008-08-27 19:55:04 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pxa27x_cpu_pm_finish(void)
|
|
|
|
{
|
|
|
|
/* ensure not to come back here if it wasn't intended */
|
|
|
|
PSPR = 0;
|
|
|
|
}
|
|
|
|
|
2007-07-18 18:38:45 +08:00
|
|
|
static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
|
2008-05-03 04:17:06 +08:00
|
|
|
.save_count = SLEEP_SAVE_COUNT,
|
2007-07-18 18:38:45 +08:00
|
|
|
.save = pxa27x_cpu_pm_save,
|
|
|
|
.restore = pxa27x_cpu_pm_restore,
|
|
|
|
.valid = pxa27x_cpu_pm_valid,
|
|
|
|
.enter = pxa27x_cpu_pm_enter,
|
2008-08-27 19:55:04 +08:00
|
|
|
.prepare = pxa27x_cpu_pm_prepare,
|
|
|
|
.finish = pxa27x_cpu_pm_finish,
|
2007-05-15 18:16:10 +08:00
|
|
|
};
|
2007-07-18 18:38:45 +08:00
|
|
|
|
|
|
|
static void __init pxa27x_init_pm(void)
|
|
|
|
{
|
|
|
|
pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
|
|
|
|
}
|
2008-01-02 08:24:49 +08:00
|
|
|
#else
|
|
|
|
static inline void pxa27x_init_pm(void) {}
|
2005-06-14 05:35:41 +08:00
|
|
|
#endif
|
|
|
|
|
2007-08-29 17:22:17 +08:00
|
|
|
/* PXA27x: Various gpios can issue wakeup events. This logic only
|
|
|
|
* handles the simple cases, not the WEMUX2 and WEMUX3 options
|
|
|
|
*/
|
2010-11-29 18:18:26 +08:00
|
|
|
static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
|
2007-08-29 17:22:17 +08:00
|
|
|
{
|
2010-11-29 18:18:26 +08:00
|
|
|
int gpio = IRQ_TO_GPIO(d->irq);
|
2007-08-29 17:22:17 +08:00
|
|
|
uint32_t mask;
|
|
|
|
|
2008-03-11 09:46:28 +08:00
|
|
|
if (gpio >= 0 && gpio < 128)
|
|
|
|
return gpio_set_wake(gpio, on);
|
2007-08-29 17:22:17 +08:00
|
|
|
|
2010-11-29 18:18:26 +08:00
|
|
|
if (d->irq == IRQ_KEYPAD)
|
2008-03-11 09:46:28 +08:00
|
|
|
return keypad_set_wake(on);
|
2007-08-29 17:22:17 +08:00
|
|
|
|
2010-11-29 18:18:26 +08:00
|
|
|
switch (d->irq) {
|
2007-08-29 17:22:17 +08:00
|
|
|
case IRQ_RTCAlrm:
|
|
|
|
mask = PWER_RTC;
|
|
|
|
break;
|
|
|
|
case IRQ_USB:
|
|
|
|
mask = 1u << 26;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (on)
|
|
|
|
PWER |= mask;
|
|
|
|
else
|
|
|
|
PWER &=~mask;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init pxa27x_init_irq(void)
|
|
|
|
{
|
2008-03-04 14:19:58 +08:00
|
|
|
pxa_init_irq(34, pxa27x_set_wake);
|
2009-01-06 17:37:37 +08:00
|
|
|
pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
|
2007-08-29 17:22:17 +08:00
|
|
|
}
|
|
|
|
|
2010-10-11 08:20:19 +08:00
|
|
|
static struct map_desc pxa27x_io_desc[] __initdata = {
|
|
|
|
{ /* Mem Ctl */
|
2010-11-03 23:29:35 +08:00
|
|
|
.virtual = SMEMC_VIRT,
|
|
|
|
.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
|
2010-10-11 08:20:19 +08:00
|
|
|
.length = 0x00200000,
|
|
|
|
.type = MT_DEVICE
|
|
|
|
}, { /* IMem ctl */
|
|
|
|
.virtual = 0xfe000000,
|
|
|
|
.pfn = __phys_to_pfn(0x58000000),
|
|
|
|
.length = 0x00100000,
|
|
|
|
.type = MT_DEVICE
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init pxa27x_map_io(void)
|
|
|
|
{
|
|
|
|
pxa_map_io();
|
|
|
|
iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
|
|
|
|
pxa27x_get_clk_frequency_khz(1);
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
* device registration specific to PXA27x.
|
|
|
|
*/
|
2008-08-17 13:23:05 +08:00
|
|
|
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
|
2008-01-28 01:14:50 +08:00
|
|
|
{
|
2008-06-03 01:49:27 +08:00
|
|
|
local_irq_disable();
|
|
|
|
PCFR |= PCFR_PI2CEN;
|
|
|
|
local_irq_enable();
|
2008-11-28 15:24:12 +08:00
|
|
|
pxa_register_device(&pxa27x_device_i2c_power, info);
|
2008-01-28 01:14:50 +08:00
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static struct platform_device *devices[] __initdata = {
|
2008-06-23 06:36:39 +08:00
|
|
|
&pxa27x_device_udc,
|
2010-06-14 00:43:00 +08:00
|
|
|
&pxa_device_pmu,
|
2007-07-17 17:45:58 +08:00
|
|
|
&pxa_device_i2s,
|
2010-03-18 04:15:21 +08:00
|
|
|
&pxa_device_asoc_ssp1,
|
|
|
|
&pxa_device_asoc_ssp2,
|
|
|
|
&pxa_device_asoc_ssp3,
|
|
|
|
&pxa_device_asoc_platform,
|
2008-11-14 06:50:56 +08:00
|
|
|
&sa1100_device_rtc,
|
2007-07-17 17:45:58 +08:00
|
|
|
&pxa_device_rtc,
|
2007-12-10 17:54:36 +08:00
|
|
|
&pxa27x_device_ssp1,
|
|
|
|
&pxa27x_device_ssp2,
|
|
|
|
&pxa27x_device_ssp3,
|
2008-04-14 04:44:04 +08:00
|
|
|
&pxa27x_device_pwm0,
|
|
|
|
&pxa27x_device_pwm1,
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
2008-01-29 07:00:02 +08:00
|
|
|
static struct sys_device pxa27x_sysdev[] = {
|
|
|
|
{
|
|
|
|
.cls = &pxa_irq_sysclass,
|
2008-09-03 18:06:34 +08:00
|
|
|
}, {
|
|
|
|
.cls = &pxa2xx_mfp_sysclass,
|
2008-01-29 07:00:02 +08:00
|
|
|
}, {
|
|
|
|
.cls = &pxa_gpio_sysclass,
|
2010-11-23 17:00:03 +08:00
|
|
|
}, {
|
|
|
|
.cls = &pxa2xx_clock_sysclass,
|
|
|
|
}
|
2008-01-29 07:00:02 +08:00
|
|
|
};
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static int __init pxa27x_init(void)
|
|
|
|
{
|
2008-01-29 07:00:02 +08:00
|
|
|
int i, ret = 0;
|
|
|
|
|
2007-05-15 18:16:10 +08:00
|
|
|
if (cpu_is_pxa27x()) {
|
2008-07-29 14:26:00 +08:00
|
|
|
|
|
|
|
reset_status = RCSR;
|
|
|
|
|
2010-01-12 20:28:00 +08:00
|
|
|
clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
|
2007-08-20 17:18:02 +08:00
|
|
|
|
2009-01-02 16:26:33 +08:00
|
|
|
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
|
2007-06-22 12:40:17 +08:00
|
|
|
return ret;
|
2008-01-02 08:24:49 +08:00
|
|
|
|
2007-07-18 18:38:45 +08:00
|
|
|
pxa27x_init_pm();
|
2008-01-02 08:24:49 +08:00
|
|
|
|
2008-01-29 07:00:02 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
|
|
|
|
ret = sysdev_register(&pxa27x_sysdev[i]);
|
|
|
|
if (ret)
|
|
|
|
pr_err("failed to register sysdev[%d]\n", i);
|
|
|
|
}
|
|
|
|
|
2007-05-15 18:16:10 +08:00
|
|
|
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
|
|
|
}
|
2008-01-29 07:00:02 +08:00
|
|
|
|
2007-05-15 18:16:10 +08:00
|
|
|
return ret;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2008-04-19 17:59:24 +08:00
|
|
|
postcore_initcall(pxa27x_init);
|