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OpenCloudOS-Kernel
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OpenCloudOS-Kernel/drivers/clk/meson/meson-eeclk.h

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clk: meson: factorise meson64 peripheral clock controller drivers The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-01 22:53:45 +08:00
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __MESON_CLKC_H
#define __MESON_CLKC_H
#include <linux/clk-provider.h>
#include "clk-regmap.h"
struct platform_device;
struct meson_eeclkc_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
clk: meson: eeclk: add init regs Like the PLL and MPLL, the controller may require some magic setting to be applied on startup. This is needed when the initial setting is not applied by the boot ROM. The controller need to do it when the setting applies to several clock, like all the MPLLs in the case of g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-13 20:31:14 +08:00
const struct reg_sequence *init_regs;
unsigned int init_count;
clk: meson: factorise meson64 peripheral clock controller drivers The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-01 22:53:45 +08:00
struct clk_hw_onecell_data *hw_onecell_data;
};
int meson_eeclkc_probe(struct platform_device *pdev);
#endif /* __MESON_CLKC_H */