OpenCloudOS-Kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h

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/* SPDX-License-Identifier: GPL-2.0-only */
drm/msm: Add SDM845 DPU support SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-06-28 03:26:09 +08:00
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DPU_HW_VBIF_H
#define _DPU_HW_VBIF_H
#include "dpu_hw_catalog.h"
#include "dpu_hw_mdss.h"
#include "dpu_hw_util.h"
struct dpu_hw_vbif;
/**
* struct dpu_hw_vbif_ops : Interface to the VBIF hardware driver functions
* Assumption is these functions will be called after clocks are enabled
*/
struct dpu_hw_vbif_ops {
/**
* set_limit_conf - set transaction limit config
* @vbif: vbif context driver
* @xin_id: client interface identifier
* @rd: true for read limit; false for write limit
* @limit: outstanding transaction limit
*/
void (*set_limit_conf)(struct dpu_hw_vbif *vbif,
u32 xin_id, bool rd, u32 limit);
/**
* get_limit_conf - get transaction limit config
* @vbif: vbif context driver
* @xin_id: client interface identifier
* @rd: true for read limit; false for write limit
* @return: outstanding transaction limit
*/
u32 (*get_limit_conf)(struct dpu_hw_vbif *vbif,
u32 xin_id, bool rd);
/**
* set_halt_ctrl - set halt control
* @vbif: vbif context driver
* @xin_id: client interface identifier
* @enable: halt control enable
*/
void (*set_halt_ctrl)(struct dpu_hw_vbif *vbif,
u32 xin_id, bool enable);
/**
* get_halt_ctrl - get halt control
* @vbif: vbif context driver
* @xin_id: client interface identifier
* @return: halt control enable
*/
bool (*get_halt_ctrl)(struct dpu_hw_vbif *vbif,
u32 xin_id);
/**
* set_qos_remap - set QoS priority remap
* @vbif: vbif context driver
* @xin_id: client interface identifier
* @level: priority level
* @remap_level: remapped level
*/
void (*set_qos_remap)(struct dpu_hw_vbif *vbif,
u32 xin_id, u32 level, u32 remap_level);
/**
* set_mem_type - set memory type
* @vbif: vbif context driver
* @xin_id: client interface identifier
* @value: memory type value
*/
void (*set_mem_type)(struct dpu_hw_vbif *vbif,
u32 xin_id, u32 value);
/**
* clear_errors - clear any vbif errors
* This function clears any detected pending/source errors
* on the VBIF interface, and optionally returns the detected
* error mask(s).
* @vbif: vbif context driver
* @pnd_errors: pointer to pending error reporting variable
* @src_errors: pointer to source error reporting variable
*/
void (*clear_errors)(struct dpu_hw_vbif *vbif,
u32 *pnd_errors, u32 *src_errors);
/**
* set_write_gather_en - set write_gather enable
* @vbif: vbif context driver
* @xin_id: client interface identifier
*/
void (*set_write_gather_en)(struct dpu_hw_vbif *vbif, u32 xin_id);
};
struct dpu_hw_vbif {
/* base */
struct dpu_hw_blk_reg_map hw;
/* vbif */
enum dpu_vbif idx;
const struct dpu_vbif_cfg *cap;
/* ops */
struct dpu_hw_vbif_ops ops;
};
/**
* dpu_hw_vbif_init - initializes the vbif driver for the passed interface idx
* @idx: Interface index for which driver object is required
* @addr: Mapped register io address of MDSS
* @m: Pointer to mdss catalog data
*/
struct dpu_hw_vbif *dpu_hw_vbif_init(enum dpu_vbif idx,
void __iomem *addr,
const struct dpu_mdss_cfg *m);
void dpu_hw_vbif_destroy(struct dpu_hw_vbif *vbif);
#endif /*_DPU_HW_VBIF_H */