2016-10-10 18:15:30 +08:00
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/* QLogic qedr NIC Driver
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* Copyright (c) 2015-2016 QLogic Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and /or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/module.h>
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#include <rdma/ib_verbs.h>
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#include <rdma/ib_addr.h>
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2016-10-10 18:15:32 +08:00
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#include <rdma/ib_user_verbs.h>
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2016-10-10 18:15:30 +08:00
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#include <linux/netdevice.h>
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#include <linux/iommu.h>
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#include <net/addrconf.h>
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#include <linux/qed/qede_roce.h>
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2016-10-10 18:15:31 +08:00
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#include <linux/qed/qed_chain.h>
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#include <linux/qed/qed_if.h>
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2016-10-10 18:15:30 +08:00
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#include "qedr.h"
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2016-10-10 18:15:32 +08:00
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#include "verbs.h"
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#include <rdma/qedr-abi.h>
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2016-10-10 18:15:30 +08:00
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MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
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MODULE_AUTHOR("QLogic Corporation");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_VERSION(QEDR_MODULE_VERSION);
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2016-10-10 18:15:34 +08:00
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#define QEDR_WQ_MULTIPLIER_DFT (3)
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2016-10-10 18:15:30 +08:00
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void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
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enum ib_event_type type)
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{
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struct ib_event ibev;
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ibev.device = &dev->ibdev;
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ibev.element.port_num = port_num;
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ibev.event = type;
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ib_dispatch_event(&ibev);
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}
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static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
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u8 port_num)
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{
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return IB_LINK_LAYER_ETHERNET;
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}
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2016-10-10 18:15:31 +08:00
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static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
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size_t str_len)
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{
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struct qedr_dev *qedr = get_qedr_dev(ibdev);
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u32 fw_ver = (u32)qedr->attr.fw_ver;
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snprintf(str, str_len, "%d. %d. %d. %d",
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(fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
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(fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
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}
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2016-10-10 18:15:30 +08:00
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static int qedr_register_device(struct qedr_dev *dev)
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{
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strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
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memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
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dev->ibdev.owner = THIS_MODULE;
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2016-10-10 18:15:32 +08:00
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dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
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dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
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QEDR_UVERBS(QUERY_DEVICE) |
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2016-10-10 18:15:33 +08:00
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QEDR_UVERBS(QUERY_PORT) |
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QEDR_UVERBS(ALLOC_PD) |
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QEDR_UVERBS(DEALLOC_PD) |
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QEDR_UVERBS(CREATE_COMP_CHANNEL) |
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QEDR_UVERBS(CREATE_CQ) |
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QEDR_UVERBS(RESIZE_CQ) |
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QEDR_UVERBS(DESTROY_CQ) |
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2016-10-10 18:15:34 +08:00
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QEDR_UVERBS(REQ_NOTIFY_CQ) |
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QEDR_UVERBS(CREATE_QP) |
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QEDR_UVERBS(MODIFY_QP) |
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QEDR_UVERBS(QUERY_QP) |
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2016-10-10 18:15:35 +08:00
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QEDR_UVERBS(DESTROY_QP) |
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QEDR_UVERBS(REG_MR) |
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2016-10-10 18:15:36 +08:00
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QEDR_UVERBS(DEREG_MR) |
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QEDR_UVERBS(POLL_CQ) |
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QEDR_UVERBS(POST_SEND) |
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QEDR_UVERBS(POST_RECV);
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2016-10-10 18:15:32 +08:00
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dev->ibdev.phys_port_cnt = 1;
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dev->ibdev.num_comp_vectors = dev->num_cnq;
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dev->ibdev.node_type = RDMA_NODE_IB_CA;
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dev->ibdev.query_device = qedr_query_device;
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dev->ibdev.query_port = qedr_query_port;
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dev->ibdev.modify_port = qedr_modify_port;
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dev->ibdev.query_gid = qedr_query_gid;
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dev->ibdev.add_gid = qedr_add_gid;
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dev->ibdev.del_gid = qedr_del_gid;
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dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
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dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
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dev->ibdev.mmap = qedr_mmap;
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2016-10-10 18:15:33 +08:00
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dev->ibdev.alloc_pd = qedr_alloc_pd;
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dev->ibdev.dealloc_pd = qedr_dealloc_pd;
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dev->ibdev.create_cq = qedr_create_cq;
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dev->ibdev.destroy_cq = qedr_destroy_cq;
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dev->ibdev.resize_cq = qedr_resize_cq;
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dev->ibdev.req_notify_cq = qedr_arm_cq;
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2016-10-10 18:15:34 +08:00
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dev->ibdev.create_qp = qedr_create_qp;
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dev->ibdev.modify_qp = qedr_modify_qp;
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dev->ibdev.query_qp = qedr_query_qp;
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dev->ibdev.destroy_qp = qedr_destroy_qp;
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2016-10-10 18:15:33 +08:00
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dev->ibdev.query_pkey = qedr_query_pkey;
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2016-10-10 18:15:35 +08:00
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dev->ibdev.get_dma_mr = qedr_get_dma_mr;
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dev->ibdev.dereg_mr = qedr_dereg_mr;
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dev->ibdev.reg_user_mr = qedr_reg_user_mr;
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dev->ibdev.alloc_mr = qedr_alloc_mr;
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dev->ibdev.map_mr_sg = qedr_map_mr_sg;
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2016-10-10 18:15:36 +08:00
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dev->ibdev.poll_cq = qedr_poll_cq;
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dev->ibdev.post_send = qedr_post_send;
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dev->ibdev.post_recv = qedr_post_recv;
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2016-10-10 18:15:32 +08:00
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dev->ibdev.dma_device = &dev->pdev->dev;
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2016-10-10 18:15:30 +08:00
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dev->ibdev.get_link_layer = qedr_link_layer;
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2016-10-10 18:15:31 +08:00
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dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
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2016-10-10 18:15:30 +08:00
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return 0;
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}
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2016-10-10 18:15:31 +08:00
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/* This function allocates fast-path status block memory */
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static int qedr_alloc_mem_sb(struct qedr_dev *dev,
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struct qed_sb_info *sb_info, u16 sb_id)
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{
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struct status_block *sb_virt;
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dma_addr_t sb_phys;
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int rc;
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sb_virt = dma_alloc_coherent(&dev->pdev->dev,
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sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
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if (!sb_virt)
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return -ENOMEM;
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rc = dev->ops->common->sb_init(dev->cdev, sb_info,
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sb_virt, sb_phys, sb_id,
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QED_SB_TYPE_CNQ);
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if (rc) {
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pr_err("Status block initialization failed\n");
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dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
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sb_virt, sb_phys);
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return rc;
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}
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return 0;
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}
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static void qedr_free_mem_sb(struct qedr_dev *dev,
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struct qed_sb_info *sb_info, int sb_id)
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{
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if (sb_info->sb_virt) {
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dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
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dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
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(void *)sb_info->sb_virt, sb_info->sb_phys);
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}
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}
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static void qedr_free_resources(struct qedr_dev *dev)
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{
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int i;
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for (i = 0; i < dev->num_cnq; i++) {
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qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
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dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
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}
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kfree(dev->cnq_array);
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kfree(dev->sb_array);
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kfree(dev->sgid_tbl);
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}
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static int qedr_alloc_resources(struct qedr_dev *dev)
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{
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struct qedr_cnq *cnq;
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__le16 *cons_pi;
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u16 n_entries;
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int i, rc;
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dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
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QEDR_MAX_SGID, GFP_KERNEL);
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if (!dev->sgid_tbl)
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return -ENOMEM;
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spin_lock_init(&dev->sgid_lock);
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/* Allocate Status blocks for CNQ */
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dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
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GFP_KERNEL);
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if (!dev->sb_array) {
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rc = -ENOMEM;
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goto err1;
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}
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dev->cnq_array = kcalloc(dev->num_cnq,
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sizeof(*dev->cnq_array), GFP_KERNEL);
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if (!dev->cnq_array) {
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rc = -ENOMEM;
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goto err2;
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}
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dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
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/* Allocate CNQ PBLs */
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n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
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for (i = 0; i < dev->num_cnq; i++) {
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cnq = &dev->cnq_array[i];
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rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
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dev->sb_start + i);
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if (rc)
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goto err3;
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rc = dev->ops->common->chain_alloc(dev->cdev,
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QED_CHAIN_USE_TO_CONSUME,
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QED_CHAIN_MODE_PBL,
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QED_CHAIN_CNT_TYPE_U16,
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n_entries,
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sizeof(struct regpair *),
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&cnq->pbl);
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if (rc)
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goto err4;
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cnq->dev = dev;
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cnq->sb = &dev->sb_array[i];
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cons_pi = dev->sb_array[i].sb_virt->pi_array;
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cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
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cnq->index = i;
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sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
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DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
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i, qed_chain_get_cons_idx(&cnq->pbl));
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}
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return 0;
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err4:
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qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
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err3:
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for (--i; i >= 0; i--) {
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dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
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qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
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}
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kfree(dev->cnq_array);
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err2:
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kfree(dev->sb_array);
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err1:
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kfree(dev->sgid_tbl);
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return rc;
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}
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|
2016-10-10 18:15:30 +08:00
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/* QEDR sysfs interface */
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static ssize_t show_rev(struct device *device, struct device_attribute *attr,
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char *buf)
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{
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struct qedr_dev *dev = dev_get_drvdata(device);
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return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
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}
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static ssize_t show_hca_type(struct device *device,
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struct device_attribute *attr, char *buf)
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{
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return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
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}
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static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
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static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
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static struct device_attribute *qedr_attributes[] = {
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&dev_attr_hw_rev,
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&dev_attr_hca_type
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};
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static void qedr_remove_sysfiles(struct qedr_dev *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
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device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
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}
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static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
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{
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struct pci_dev *bridge;
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u32 val;
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|
|
dev->atomic_cap = IB_ATOMIC_NONE;
|
|
|
|
|
|
|
|
bridge = pdev->bus->self;
|
|
|
|
if (!bridge)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Check whether we are connected directly or via a switch */
|
|
|
|
while (bridge && bridge->bus->parent) {
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT,
|
|
|
|
"Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
|
|
|
|
bridge->bus->number, bridge->bus->primary);
|
|
|
|
/* Need to check Atomic Op Routing Supported all the way to
|
|
|
|
* root complex.
|
|
|
|
*/
|
|
|
|
pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
|
|
|
|
if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
|
|
|
|
pcie_capability_clear_word(pdev,
|
|
|
|
PCI_EXP_DEVCTL2,
|
|
|
|
PCI_EXP_DEVCTL2_ATOMIC_REQ);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
bridge = bridge->bus->parent->self;
|
|
|
|
}
|
|
|
|
bridge = pdev->bus->self;
|
|
|
|
|
|
|
|
/* according to bridge capability */
|
|
|
|
pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
|
|
|
|
if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
|
|
|
|
pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
|
|
|
|
PCI_EXP_DEVCTL2_ATOMIC_REQ);
|
|
|
|
dev->atomic_cap = IB_ATOMIC_GLOB;
|
|
|
|
} else {
|
|
|
|
pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
|
|
|
|
PCI_EXP_DEVCTL2_ATOMIC_REQ);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
static const struct qed_rdma_ops *qed_ops;
|
|
|
|
|
|
|
|
#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
|
|
|
|
|
|
|
|
static irqreturn_t qedr_irq_handler(int irq, void *handle)
|
|
|
|
{
|
|
|
|
u16 hw_comp_cons, sw_comp_cons;
|
|
|
|
struct qedr_cnq *cnq = handle;
|
2016-10-10 18:15:33 +08:00
|
|
|
struct regpair *cq_handle;
|
|
|
|
struct qedr_cq *cq;
|
2016-10-10 18:15:31 +08:00
|
|
|
|
|
|
|
qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
|
|
|
|
|
|
|
|
qed_sb_update_sb_idx(cnq->sb);
|
|
|
|
|
|
|
|
hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
|
|
|
|
sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
|
|
|
|
|
|
|
|
/* Align protocol-index and chain reads */
|
|
|
|
rmb();
|
|
|
|
|
|
|
|
while (sw_comp_cons != hw_comp_cons) {
|
2016-10-10 18:15:33 +08:00
|
|
|
cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
|
|
|
|
cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
|
|
|
|
cq_handle->lo);
|
|
|
|
|
|
|
|
if (cq == NULL) {
|
|
|
|
DP_ERR(cnq->dev,
|
|
|
|
"Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
|
|
|
|
cq_handle->hi, cq_handle->lo, sw_comp_cons,
|
|
|
|
hw_comp_cons);
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
|
|
|
|
DP_ERR(cnq->dev,
|
|
|
|
"Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
|
|
|
|
cq_handle->hi, cq_handle->lo, cq);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
cq->arm_flags = 0;
|
|
|
|
|
|
|
|
if (cq->ibcq.comp_handler)
|
|
|
|
(*cq->ibcq.comp_handler)
|
|
|
|
(&cq->ibcq, cq->ibcq.cq_context);
|
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
|
2016-10-10 18:15:33 +08:00
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
cnq->n_comp++;
|
2016-10-10 18:15:33 +08:00
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
|
|
|
|
sw_comp_cons);
|
|
|
|
|
|
|
|
qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qedr_sync_free_irqs(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
u32 vector;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < dev->int_info.used_cnt; i++) {
|
|
|
|
if (dev->int_info.msix_cnt) {
|
|
|
|
vector = dev->int_info.msix[i * dev->num_hwfns].vector;
|
|
|
|
synchronize_irq(vector);
|
|
|
|
free_irq(vector, &dev->cnq_array[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->int_info.used_cnt = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qedr_req_msix_irqs(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
int i, rc = 0;
|
|
|
|
|
|
|
|
if (dev->num_cnq > dev->int_info.msix_cnt) {
|
|
|
|
DP_ERR(dev,
|
|
|
|
"Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
|
|
|
|
dev->num_cnq, dev->int_info.msix_cnt);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dev->num_cnq; i++) {
|
|
|
|
rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
|
|
|
|
qedr_irq_handler, 0, dev->cnq_array[i].name,
|
|
|
|
&dev->cnq_array[i]);
|
|
|
|
if (rc) {
|
|
|
|
DP_ERR(dev, "Request cnq %d irq failed\n", i);
|
|
|
|
qedr_sync_free_irqs(dev);
|
|
|
|
} else {
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT,
|
|
|
|
"Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
|
|
|
|
dev->cnq_array[i].name, i,
|
|
|
|
&dev->cnq_array[i]);
|
|
|
|
dev->int_info.used_cnt++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qedr_setup_irqs(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
|
|
|
|
|
|
|
|
/* Learn Interrupt configuration */
|
|
|
|
rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
|
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
|
|
|
|
if (rc) {
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->int_info.msix_cnt) {
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
|
|
|
|
dev->int_info.msix_cnt);
|
|
|
|
rc = qedr_req_msix_irqs(dev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qedr_set_device_attr(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
struct qed_rdma_device *qed_attr;
|
|
|
|
struct qedr_device_attr *attr;
|
|
|
|
u32 page_size;
|
|
|
|
|
|
|
|
/* Part 1 - query core capabilities */
|
|
|
|
qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
|
|
|
|
|
|
|
|
/* Part 2 - check capabilities */
|
|
|
|
page_size = ~dev->attr.page_size_caps + 1;
|
|
|
|
if (page_size > PAGE_SIZE) {
|
|
|
|
DP_ERR(dev,
|
|
|
|
"Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
|
|
|
|
PAGE_SIZE, page_size);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Part 3 - copy and update capabilities */
|
|
|
|
attr = &dev->attr;
|
|
|
|
attr->vendor_id = qed_attr->vendor_id;
|
|
|
|
attr->vendor_part_id = qed_attr->vendor_part_id;
|
|
|
|
attr->hw_ver = qed_attr->hw_ver;
|
|
|
|
attr->fw_ver = qed_attr->fw_ver;
|
|
|
|
attr->node_guid = qed_attr->node_guid;
|
|
|
|
attr->sys_image_guid = qed_attr->sys_image_guid;
|
|
|
|
attr->max_cnq = qed_attr->max_cnq;
|
|
|
|
attr->max_sge = qed_attr->max_sge;
|
|
|
|
attr->max_inline = qed_attr->max_inline;
|
|
|
|
attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
|
|
|
|
attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
|
|
|
|
attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
|
|
|
|
attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
|
|
|
|
attr->max_dev_resp_rd_atomic_resc =
|
|
|
|
qed_attr->max_dev_resp_rd_atomic_resc;
|
|
|
|
attr->max_cq = qed_attr->max_cq;
|
|
|
|
attr->max_qp = qed_attr->max_qp;
|
|
|
|
attr->max_mr = qed_attr->max_mr;
|
|
|
|
attr->max_mr_size = qed_attr->max_mr_size;
|
|
|
|
attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
|
|
|
|
attr->max_mw = qed_attr->max_mw;
|
|
|
|
attr->max_fmr = qed_attr->max_fmr;
|
|
|
|
attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
|
|
|
|
attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
|
|
|
|
attr->max_pd = qed_attr->max_pd;
|
|
|
|
attr->max_ah = qed_attr->max_ah;
|
|
|
|
attr->max_pkey = qed_attr->max_pkey;
|
|
|
|
attr->max_srq = qed_attr->max_srq;
|
|
|
|
attr->max_srq_wr = qed_attr->max_srq_wr;
|
|
|
|
attr->dev_caps = qed_attr->dev_caps;
|
|
|
|
attr->page_size_caps = qed_attr->page_size_caps;
|
|
|
|
attr->dev_ack_delay = qed_attr->dev_ack_delay;
|
|
|
|
attr->reserved_lkey = qed_attr->reserved_lkey;
|
|
|
|
attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
|
|
|
|
attr->max_stats_queues = qed_attr->max_stats_queues;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qedr_init_hw(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
struct qed_rdma_add_user_out_params out_params;
|
|
|
|
struct qed_rdma_start_in_params *in_params;
|
|
|
|
struct qed_rdma_cnq_params *cur_pbl;
|
|
|
|
struct qed_rdma_events events;
|
|
|
|
dma_addr_t p_phys_table;
|
|
|
|
u32 page_cnt;
|
|
|
|
int rc = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
|
|
|
|
if (!in_params) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
in_params->desired_cnq = dev->num_cnq;
|
|
|
|
for (i = 0; i < dev->num_cnq; i++) {
|
|
|
|
cur_pbl = &in_params->cnq_pbl_list[i];
|
|
|
|
|
|
|
|
page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
|
|
|
|
cur_pbl->num_pbl_pages = page_cnt;
|
|
|
|
|
|
|
|
p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
|
|
|
|
cur_pbl->pbl_ptr = (u64)p_phys_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
events.context = dev;
|
|
|
|
|
|
|
|
in_params->events = &events;
|
|
|
|
in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
|
|
|
|
in_params->max_mtu = dev->ndev->mtu;
|
|
|
|
ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
|
|
|
|
|
|
|
|
rc = dev->ops->rdma_init(dev->cdev, in_params);
|
|
|
|
if (rc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
|
|
|
|
if (rc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
|
|
|
|
dev->db_phys_addr = out_params.dpi_phys_addr;
|
|
|
|
dev->db_size = out_params.dpi_size;
|
|
|
|
dev->dpi = out_params.dpi;
|
|
|
|
|
|
|
|
rc = qedr_set_device_attr(dev);
|
|
|
|
out:
|
|
|
|
kfree(in_params);
|
|
|
|
if (rc)
|
|
|
|
DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
void qedr_stop_hw(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
|
|
|
|
dev->ops->rdma_stop(dev->rdma_ctx);
|
|
|
|
}
|
|
|
|
|
2016-10-10 18:15:30 +08:00
|
|
|
static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
|
|
|
|
struct net_device *ndev)
|
|
|
|
{
|
2016-10-10 18:15:31 +08:00
|
|
|
struct qed_dev_rdma_info dev_info;
|
2016-10-10 18:15:30 +08:00
|
|
|
struct qedr_dev *dev;
|
|
|
|
int rc = 0, i;
|
|
|
|
|
|
|
|
dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
|
|
|
|
if (!dev) {
|
|
|
|
pr_err("Unable to allocate ib device\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
|
|
|
|
|
|
|
|
dev->pdev = pdev;
|
|
|
|
dev->ndev = ndev;
|
|
|
|
dev->cdev = cdev;
|
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
qed_ops = qed_get_rdma_ops();
|
|
|
|
if (!qed_ops) {
|
|
|
|
DP_ERR(dev, "Failed to get qed roce operations\n");
|
|
|
|
goto init_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->ops = qed_ops;
|
|
|
|
rc = qed_ops->fill_dev_info(cdev, &dev_info);
|
|
|
|
if (rc)
|
|
|
|
goto init_err;
|
|
|
|
|
|
|
|
dev->num_hwfns = dev_info.common.num_hwfns;
|
|
|
|
dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
|
|
|
|
|
|
|
|
dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
|
|
|
|
if (!dev->num_cnq) {
|
|
|
|
DP_ERR(dev, "not enough CNQ resources.\n");
|
|
|
|
goto init_err;
|
|
|
|
}
|
|
|
|
|
2016-10-10 18:15:34 +08:00
|
|
|
dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
|
|
|
|
|
2016-10-10 18:15:30 +08:00
|
|
|
qedr_pci_set_atomic(dev, pdev);
|
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
rc = qedr_alloc_resources(dev);
|
|
|
|
if (rc)
|
|
|
|
goto init_err;
|
|
|
|
|
|
|
|
rc = qedr_init_hw(dev);
|
|
|
|
if (rc)
|
|
|
|
goto alloc_err;
|
|
|
|
|
|
|
|
rc = qedr_setup_irqs(dev);
|
|
|
|
if (rc)
|
|
|
|
goto irq_err;
|
|
|
|
|
2016-10-10 18:15:30 +08:00
|
|
|
rc = qedr_register_device(dev);
|
|
|
|
if (rc) {
|
|
|
|
DP_ERR(dev, "Unable to allocate register device\n");
|
2016-10-10 18:15:31 +08:00
|
|
|
goto reg_err;
|
2016-10-10 18:15:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
|
|
|
|
if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
|
2016-10-10 18:15:31 +08:00
|
|
|
goto reg_err;
|
2016-10-10 18:15:30 +08:00
|
|
|
|
|
|
|
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
|
|
|
|
return dev;
|
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
reg_err:
|
|
|
|
qedr_sync_free_irqs(dev);
|
|
|
|
irq_err:
|
|
|
|
qedr_stop_hw(dev);
|
|
|
|
alloc_err:
|
|
|
|
qedr_free_resources(dev);
|
2016-10-10 18:15:30 +08:00
|
|
|
init_err:
|
|
|
|
ib_dealloc_device(&dev->ibdev);
|
|
|
|
DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qedr_remove(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
/* First unregister with stack to stop all the active traffic
|
|
|
|
* of the registered clients.
|
|
|
|
*/
|
|
|
|
qedr_remove_sysfiles(dev);
|
|
|
|
|
2016-10-10 18:15:31 +08:00
|
|
|
qedr_stop_hw(dev);
|
|
|
|
qedr_sync_free_irqs(dev);
|
|
|
|
qedr_free_resources(dev);
|
2016-10-10 18:15:30 +08:00
|
|
|
ib_dealloc_device(&dev->ibdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qedr_close(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qedr_shutdown(struct qedr_dev *dev)
|
|
|
|
{
|
|
|
|
qedr_close(dev);
|
|
|
|
qedr_remove(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* event handling via NIC driver ensures that all the NIC specific
|
|
|
|
* initialization done before RoCE driver notifies
|
|
|
|
* event to stack.
|
|
|
|
*/
|
|
|
|
static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
|
|
|
|
{
|
|
|
|
switch (event) {
|
|
|
|
case QEDE_UP:
|
|
|
|
qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
|
|
|
|
break;
|
|
|
|
case QEDE_DOWN:
|
|
|
|
qedr_close(dev);
|
|
|
|
break;
|
|
|
|
case QEDE_CLOSE:
|
|
|
|
qedr_shutdown(dev);
|
|
|
|
break;
|
|
|
|
case QEDE_CHANGE_ADDR:
|
|
|
|
qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_err("Event not supported\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct qedr_driver qedr_drv = {
|
|
|
|
.name = "qedr_driver",
|
|
|
|
.add = qedr_add,
|
|
|
|
.remove = qedr_remove,
|
|
|
|
.notify = qedr_notify,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init qedr_init_module(void)
|
|
|
|
{
|
|
|
|
return qede_roce_register_driver(&qedr_drv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit qedr_exit_module(void)
|
|
|
|
{
|
|
|
|
qede_roce_unregister_driver(&qedr_drv);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(qedr_init_module);
|
|
|
|
module_exit(qedr_exit_module);
|