2015-04-21 04:55:21 +08:00
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/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Dave Airlie
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*/
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#include <linux/seq_file.h>
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#include <linux/atomic.h>
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#include <linux/wait.h>
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#include <linux/kref.h>
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#include <linux/slab.h>
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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/*
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* Fences
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* Fences mark an event in the GPUs pipeline and are used
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* for GPU/CPU synchronization. When the fence is written,
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* it is expected that all buffers associated with that fence
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* are no longer in use by the associated ring on the GPU and
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* that the the relevant GPU caches have been flushed.
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*/
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/**
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* amdgpu_fence_write - write a fence value
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*
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* @ring: ring the fence is associated with
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* @seq: sequence number to write
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*
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* Writes a fence value to memory (all asics).
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*/
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static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
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{
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struct amdgpu_fence_driver *drv = &ring->fence_drv;
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if (drv->cpu_addr)
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*drv->cpu_addr = cpu_to_le32(seq);
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}
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/**
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* amdgpu_fence_read - read a fence value
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*
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* @ring: ring the fence is associated with
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*
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* Reads a fence value from memory (all asics).
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* Returns the value of the fence read from memory.
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*/
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static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
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{
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struct amdgpu_fence_driver *drv = &ring->fence_drv;
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u32 seq = 0;
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if (drv->cpu_addr)
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seq = le32_to_cpu(*drv->cpu_addr);
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else
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seq = lower_32_bits(atomic64_read(&drv->last_seq));
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return seq;
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}
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/**
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* amdgpu_fence_schedule_check - schedule lockup check
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*
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* @ring: pointer to struct amdgpu_ring
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*
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* Queues a delayed work item to check for lockups.
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*/
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static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring)
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{
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/*
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* Do not reset the timer here with mod_delayed_work,
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* this can livelock in an interaction with TTM delayed destroy.
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*/
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queue_delayed_work(system_power_efficient_wq,
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&ring->fence_drv.lockup_work,
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AMDGPU_FENCE_JIFFIES_TIMEOUT);
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}
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/**
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* amdgpu_fence_emit - emit a fence on the requested ring
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*
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* @ring: ring the fence is associated with
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* @owner: creator of the fence
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* @fence: amdgpu fence object
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*
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* Emits a fence command on the requested ring (all asics).
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* Returns 0 on success, -ENOMEM on failure.
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*/
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int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
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struct amdgpu_fence **fence)
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{
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struct amdgpu_device *adev = ring->adev;
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/* we are protected by the ring emission mutex */
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*fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
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if ((*fence) == NULL) {
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return -ENOMEM;
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}
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(*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
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(*fence)->ring = ring;
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(*fence)->owner = owner;
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fence_init(&(*fence)->base, &amdgpu_fence_ops,
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&adev->fence_queue.lock, adev->fence_context + ring->idx,
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(*fence)->seq);
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amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, (*fence)->seq, false);
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trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq);
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return 0;
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}
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/**
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* amdgpu_fence_check_signaled - callback from fence_queue
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*
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* this function is called with fence_queue lock held, which is also used
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* for the fence locking itself, so unlocked variants are used for
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* fence_signal, and remove_wait_queue.
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*/
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static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
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{
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struct amdgpu_fence *fence;
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struct amdgpu_device *adev;
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u64 seq;
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int ret;
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fence = container_of(wait, struct amdgpu_fence, fence_wake);
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adev = fence->ring->adev;
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/*
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* We cannot use amdgpu_fence_process here because we're already
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* in the waitqueue, in a call from wake_up_all.
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*/
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seq = atomic64_read(&fence->ring->fence_drv.last_seq);
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if (seq >= fence->seq) {
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ret = fence_signal_locked(&fence->base);
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if (!ret)
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FENCE_TRACE(&fence->base, "signaled from irq context\n");
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else
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FENCE_TRACE(&fence->base, "was already signaled\n");
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amdgpu_irq_put(adev, fence->ring->fence_drv.irq_src,
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fence->ring->fence_drv.irq_type);
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__remove_wait_queue(&adev->fence_queue, &fence->fence_wake);
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fence_put(&fence->base);
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} else
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FENCE_TRACE(&fence->base, "pending\n");
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return 0;
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}
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/**
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* amdgpu_fence_activity - check for fence activity
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*
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* @ring: pointer to struct amdgpu_ring
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*
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* Checks the current fence value and calculates the last
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* signalled fence value. Returns true if activity occured
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* on the ring, and the fence_queue should be waken up.
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*/
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static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
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{
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uint64_t seq, last_seq, last_emitted;
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unsigned count_loop = 0;
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bool wake = false;
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/* Note there is a scenario here for an infinite loop but it's
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* very unlikely to happen. For it to happen, the current polling
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* process need to be interrupted by another process and another
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* process needs to update the last_seq btw the atomic read and
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* xchg of the current process.
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*
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* More over for this to go in infinite loop there need to be
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2015-05-13 22:52:42 +08:00
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* continuously new fence signaled ie amdgpu_fence_read needs
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2015-04-21 04:55:21 +08:00
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* to return a different value each time for both the currently
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* polling process and the other process that xchg the last_seq
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* btw atomic read and xchg of the current process. And the
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* value the other process set as last seq must be higher than
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* the seq value we just read. Which means that current process
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2015-05-13 22:52:42 +08:00
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* need to be interrupted after amdgpu_fence_read and before
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2015-04-21 04:55:21 +08:00
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* atomic xchg.
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*
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* To be even more safe we count the number of time we loop and
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* we bail after 10 loop just accepting the fact that we might
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* have temporarly set the last_seq not to the true real last
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* seq but to an older one.
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*/
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last_seq = atomic64_read(&ring->fence_drv.last_seq);
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do {
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last_emitted = ring->fence_drv.sync_seq[ring->idx];
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seq = amdgpu_fence_read(ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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seq &= 0xffffffff;
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seq |= last_emitted & 0xffffffff00000000LL;
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}
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if (seq <= last_seq || seq > last_emitted) {
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break;
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}
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/* If we loop over we don't want to return without
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* checking if a fence is signaled as it means that the
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* seq we just read is different from the previous on.
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*/
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wake = true;
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last_seq = seq;
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if ((count_loop++) > 10) {
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/* We looped over too many time leave with the
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* fact that we might have set an older fence
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* seq then the current real last seq as signaled
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* by the hw.
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*/
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break;
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}
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} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
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if (seq < last_emitted)
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amdgpu_fence_schedule_check(ring);
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return wake;
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}
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/**
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* amdgpu_fence_check_lockup - check for hardware lockup
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*
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* @work: delayed work item
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*
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* Checks for fence activity and if there is none probe
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* the hardware if a lockup occured.
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*/
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static void amdgpu_fence_check_lockup(struct work_struct *work)
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{
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struct amdgpu_fence_driver *fence_drv;
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struct amdgpu_ring *ring;
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fence_drv = container_of(work, struct amdgpu_fence_driver,
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lockup_work.work);
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ring = fence_drv->ring;
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if (!down_read_trylock(&ring->adev->exclusive_lock)) {
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/* just reschedule the check if a reset is going on */
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amdgpu_fence_schedule_check(ring);
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return;
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}
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if (fence_drv->delayed_irq && ring->adev->ddev->irq_enabled) {
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fence_drv->delayed_irq = false;
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amdgpu_irq_update(ring->adev, fence_drv->irq_src,
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fence_drv->irq_type);
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}
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if (amdgpu_fence_activity(ring))
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wake_up_all(&ring->adev->fence_queue);
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else if (amdgpu_ring_is_lockup(ring)) {
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/* good news we believe it's a lockup */
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dev_warn(ring->adev->dev, "GPU lockup (current fence id "
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"0x%016llx last fence id 0x%016llx on ring %d)\n",
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(uint64_t)atomic64_read(&fence_drv->last_seq),
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fence_drv->sync_seq[ring->idx], ring->idx);
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/* remember that we need an reset */
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ring->adev->needs_reset = true;
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wake_up_all(&ring->adev->fence_queue);
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}
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up_read(&ring->adev->exclusive_lock);
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}
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/**
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* amdgpu_fence_process - process a fence
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*
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* @adev: amdgpu_device pointer
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* @ring: ring index the fence is associated with
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*
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* Checks the current fence value and wakes the fence queue
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* if the sequence number has increased (all asics).
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*/
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void amdgpu_fence_process(struct amdgpu_ring *ring)
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{
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uint64_t seq, last_seq, last_emitted;
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unsigned count_loop = 0;
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bool wake = false;
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/* Note there is a scenario here for an infinite loop but it's
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* very unlikely to happen. For it to happen, the current polling
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* process need to be interrupted by another process and another
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* process needs to update the last_seq btw the atomic read and
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* xchg of the current process.
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*
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* More over for this to go in infinite loop there need to be
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* continuously new fence signaled ie amdgpu_fence_read needs
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* to return a different value each time for both the currently
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* polling process and the other process that xchg the last_seq
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* btw atomic read and xchg of the current process. And the
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* value the other process set as last seq must be higher than
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* the seq value we just read. Which means that current process
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* need to be interrupted after amdgpu_fence_read and before
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* atomic xchg.
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*
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* To be even more safe we count the number of time we loop and
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* we bail after 10 loop just accepting the fact that we might
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* have temporarly set the last_seq not to the true real last
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* seq but to an older one.
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*/
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last_seq = atomic64_read(&ring->fence_drv.last_seq);
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do {
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last_emitted = ring->fence_drv.sync_seq[ring->idx];
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seq = amdgpu_fence_read(ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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seq &= 0xffffffff;
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seq |= last_emitted & 0xffffffff00000000LL;
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}
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if (seq <= last_seq || seq > last_emitted) {
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break;
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}
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/* If we loop over we don't want to return without
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* checking if a fence is signaled as it means that the
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* seq we just read is different from the previous on.
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*/
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wake = true;
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last_seq = seq;
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if ((count_loop++) > 10) {
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/* We looped over too many time leave with the
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* fact that we might have set an older fence
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* seq then the current real last seq as signaled
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* by the hw.
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*/
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break;
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}
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} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
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if (wake)
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|
|
wake_up_all(&ring->adev->fence_queue);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
|
|
|
|
*
|
|
|
|
* @ring: ring the fence is associated with
|
|
|
|
* @seq: sequence number
|
|
|
|
*
|
|
|
|
* Check if the last signaled fence sequnce number is >= the requested
|
|
|
|
* sequence number (all asics).
|
|
|
|
* Returns true if the fence has signaled (current fence value
|
|
|
|
* is >= requested value) or false if it has not (current fence
|
|
|
|
* value is < the requested value. Helper function for
|
|
|
|
* amdgpu_fence_signaled().
|
|
|
|
*/
|
|
|
|
static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
|
|
|
|
{
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
/* poll new last sequence at least once */
|
|
|
|
amdgpu_fence_process(ring);
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool amdgpu_fence_is_signaled(struct fence *f)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
|
|
struct amdgpu_ring *ring = fence->ring;
|
|
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (down_read_trylock(&adev->exclusive_lock)) {
|
|
|
|
amdgpu_fence_process(ring);
|
|
|
|
up_read(&adev->exclusive_lock);
|
|
|
|
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_enable_signaling - enable signalling on fence
|
|
|
|
* @fence: fence
|
|
|
|
*
|
|
|
|
* This function is called with fence_queue lock held, and adds a callback
|
|
|
|
* to fence_queue that checks if this fence is signaled, and if so it
|
|
|
|
* signals the fence and removes itself.
|
|
|
|
*/
|
|
|
|
static bool amdgpu_fence_enable_signaling(struct fence *f)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
|
|
struct amdgpu_ring *ring = fence->ring;
|
|
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (down_read_trylock(&adev->exclusive_lock)) {
|
|
|
|
amdgpu_irq_get(adev, ring->fence_drv.irq_src,
|
|
|
|
ring->fence_drv.irq_type);
|
|
|
|
if (amdgpu_fence_activity(ring))
|
|
|
|
wake_up_all_locked(&adev->fence_queue);
|
|
|
|
|
|
|
|
/* did fence get signaled after we enabled the sw irq? */
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) {
|
|
|
|
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
|
|
|
|
ring->fence_drv.irq_type);
|
|
|
|
up_read(&adev->exclusive_lock);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
up_read(&adev->exclusive_lock);
|
|
|
|
} else {
|
|
|
|
/* we're probably in a lockup, lets not fiddle too much */
|
|
|
|
if (amdgpu_irq_get_delayed(adev, ring->fence_drv.irq_src,
|
|
|
|
ring->fence_drv.irq_type))
|
|
|
|
ring->fence_drv.delayed_irq = true;
|
|
|
|
amdgpu_fence_schedule_check(ring);
|
|
|
|
}
|
|
|
|
|
|
|
|
fence->fence_wake.flags = 0;
|
|
|
|
fence->fence_wake.private = NULL;
|
|
|
|
fence->fence_wake.func = amdgpu_fence_check_signaled;
|
|
|
|
__add_wait_queue(&adev->fence_queue, &fence->fence_wake);
|
|
|
|
fence_get(f);
|
|
|
|
FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_signaled - check if a fence has signaled
|
|
|
|
*
|
|
|
|
* @fence: amdgpu fence object
|
|
|
|
*
|
|
|
|
* Check if the requested fence has signaled (all asics).
|
|
|
|
* Returns true if the fence has signaled or false if it has not.
|
|
|
|
*/
|
|
|
|
bool amdgpu_fence_signaled(struct amdgpu_fence *fence)
|
|
|
|
{
|
|
|
|
if (!fence)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) {
|
|
|
|
if (!fence_signal(&fence->base))
|
|
|
|
FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_any_seq_signaled - check if any sequence number is signaled
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
* @seq: sequence numbers
|
|
|
|
*
|
|
|
|
* Check if the last signaled fence sequnce number is >= the requested
|
|
|
|
* sequence number (all asics).
|
|
|
|
* Returns true if any has signaled (current value is >= requested value)
|
|
|
|
* or false if it has not. Helper function for amdgpu_fence_wait_seq.
|
|
|
|
*/
|
|
|
|
static bool amdgpu_fence_any_seq_signaled(struct amdgpu_device *adev, u64 *seq)
|
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
if (!adev->rings[i] || !seq[i])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (amdgpu_fence_seq_signaled(adev->rings[i], seq[i]))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_wait_seq_timeout - wait for a specific sequence numbers
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
* @target_seq: sequence number(s) we want to wait for
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
* @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
|
|
|
|
*
|
|
|
|
* Wait for the requested sequence number(s) to be written by any ring
|
|
|
|
* (all asics). Sequnce number array is indexed by ring id.
|
|
|
|
* @intr selects whether to use interruptable (true) or non-interruptable
|
|
|
|
* (false) sleep when waiting for the sequence number. Helper function
|
|
|
|
* for amdgpu_fence_wait_*().
|
|
|
|
* Returns remaining time if the sequence number has passed, 0 when
|
|
|
|
* the wait timeout, or an error for all other cases.
|
|
|
|
* -EDEADLK is returned when a GPU lockup has been detected.
|
|
|
|
*/
|
|
|
|
long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev, u64 *target_seq,
|
|
|
|
bool intr, long timeout)
|
|
|
|
{
|
|
|
|
uint64_t last_seq[AMDGPU_MAX_RINGS];
|
|
|
|
bool signaled;
|
|
|
|
int i, r;
|
|
|
|
|
|
|
|
while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) {
|
|
|
|
|
|
|
|
/* Save current sequence values, used to check for GPU lockups */
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
|
|
|
|
if (!ring || !target_seq[i])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
last_seq[i] = atomic64_read(&ring->fence_drv.last_seq);
|
|
|
|
trace_amdgpu_fence_wait_begin(adev->ddev, i, target_seq[i]);
|
|
|
|
amdgpu_irq_get(adev, ring->fence_drv.irq_src,
|
|
|
|
ring->fence_drv.irq_type);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intr) {
|
|
|
|
r = wait_event_interruptible_timeout(adev->fence_queue, (
|
|
|
|
(signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
|
|
|
|
|| adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
|
|
|
|
} else {
|
|
|
|
r = wait_event_timeout(adev->fence_queue, (
|
|
|
|
(signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
|
|
|
|
|| adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
|
|
|
|
if (!ring || !target_seq[i])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
|
|
|
|
ring->fence_drv.irq_type);
|
|
|
|
trace_amdgpu_fence_wait_end(adev->ddev, i, target_seq[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(r < 0))
|
|
|
|
return r;
|
|
|
|
|
|
|
|
if (unlikely(!signaled)) {
|
|
|
|
|
|
|
|
if (adev->needs_reset)
|
|
|
|
return -EDEADLK;
|
|
|
|
|
|
|
|
/* we were interrupted for some reason and fence
|
|
|
|
* isn't signaled yet, resume waiting */
|
|
|
|
if (r)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
|
|
|
|
if (!ring || !target_seq[i])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (last_seq[i] != atomic64_read(&ring->fence_drv.last_seq))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i != AMDGPU_MAX_RINGS)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
if (!adev->rings[i] || !target_seq[i])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (amdgpu_ring_is_lockup(adev->rings[i]))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i < AMDGPU_MAX_RINGS) {
|
|
|
|
/* good news we believe it's a lockup */
|
|
|
|
dev_warn(adev->dev, "GPU lockup (waiting for "
|
|
|
|
"0x%016llx last fence id 0x%016llx on"
|
|
|
|
" ring %d)\n",
|
|
|
|
target_seq[i], last_seq[i], i);
|
|
|
|
|
|
|
|
/* remember that we need an reset */
|
|
|
|
adev->needs_reset = true;
|
|
|
|
wake_up_all(&adev->fence_queue);
|
|
|
|
return -EDEADLK;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timeout < MAX_SCHEDULE_TIMEOUT) {
|
|
|
|
timeout -= AMDGPU_FENCE_JIFFIES_TIMEOUT;
|
|
|
|
if (timeout <= 0) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return timeout;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_wait - wait for a fence to signal
|
|
|
|
*
|
|
|
|
* @fence: amdgpu fence object
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
*
|
|
|
|
* Wait for the requested fence to signal (all asics).
|
|
|
|
* @intr selects whether to use interruptable (true) or non-interruptable
|
|
|
|
* (false) sleep when waiting for the fence.
|
|
|
|
* Returns 0 if the fence has passed, error for all other cases.
|
|
|
|
*/
|
|
|
|
int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr)
|
|
|
|
{
|
|
|
|
uint64_t seq[AMDGPU_MAX_RINGS] = {};
|
|
|
|
long r;
|
|
|
|
|
|
|
|
seq[fence->ring->idx] = fence->seq;
|
|
|
|
r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (r < 0) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = fence_signal(&fence->base);
|
|
|
|
if (!r)
|
|
|
|
FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_wait_any - wait for a fence to signal on any ring
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
* @fences: amdgpu fence object(s)
|
|
|
|
* @intr: use interruptable sleep
|
|
|
|
*
|
|
|
|
* Wait for any requested fence to signal (all asics). Fence
|
|
|
|
* array is indexed by ring id. @intr selects whether to use
|
|
|
|
* interruptable (true) or non-interruptable (false) sleep when
|
|
|
|
* waiting for the fences. Used by the suballocator.
|
|
|
|
* Returns 0 if any fence has passed, error for all other cases.
|
|
|
|
*/
|
|
|
|
int amdgpu_fence_wait_any(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_fence **fences,
|
|
|
|
bool intr)
|
|
|
|
{
|
|
|
|
uint64_t seq[AMDGPU_MAX_RINGS];
|
|
|
|
unsigned i, num_rings = 0;
|
|
|
|
long r;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
seq[i] = 0;
|
|
|
|
|
|
|
|
if (!fences[i]) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
seq[i] = fences[i]->seq;
|
|
|
|
++num_rings;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* nothing to wait for ? */
|
|
|
|
if (num_rings == 0)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
r = amdgpu_fence_wait_seq_timeout(adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (r < 0) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_wait_next - wait for the next fence to signal
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
* @ring: ring index the fence is associated with
|
|
|
|
*
|
|
|
|
* Wait for the next fence on the requested ring to signal (all asics).
|
|
|
|
* Returns 0 if the next fence has passed, error for all other cases.
|
|
|
|
* Caller must hold ring lock.
|
|
|
|
*/
|
|
|
|
int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
|
|
|
|
{
|
|
|
|
uint64_t seq[AMDGPU_MAX_RINGS] = {};
|
|
|
|
long r;
|
|
|
|
|
|
|
|
seq[ring->idx] = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
|
|
|
|
if (seq[ring->idx] >= ring->fence_drv.sync_seq[ring->idx]) {
|
|
|
|
/* nothing to wait for, last_seq is
|
|
|
|
already the last emited fence */
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
r = amdgpu_fence_wait_seq_timeout(ring->adev, seq, false, MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (r < 0)
|
|
|
|
return r;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_wait_empty - wait for all fences to signal
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
* @ring: ring index the fence is associated with
|
|
|
|
*
|
|
|
|
* Wait for all fences on the requested ring to signal (all asics).
|
|
|
|
* Returns 0 if the fences have passed, error for all other cases.
|
|
|
|
* Caller must hold ring lock.
|
|
|
|
*/
|
|
|
|
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
|
|
|
|
{
|
|
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
uint64_t seq[AMDGPU_MAX_RINGS] = {};
|
|
|
|
long r;
|
|
|
|
|
|
|
|
seq[ring->idx] = ring->fence_drv.sync_seq[ring->idx];
|
|
|
|
if (!seq[ring->idx])
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
r = amdgpu_fence_wait_seq_timeout(adev, seq, false, MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (r < 0) {
|
|
|
|
if (r == -EDEADLK)
|
|
|
|
return -EDEADLK;
|
|
|
|
|
|
|
|
dev_err(adev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
|
|
|
|
ring->idx, r);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_ref - take a ref on a fence
|
|
|
|
*
|
|
|
|
* @fence: amdgpu fence object
|
|
|
|
*
|
|
|
|
* Take a reference on a fence (all asics).
|
|
|
|
* Returns the fence.
|
|
|
|
*/
|
|
|
|
struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence)
|
|
|
|
{
|
|
|
|
fence_get(&fence->base);
|
|
|
|
return fence;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_unref - remove a ref on a fence
|
|
|
|
*
|
|
|
|
* @fence: amdgpu fence object
|
|
|
|
*
|
|
|
|
* Remove a reference on a fence (all asics).
|
|
|
|
*/
|
|
|
|
void amdgpu_fence_unref(struct amdgpu_fence **fence)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence *tmp = *fence;
|
|
|
|
|
|
|
|
*fence = NULL;
|
|
|
|
if (tmp)
|
|
|
|
fence_put(&tmp->base);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_count_emitted - get the count of emitted fences
|
|
|
|
*
|
|
|
|
* @ring: ring the fence is associated with
|
|
|
|
*
|
|
|
|
* Get the number of fences emitted on the requested ring (all asics).
|
|
|
|
* Returns the number of emitted fences on the ring. Used by the
|
|
|
|
* dynpm code to ring track activity.
|
|
|
|
*/
|
|
|
|
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
|
|
|
|
{
|
|
|
|
uint64_t emitted;
|
|
|
|
|
|
|
|
/* We are not protected by ring lock when reading the last sequence
|
|
|
|
* but it's ok to report slightly wrong fence count here.
|
|
|
|
*/
|
|
|
|
amdgpu_fence_process(ring);
|
|
|
|
emitted = ring->fence_drv.sync_seq[ring->idx]
|
|
|
|
- atomic64_read(&ring->fence_drv.last_seq);
|
|
|
|
/* to avoid 32bits warp around */
|
|
|
|
if (emitted > 0x10000000)
|
|
|
|
emitted = 0x10000000;
|
|
|
|
|
|
|
|
return (unsigned)emitted;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_need_sync - do we need a semaphore
|
|
|
|
*
|
|
|
|
* @fence: amdgpu fence object
|
|
|
|
* @dst_ring: which ring to check against
|
|
|
|
*
|
|
|
|
* Check if the fence needs to be synced against another ring
|
|
|
|
* (all asics). If so, we need to emit a semaphore.
|
|
|
|
* Returns true if we need to sync with another ring, false if
|
|
|
|
* not.
|
|
|
|
*/
|
|
|
|
bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
|
|
|
|
struct amdgpu_ring *dst_ring)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence_driver *fdrv;
|
|
|
|
|
|
|
|
if (!fence)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (fence->ring == dst_ring)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* we are protected by the ring mutex */
|
|
|
|
fdrv = &dst_ring->fence_drv;
|
|
|
|
if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_note_sync - record the sync point
|
|
|
|
*
|
|
|
|
* @fence: amdgpu fence object
|
|
|
|
* @dst_ring: which ring to check against
|
|
|
|
*
|
|
|
|
* Note the sequence number at which point the fence will
|
|
|
|
* be synced with the requested ring (all asics).
|
|
|
|
*/
|
|
|
|
void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
|
|
|
|
struct amdgpu_ring *dst_ring)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence_driver *dst, *src;
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
if (!fence)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (fence->ring == dst_ring)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* we are protected by the ring mutex */
|
|
|
|
src = &fence->ring->fence_drv;
|
|
|
|
dst = &dst_ring->fence_drv;
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
if (i == dst_ring->idx)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_driver_start_ring - make the fence driver
|
|
|
|
* ready for use on the requested ring.
|
|
|
|
*
|
|
|
|
* @ring: ring to start the fence driver on
|
|
|
|
* @irq_src: interrupt source to use for this ring
|
|
|
|
* @irq_type: interrupt type to use for this ring
|
|
|
|
*
|
|
|
|
* Make the fence driver ready for processing (all asics).
|
|
|
|
* Not all asics have all rings, so each asic will only
|
|
|
|
* start the fence driver on the rings it has.
|
|
|
|
* Returns 0 for success, errors for failure.
|
|
|
|
*/
|
|
|
|
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
|
|
|
|
struct amdgpu_irq_src *irq_src,
|
|
|
|
unsigned irq_type)
|
|
|
|
{
|
|
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
uint64_t index;
|
|
|
|
|
|
|
|
if (ring != &adev->uvd.ring) {
|
|
|
|
ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
|
|
|
|
ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
|
|
|
|
} else {
|
|
|
|
/* put fence directly behind firmware */
|
|
|
|
index = ALIGN(adev->uvd.fw->size, 8);
|
|
|
|
ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
|
|
|
|
ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
|
|
|
|
}
|
|
|
|
amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
|
|
|
|
ring->fence_drv.initialized = true;
|
|
|
|
ring->fence_drv.irq_src = irq_src;
|
|
|
|
ring->fence_drv.irq_type = irq_type;
|
|
|
|
dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
|
|
|
|
"cpu addr 0x%p\n", ring->idx,
|
|
|
|
ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_driver_init_ring - init the fence driver
|
|
|
|
* for the requested ring.
|
|
|
|
*
|
|
|
|
* @ring: ring to init the fence driver on
|
|
|
|
*
|
|
|
|
* Init the fence driver for the requested ring (all asics).
|
|
|
|
* Helper function for amdgpu_fence_driver_init().
|
|
|
|
*/
|
|
|
|
void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
ring->fence_drv.cpu_addr = NULL;
|
|
|
|
ring->fence_drv.gpu_addr = 0;
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
|
|
|
|
ring->fence_drv.sync_seq[i] = 0;
|
|
|
|
|
|
|
|
atomic64_set(&ring->fence_drv.last_seq, 0);
|
|
|
|
ring->fence_drv.initialized = false;
|
|
|
|
|
|
|
|
INIT_DELAYED_WORK(&ring->fence_drv.lockup_work,
|
|
|
|
amdgpu_fence_check_lockup);
|
|
|
|
ring->fence_drv.ring = ring;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_driver_init - init the fence driver
|
|
|
|
* for all possible rings.
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
*
|
|
|
|
* Init the fence driver for all possible rings (all asics).
|
|
|
|
* Not all asics have all rings, so each asic will only
|
|
|
|
* start the fence driver on the rings it has using
|
|
|
|
* amdgpu_fence_driver_start_ring().
|
|
|
|
* Returns 0 for success.
|
|
|
|
*/
|
|
|
|
int amdgpu_fence_driver_init(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
init_waitqueue_head(&adev->fence_queue);
|
|
|
|
if (amdgpu_debugfs_fence_init(adev))
|
|
|
|
dev_err(adev->dev, "fence debugfs file creation failed\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_driver_fini - tear down the fence driver
|
|
|
|
* for all possible rings.
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
*
|
|
|
|
* Tear down the fence driver for all possible rings (all asics).
|
|
|
|
*/
|
|
|
|
void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
int i, r;
|
|
|
|
|
|
|
|
mutex_lock(&adev->ring_lock);
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
|
|
continue;
|
|
|
|
r = amdgpu_fence_wait_empty(ring);
|
|
|
|
if (r) {
|
|
|
|
/* no need to trigger GPU reset as we are unloading */
|
|
|
|
amdgpu_fence_driver_force_completion(adev);
|
|
|
|
}
|
|
|
|
wake_up_all(&adev->fence_queue);
|
|
|
|
ring->fence_drv.initialized = false;
|
|
|
|
}
|
|
|
|
mutex_unlock(&adev->ring_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_fence_driver_force_completion - force all fence waiter to complete
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device pointer
|
|
|
|
*
|
|
|
|
* In case of GPU reset failure make sure no process keep waiting on fence
|
|
|
|
* that will never complete.
|
|
|
|
*/
|
|
|
|
void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fence debugfs
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
amdgpu_fence_process(ring);
|
|
|
|
|
|
|
|
seq_printf(m, "--- ring %d ---\n", i);
|
|
|
|
seq_printf(m, "Last signaled fence 0x%016llx\n",
|
|
|
|
(unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
|
|
|
|
seq_printf(m, "Last emitted 0x%016llx\n",
|
|
|
|
ring->fence_drv.sync_seq[i]);
|
|
|
|
|
|
|
|
for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
|
|
|
|
struct amdgpu_ring *other = adev->rings[j];
|
|
|
|
if (i != j && other && other->fence_drv.initialized)
|
|
|
|
seq_printf(m, "Last sync to ring %d 0x%016llx\n",
|
|
|
|
j, ring->fence_drv.sync_seq[j]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_info_list amdgpu_debugfs_fence_list[] = {
|
|
|
|
{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *amdgpu_fence_get_driver_name(struct fence *fence)
|
|
|
|
{
|
|
|
|
return "amdgpu";
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *amdgpu_fence_get_timeline_name(struct fence *f)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
|
|
return (const char *)fence->ring->name;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence)
|
|
|
|
{
|
|
|
|
return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct amdgpu_wait_cb {
|
|
|
|
struct fence_cb base;
|
|
|
|
struct task_struct *task;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
|
|
|
|
{
|
|
|
|
struct amdgpu_wait_cb *wait =
|
|
|
|
container_of(cb, struct amdgpu_wait_cb, base);
|
|
|
|
wake_up_process(wait->task);
|
|
|
|
}
|
|
|
|
|
|
|
|
static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
|
|
|
|
signed long t)
|
|
|
|
{
|
|
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
|
|
struct amdgpu_device *adev = fence->ring->adev;
|
|
|
|
struct amdgpu_wait_cb cb;
|
|
|
|
|
|
|
|
cb.task = current;
|
|
|
|
|
|
|
|
if (fence_add_callback(f, &cb.base, amdgpu_fence_wait_cb))
|
|
|
|
return t;
|
|
|
|
|
|
|
|
while (t > 0) {
|
|
|
|
if (intr)
|
|
|
|
set_current_state(TASK_INTERRUPTIBLE);
|
|
|
|
else
|
|
|
|
set_current_state(TASK_UNINTERRUPTIBLE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* amdgpu_test_signaled must be called after
|
|
|
|
* set_current_state to prevent a race with wake_up_process
|
|
|
|
*/
|
|
|
|
if (amdgpu_test_signaled(fence))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (adev->needs_reset) {
|
|
|
|
t = -EDEADLK;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
t = schedule_timeout(t);
|
|
|
|
|
|
|
|
if (t > 0 && intr && signal_pending(current))
|
|
|
|
t = -ERESTARTSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
__set_current_state(TASK_RUNNING);
|
|
|
|
fence_remove_callback(f, &cb.base);
|
|
|
|
|
|
|
|
return t;
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct fence_ops amdgpu_fence_ops = {
|
|
|
|
.get_driver_name = amdgpu_fence_get_driver_name,
|
|
|
|
.get_timeline_name = amdgpu_fence_get_timeline_name,
|
|
|
|
.enable_signaling = amdgpu_fence_enable_signaling,
|
|
|
|
.signaled = amdgpu_fence_is_signaled,
|
|
|
|
.wait = amdgpu_fence_default_wait,
|
|
|
|
.release = NULL,
|
|
|
|
};
|