2019-06-04 16:11:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2011-03-11 13:17:45 +08:00
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/*
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* OMAP4 Voltage Controller (VC) data
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*
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* Copyright (C) 2007, 2010 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Lesly A M <x0080970@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2008, 2011 Nokia Corporation
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* Kalle Jokiniemi
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* Paul Walmsley
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*/
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/init.h>
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2011-11-11 05:45:17 +08:00
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#include "common.h"
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2011-03-11 13:17:45 +08:00
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#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "voltage.h"
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#include "vc.h"
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/*
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* VC data common to 44xx chips
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* XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
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*/
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2011-03-23 07:14:57 +08:00
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static const struct omap_vc_common omap4_vc_common = {
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2011-03-11 13:17:45 +08:00
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.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
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.data_shift = OMAP4430_DATA_SHIFT,
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.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
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.regaddr_shift = OMAP4430_REGADDR_SHIFT,
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.valid = OMAP4430_VALID_MASK,
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.cmd_on_shift = OMAP4430_ON_SHIFT,
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.cmd_on_mask = OMAP4430_ON_MASK,
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.cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
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.cmd_ret_shift = OMAP4430_RET_SHIFT,
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.cmd_off_shift = OMAP4430_OFF_SHIFT,
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2011-03-31 07:36:30 +08:00
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.i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
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2015-05-04 23:54:41 +08:00
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.i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
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2011-03-31 07:36:30 +08:00
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.i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
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.i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
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2011-03-11 13:17:45 +08:00
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};
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/* VC instance data for each controllable voltage line */
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2011-03-23 07:14:57 +08:00
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struct omap_vc_channel omap4_vc_mpu = {
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2011-06-03 08:28:13 +08:00
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.flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT,
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2011-03-23 07:14:57 +08:00
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.common = &omap4_vc_common,
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2011-07-21 07:35:46 +08:00
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.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
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.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
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.smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
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.cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
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2011-03-11 13:17:45 +08:00
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.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
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.smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
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.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
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2011-06-10 02:01:55 +08:00
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.smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
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OMAP3+: VC: abstract out channel configuration
VC channel configuration is programmed based on settings coming from
the PMIC configuration.
Currently, the VC channel to PMIC mapping is a simple one-to-one
mapping. Whenever a VC channel parameter is configured (i2c slave
addres, PMIC register address, on/ret/off command), the corresponding
bits are enabled in the VC channel configuration register.
If necessary, the programmability of channel configuration settings
could be extended to board/PMIC files, however, because this patch
changes the channel configuration to be programmed based on existing
values from the PMIC settings, it may not be required.
Also note that starting with OMAP4, where there are more than 2
channels, one channel is identified as the "default" channel. When
any of the bits in the channel config for the other channels are zero,
it means to use the default channel. The OMAP4 TRM (at least through
NDA version Q) is wrong in describing which is the default channel.
The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-03-30 06:57:16 +08:00
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.cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
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2011-03-11 13:17:45 +08:00
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};
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2011-03-23 07:14:57 +08:00
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struct omap_vc_channel omap4_vc_iva = {
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.common = &omap4_vc_common,
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2011-07-21 07:35:46 +08:00
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.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
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.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
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.smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
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.cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
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2011-03-11 13:17:45 +08:00
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.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
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.smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
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.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
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2011-06-10 02:01:55 +08:00
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.smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
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OMAP3+: VC: abstract out channel configuration
VC channel configuration is programmed based on settings coming from
the PMIC configuration.
Currently, the VC channel to PMIC mapping is a simple one-to-one
mapping. Whenever a VC channel parameter is configured (i2c slave
addres, PMIC register address, on/ret/off command), the corresponding
bits are enabled in the VC channel configuration register.
If necessary, the programmability of channel configuration settings
could be extended to board/PMIC files, however, because this patch
changes the channel configuration to be programmed based on existing
values from the PMIC settings, it may not be required.
Also note that starting with OMAP4, where there are more than 2
channels, one channel is identified as the "default" channel. When
any of the bits in the channel config for the other channels are zero,
it means to use the default channel. The OMAP4 TRM (at least through
NDA version Q) is wrong in describing which is the default channel.
The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-03-30 06:57:16 +08:00
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.cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
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2011-03-11 13:17:45 +08:00
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};
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2011-03-23 07:14:57 +08:00
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struct omap_vc_channel omap4_vc_core = {
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.common = &omap4_vc_common,
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2011-07-21 07:35:46 +08:00
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.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
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.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
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.smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
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.cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
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2011-03-11 13:17:45 +08:00
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.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
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.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
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.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
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2011-06-10 02:01:55 +08:00
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.smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
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OMAP3+: VC: abstract out channel configuration
VC channel configuration is programmed based on settings coming from
the PMIC configuration.
Currently, the VC channel to PMIC mapping is a simple one-to-one
mapping. Whenever a VC channel parameter is configured (i2c slave
addres, PMIC register address, on/ret/off command), the corresponding
bits are enabled in the VC channel configuration register.
If necessary, the programmability of channel configuration settings
could be extended to board/PMIC files, however, because this patch
changes the channel configuration to be programmed based on existing
values from the PMIC settings, it may not be required.
Also note that starting with OMAP4, where there are more than 2
channels, one channel is identified as the "default" channel. When
any of the bits in the channel config for the other channels are zero,
it means to use the default channel. The OMAP4 TRM (at least through
NDA version Q) is wrong in describing which is the default channel.
The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-03-30 06:57:16 +08:00
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.cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
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2011-03-11 13:17:45 +08:00
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};
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2012-09-26 00:33:35 +08:00
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/*
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* Voltage levels for different operating modes: on, sleep, retention and off
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*/
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#define OMAP4_ON_VOLTAGE_UV 1375000
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#define OMAP4_ONLP_VOLTAGE_UV 1375000
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#define OMAP4_RET_VOLTAGE_UV 837500
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#define OMAP4_OFF_VOLTAGE_UV 0
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struct omap_vc_param omap4_mpu_vc_data = {
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.on = OMAP4_ON_VOLTAGE_UV,
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.onlp = OMAP4_ONLP_VOLTAGE_UV,
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.ret = OMAP4_RET_VOLTAGE_UV,
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.off = OMAP4_OFF_VOLTAGE_UV,
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};
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struct omap_vc_param omap4_iva_vc_data = {
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.on = OMAP4_ON_VOLTAGE_UV,
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.onlp = OMAP4_ONLP_VOLTAGE_UV,
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.ret = OMAP4_RET_VOLTAGE_UV,
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.off = OMAP4_OFF_VOLTAGE_UV,
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};
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struct omap_vc_param omap4_core_vc_data = {
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.on = OMAP4_ON_VOLTAGE_UV,
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.onlp = OMAP4_ONLP_VOLTAGE_UV,
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.ret = OMAP4_RET_VOLTAGE_UV,
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.off = OMAP4_OFF_VOLTAGE_UV,
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};
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