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OpenCloudOS-Kernel/drivers/soc/qcom/Makefile

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soc: qcom: GLINK SSR notifier This driver register as a subsystem restart notifier and will send out notifications to remote processors that has opened the "glink_ssr" GLINK channel. This mechanism is used to signal any GLINK participants that a 3rd party is gone and that the communication state has to be reset; i.e. that read and write pointers of the GLINK FIFOs are stale. Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2017-07-25 13:56:44 +08:00
obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-25 00:31:21 +08:00
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
remoteproc: Move qcom_mdt_loader into drivers/soc/qcom With the remoteproc parts cleaned out of the MDT loader we can move it to drivers/soc/qcom. Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2017-01-27 19:12:57 +08:00
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
ARM: qcom: Add Subsystem Power Manager (SPM) driver SPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode. The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence. Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode. Add support for an idle driver to set up the SPM to place the core in Standby or Standalone power collapse mode when the core is idle. Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>, Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org> Original tree available at - git://codeaurora.org/quic/la/kernel/msm-3.10.git Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Kevin Hilman <khilman@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Kumar Gala <galak@codeaurora.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-04-10 03:20:41 +08:00
obj-$(CONFIG_QCOM_PM) += spm.o
soc: qcom: Driver for the Qualcomm RPM over SMD Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based devices. The driver exposes resources that child drivers can operate on; to implementing regulator, clock and bus frequency drivers. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-28 11:20:32 +08:00
obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
soc: qcom: Add Shared Memory Manager driver The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-06-27 05:50:10 +08:00
obj-$(CONFIG_QCOM_SMEM) += smem.o
soc: qcom: Introduce common SMEM state machine code This implements a common API for handling and exposing SMP2P and SMSM state information. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 09:25:01 +08:00
obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
soc: qcom: smp2p: Qualcomm Shared Memory Point to Point Introduce the Qualcomm Shard Memory Point to Point driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 09:25:03 +08:00
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
soc: qcom: smsm: Add driver for Qualcomm SMSM This driver exposed the Qualcomm Shared Memory State Machine bits. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 09:25:02 +08:00
obj-$(CONFIG_QCOM_SMSM) += smsm.o
soc: qcom: Introduce WCNSS_CTRL SMD client The WCNSS_CTRL SMD client is used for among other things upload nv firmware to a newly booted WCNSS chip. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-22 01:52:55 +08:00
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o