2015-04-21 04:55:21 +08:00
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/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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2016-01-30 13:59:34 +08:00
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#include <drm/drm_cache.h>
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2015-04-21 04:55:21 +08:00
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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2018-02-07 09:32:38 +08:00
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#include "amdgpu_amdkfd.h"
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2015-04-21 04:55:21 +08:00
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2017-12-16 05:45:02 +08:00
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static bool amdgpu_need_backup(struct amdgpu_device *adev)
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{
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if (adev->flags & AMD_IS_APU)
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return false;
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2017-12-20 21:21:25 +08:00
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if (amdgpu_gpu_recovery == 0 ||
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(amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))
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return false;
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return true;
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2017-12-16 05:45:02 +08:00
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}
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2015-04-21 04:55:21 +08:00
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static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
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{
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2016-09-15 20:58:48 +08:00
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struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
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2017-09-16 09:05:19 +08:00
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struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
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2015-04-21 04:55:21 +08:00
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2018-02-07 09:32:38 +08:00
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if (bo->kfd_bo)
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amdgpu_amdkfd_unreserve_system_memory_limit(bo);
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2017-07-11 23:25:49 +08:00
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amdgpu_bo_kunmap(bo);
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2015-04-21 04:55:21 +08:00
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2018-03-09 21:42:54 +08:00
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if (bo->gem_base.import_attach)
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drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
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2015-04-21 04:55:21 +08:00
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drm_gem_object_release(&bo->gem_base);
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2015-11-27 23:49:00 +08:00
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amdgpu_bo_unref(&bo->parent);
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2016-08-17 11:41:30 +08:00
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if (!list_empty(&bo->shadow_list)) {
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2016-09-15 20:58:48 +08:00
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mutex_lock(&adev->shadow_list_lock);
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2016-08-17 11:41:30 +08:00
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list_del_init(&bo->shadow_list);
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2016-09-15 20:58:48 +08:00
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mutex_unlock(&adev->shadow_list_lock);
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2016-08-17 11:41:30 +08:00
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}
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2015-04-21 04:55:21 +08:00
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kfree(bo->metadata);
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kfree(bo);
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}
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bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
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{
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if (bo->destroy == &amdgpu_ttm_bo_destroy)
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return true;
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return false;
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}
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2017-09-12 16:56:17 +08:00
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void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
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2015-04-21 04:55:21 +08:00
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{
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2017-09-12 16:56:17 +08:00
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struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
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struct ttm_placement *placement = &abo->placement;
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struct ttm_place *places = abo->placements;
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u64 flags = abo->flags;
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2016-08-15 20:08:54 +08:00
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u32 c = 0;
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2015-04-24 17:37:30 +08:00
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2015-04-21 04:55:21 +08:00
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if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
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2018-01-12 21:52:22 +08:00
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unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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2017-03-29 19:41:57 +08:00
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places[c].lpfn = 0;
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2016-08-15 20:06:50 +08:00
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places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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2015-04-24 17:37:30 +08:00
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TTM_PL_FLAG_VRAM;
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2017-03-29 19:41:57 +08:00
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2016-08-15 20:06:50 +08:00
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if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
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places[c].lpfn = visible_pfn;
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else
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places[c].flags |= TTM_PL_FLAG_TOPDOWN;
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2017-03-29 19:41:57 +08:00
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if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
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places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
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2016-08-15 20:06:50 +08:00
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c++;
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2015-04-21 04:55:21 +08:00
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}
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if (domain & AMDGPU_GEM_DOMAIN_GTT) {
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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2017-08-18 21:50:17 +08:00
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if (flags & AMDGPU_GEM_CREATE_SHADOW)
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2018-01-12 21:52:22 +08:00
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places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
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2017-08-18 21:50:17 +08:00
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else
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places[c].lpfn = 0;
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2016-08-15 20:06:50 +08:00
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places[c].flags = TTM_PL_FLAG_TT;
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if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
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places[c].flags |= TTM_PL_FLAG_WC |
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TTM_PL_FLAG_UNCACHED;
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else
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places[c].flags |= TTM_PL_FLAG_CACHED;
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c++;
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2015-04-21 04:55:21 +08:00
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}
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if (domain & AMDGPU_GEM_DOMAIN_CPU) {
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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places[c].lpfn = 0;
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places[c].flags = TTM_PL_FLAG_SYSTEM;
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if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
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places[c].flags |= TTM_PL_FLAG_WC |
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TTM_PL_FLAG_UNCACHED;
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else
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places[c].flags |= TTM_PL_FLAG_CACHED;
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c++;
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2015-04-21 04:55:21 +08:00
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}
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if (domain & AMDGPU_GEM_DOMAIN_GDS) {
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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places[c].lpfn = 0;
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places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
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c++;
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2015-04-21 04:55:21 +08:00
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}
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2016-08-15 20:06:50 +08:00
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2015-04-21 04:55:21 +08:00
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if (domain & AMDGPU_GEM_DOMAIN_GWS) {
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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places[c].lpfn = 0;
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places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
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c++;
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2015-04-21 04:55:21 +08:00
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}
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2016-08-15 20:06:50 +08:00
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2015-04-21 04:55:21 +08:00
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if (domain & AMDGPU_GEM_DOMAIN_OA) {
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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places[c].lpfn = 0;
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places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
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c++;
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2015-04-21 04:55:21 +08:00
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}
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if (!c) {
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2016-08-15 20:06:50 +08:00
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places[c].fpfn = 0;
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places[c].lpfn = 0;
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places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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c++;
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2015-04-21 04:55:21 +08:00
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}
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2016-08-15 20:06:50 +08:00
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2015-04-24 17:37:30 +08:00
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placement->num_placement = c;
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2016-08-15 20:06:50 +08:00
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placement->placement = places;
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2015-04-21 04:55:21 +08:00
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2016-08-15 20:06:50 +08:00
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placement->num_busy_placement = c;
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placement->busy_placement = places;
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2015-04-21 04:55:21 +08:00
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}
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2015-12-14 20:18:01 +08:00
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/**
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2017-07-27 23:08:54 +08:00
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* amdgpu_bo_create_reserved - create reserved BO for kernel use
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2015-12-14 20:18:01 +08:00
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*
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* @adev: amdgpu device object
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* @size: size for the new BO
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* @align: alignment for the new BO
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* @domain: where to place it
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2018-03-14 23:45:22 +08:00
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* @bo_ptr: used to initialize BOs in structures
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2015-12-14 20:18:01 +08:00
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* @gpu_addr: GPU addr of the pinned BO
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* @cpu_addr: optional CPU address mapping
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*
|
2017-07-27 23:08:54 +08:00
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* Allocates and pins a BO for kernel internal use, and returns it still
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* reserved.
|
2015-12-14 20:18:01 +08:00
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*
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2018-03-14 23:45:22 +08:00
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* Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
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*
|
2015-12-14 20:18:01 +08:00
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* Returns 0 on success, negative error code otherwise.
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*/
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2017-07-27 23:08:54 +08:00
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int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
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unsigned long size, int align,
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u32 domain, struct amdgpu_bo **bo_ptr,
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u64 *gpu_addr, void **cpu_addr)
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2015-12-14 20:18:01 +08:00
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{
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2018-04-16 18:27:50 +08:00
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struct amdgpu_bo_param bp;
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2017-07-27 20:52:53 +08:00
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bool free = false;
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2015-12-14 20:18:01 +08:00
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int r;
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2018-04-16 18:27:50 +08:00
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memset(&bp, 0, sizeof(bp));
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bp.size = size;
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bp.byte_align = align;
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bp.domain = domain;
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bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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bp.type = ttm_bo_type_kernel;
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bp.resv = NULL;
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2017-07-27 20:52:53 +08:00
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if (!*bo_ptr) {
|
2018-04-16 18:27:50 +08:00
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r = amdgpu_bo_create(adev, &bp, bo_ptr);
|
2017-07-27 20:52:53 +08:00
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
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r);
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return r;
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}
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free = true;
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2015-12-14 20:18:01 +08:00
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}
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r = amdgpu_bo_reserve(*bo_ptr, false);
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if (r) {
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dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
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goto error_free;
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}
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r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
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goto error_unreserve;
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}
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if (cpu_addr) {
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r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
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goto error_unreserve;
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}
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}
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return 0;
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error_unreserve:
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amdgpu_bo_unreserve(*bo_ptr);
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error_free:
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2017-07-27 20:52:53 +08:00
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if (free)
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amdgpu_bo_unref(bo_ptr);
|
2015-12-14 20:18:01 +08:00
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return r;
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}
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|
2017-07-27 23:08:54 +08:00
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/**
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* amdgpu_bo_create_kernel - create BO for kernel use
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*
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* @adev: amdgpu device object
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* @size: size for the new BO
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|
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* @align: alignment for the new BO
|
|
|
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* @domain: where to place it
|
2018-03-14 23:45:22 +08:00
|
|
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* @bo_ptr: used to initialize BOs in structures
|
2017-07-27 23:08:54 +08:00
|
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* @gpu_addr: GPU addr of the pinned BO
|
|
|
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* @cpu_addr: optional CPU address mapping
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|
|
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*
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|
|
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* Allocates and pins a BO for kernel internal use.
|
|
|
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*
|
2018-03-14 23:45:22 +08:00
|
|
|
* Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
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|
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*
|
2017-07-27 23:08:54 +08:00
|
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* Returns 0 on success, negative error code otherwise.
|
|
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*/
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|
|
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int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
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|
|
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unsigned long size, int align,
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|
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u32 domain, struct amdgpu_bo **bo_ptr,
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|
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u64 *gpu_addr, void **cpu_addr)
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|
|
|
{
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int r;
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r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
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|
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gpu_addr, cpu_addr);
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if (r)
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return r;
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|
|
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|
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|
|
amdgpu_bo_unreserve(*bo_ptr);
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|
|
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return 0;
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|
|
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}
|
|
|
|
|
2016-09-08 10:13:32 +08:00
|
|
|
/**
|
|
|
|
* amdgpu_bo_free_kernel - free BO for kernel use
|
|
|
|
*
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|
|
|
* @bo: amdgpu BO to free
|
|
|
|
*
|
|
|
|
* unmaps and unpin a BO for kernel internal use.
|
|
|
|
*/
|
|
|
|
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
|
|
|
|
void **cpu_addr)
|
|
|
|
{
|
|
|
|
if (*bo == NULL)
|
|
|
|
return;
|
|
|
|
|
2017-04-25 02:27:00 +08:00
|
|
|
if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
|
2016-09-08 10:13:32 +08:00
|
|
|
if (cpu_addr)
|
|
|
|
amdgpu_bo_kunmap(*bo);
|
|
|
|
|
|
|
|
amdgpu_bo_unpin(*bo);
|
|
|
|
amdgpu_bo_unreserve(*bo);
|
|
|
|
}
|
|
|
|
amdgpu_bo_unref(bo);
|
|
|
|
|
|
|
|
if (gpu_addr)
|
|
|
|
*gpu_addr = 0;
|
|
|
|
|
|
|
|
if (cpu_addr)
|
|
|
|
*cpu_addr = NULL;
|
|
|
|
}
|
|
|
|
|
2017-11-11 07:35:56 +08:00
|
|
|
/* Validate bo size is bit bigger then the request domain */
|
|
|
|
static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
|
|
|
|
unsigned long size, u32 domain)
|
|
|
|
{
|
|
|
|
struct ttm_mem_type_manager *man = NULL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If GTT is part of requested domains the check must succeed to
|
|
|
|
* allow fall back to GTT
|
|
|
|
*/
|
|
|
|
if (domain & AMDGPU_GEM_DOMAIN_GTT) {
|
|
|
|
man = &adev->mman.bdev.man[TTM_PL_TT];
|
|
|
|
|
|
|
|
if (size < (man->size << PAGE_SHIFT))
|
|
|
|
return true;
|
|
|
|
else
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
|
|
|
|
man = &adev->mman.bdev.man[TTM_PL_VRAM];
|
|
|
|
|
|
|
|
if (size < (man->size << PAGE_SHIFT))
|
|
|
|
return true;
|
|
|
|
else
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
|
|
|
|
return true;
|
|
|
|
|
|
|
|
fail:
|
2017-11-15 18:37:23 +08:00
|
|
|
DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
|
|
|
|
man->size << PAGE_SHIFT);
|
2017-11-11 07:35:56 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
static int amdgpu_bo_do_create(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_bo_param *bp,
|
2017-09-12 16:56:17 +08:00
|
|
|
struct amdgpu_bo **bo_ptr)
|
2015-04-21 04:55:21 +08:00
|
|
|
{
|
2017-12-08 13:31:52 +08:00
|
|
|
struct ttm_operation_ctx ctx = {
|
2018-04-16 17:57:19 +08:00
|
|
|
.interruptible = (bp->type != ttm_bo_type_kernel),
|
2017-12-08 13:31:52 +08:00
|
|
|
.no_wait_gpu = false,
|
2018-04-16 17:57:19 +08:00
|
|
|
.resv = bp->resv,
|
2018-02-06 11:22:57 +08:00
|
|
|
.flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
|
2017-12-08 13:31:52 +08:00
|
|
|
};
|
2015-04-21 04:55:21 +08:00
|
|
|
struct amdgpu_bo *bo;
|
2018-04-16 17:57:19 +08:00
|
|
|
unsigned long page_align, size = bp->size;
|
2018-04-17 11:52:53 +08:00
|
|
|
u32 preferred_domains;
|
2015-04-21 04:55:21 +08:00
|
|
|
size_t acc_size;
|
|
|
|
int r;
|
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
|
2015-04-21 04:55:21 +08:00
|
|
|
size = ALIGN(size, PAGE_SIZE);
|
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
if (!amdgpu_bo_validate_size(adev, size, bp->domain))
|
2017-11-11 07:35:56 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
*bo_ptr = NULL;
|
|
|
|
|
|
|
|
acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
|
|
|
|
sizeof(struct amdgpu_bo));
|
|
|
|
|
|
|
|
bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
|
|
|
|
if (bo == NULL)
|
|
|
|
return -ENOMEM;
|
2018-02-16 16:52:51 +08:00
|
|
|
drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
|
2016-08-17 11:41:30 +08:00
|
|
|
INIT_LIST_HEAD(&bo->shadow_list);
|
2015-04-21 04:55:21 +08:00
|
|
|
INIT_LIST_HEAD(&bo->va);
|
2018-04-17 11:52:53 +08:00
|
|
|
preferred_domains = bp->preferred_domain ? bp->preferred_domain :
|
|
|
|
bp->domain;
|
|
|
|
bo->preferred_domains = preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
|
|
|
|
AMDGPU_GEM_DOMAIN_GTT |
|
|
|
|
AMDGPU_GEM_DOMAIN_CPU |
|
|
|
|
AMDGPU_GEM_DOMAIN_GDS |
|
|
|
|
AMDGPU_GEM_DOMAIN_GWS |
|
|
|
|
AMDGPU_GEM_DOMAIN_OA);
|
2018-04-10 19:42:38 +08:00
|
|
|
bo->allowed_domains = bo->preferred_domains;
|
2018-04-16 17:57:19 +08:00
|
|
|
if (bp->type != ttm_bo_type_kernel &&
|
2018-04-10 19:42:38 +08:00
|
|
|
bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
|
|
|
|
bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
bo->flags = bp->flags;
|
2016-01-30 13:59:34 +08:00
|
|
|
|
2017-01-23 03:15:27 +08:00
|
|
|
#ifdef CONFIG_X86_32
|
|
|
|
/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
|
|
|
|
* See https://bugs.freedesktop.org/show_bug.cgi?id=84627
|
|
|
|
*/
|
|
|
|
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
|
|
|
|
#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
|
|
|
|
/* Don't try to enable write-combining when it can't work, or things
|
|
|
|
* may be slow
|
|
|
|
* See https://bugs.freedesktop.org/show_bug.cgi?id=88758
|
|
|
|
*/
|
|
|
|
|
2017-02-01 23:59:21 +08:00
|
|
|
#ifndef CONFIG_COMPILE_TEST
|
2017-01-23 03:15:27 +08:00
|
|
|
#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
|
|
|
|
thanks to write-combining
|
2017-02-01 23:59:21 +08:00
|
|
|
#endif
|
2017-01-23 03:15:27 +08:00
|
|
|
|
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
|
|
|
|
DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
|
|
|
|
"better performance thanks to write-combining\n");
|
|
|
|
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
|
|
|
|
#else
|
2016-01-30 13:59:34 +08:00
|
|
|
/* For architectures that don't support WC memory,
|
|
|
|
* mask out the WC flag from the BO
|
|
|
|
*/
|
|
|
|
if (!drm_arch_can_wc_memory())
|
|
|
|
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
|
2017-01-23 03:15:27 +08:00
|
|
|
#endif
|
2016-01-30 13:59:34 +08:00
|
|
|
|
2017-09-12 16:56:17 +08:00
|
|
|
bo->tbo.bdev = &adev->mman.bdev;
|
2018-04-16 17:57:19 +08:00
|
|
|
amdgpu_ttm_placement_from_domain(bo, bp->domain);
|
2018-04-10 19:42:38 +08:00
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
|
2018-02-22 22:52:31 +08:00
|
|
|
&bo->placement, page_align, &ctx, acc_size,
|
2018-04-16 17:57:19 +08:00
|
|
|
NULL, bp->resv, &amdgpu_ttm_bo_destroy);
|
2018-04-10 19:42:38 +08:00
|
|
|
if (unlikely(r != 0))
|
2017-10-31 16:36:13 +08:00
|
|
|
return r;
|
|
|
|
|
2018-01-12 21:52:22 +08:00
|
|
|
if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
|
2017-06-28 10:33:18 +08:00
|
|
|
bo->tbo.mem.mem_type == TTM_PL_VRAM &&
|
2018-01-12 21:52:22 +08:00
|
|
|
bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
|
2017-04-28 00:20:47 +08:00
|
|
|
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
|
|
|
|
ctx.bytes_moved);
|
2017-06-28 10:33:18 +08:00
|
|
|
else
|
2017-04-28 00:20:47 +08:00
|
|
|
amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
|
2017-02-09 18:33:37 +08:00
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
if (bp->type == ttm_bo_type_kernel)
|
2017-03-27 19:38:11 +08:00
|
|
|
bo->tbo.priority = 1;
|
2017-01-11 00:27:49 +08:00
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
|
2016-07-20 14:44:38 +08:00
|
|
|
bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
|
2016-10-25 20:00:45 +08:00
|
|
|
struct dma_fence *fence;
|
2016-07-20 14:44:38 +08:00
|
|
|
|
2018-01-25 02:55:32 +08:00
|
|
|
r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
|
2016-11-17 19:16:34 +08:00
|
|
|
if (unlikely(r))
|
|
|
|
goto fail_unreserve;
|
|
|
|
|
2016-07-20 14:44:38 +08:00
|
|
|
amdgpu_bo_fence(bo, fence, false);
|
2016-10-25 20:00:45 +08:00
|
|
|
dma_fence_put(bo->tbo.moving);
|
|
|
|
bo->tbo.moving = dma_fence_get(fence);
|
|
|
|
dma_fence_put(fence);
|
2016-07-20 14:44:38 +08:00
|
|
|
}
|
2018-04-16 17:57:19 +08:00
|
|
|
if (!bp->resv)
|
2017-02-16 18:01:44 +08:00
|
|
|
amdgpu_bo_unreserve(bo);
|
2015-04-21 04:55:21 +08:00
|
|
|
*bo_ptr = bo;
|
|
|
|
|
|
|
|
trace_amdgpu_bo_create(bo);
|
|
|
|
|
2017-06-30 23:31:08 +08:00
|
|
|
/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
|
2018-04-16 17:57:19 +08:00
|
|
|
if (bp->type == ttm_bo_type_device)
|
2017-06-30 23:31:08 +08:00
|
|
|
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
2016-07-20 14:44:38 +08:00
|
|
|
|
|
|
|
fail_unreserve:
|
2018-04-16 17:57:19 +08:00
|
|
|
if (!bp->resv)
|
2017-01-11 03:36:56 +08:00
|
|
|
ww_mutex_unlock(&bo->tbo.resv->lock);
|
2016-07-20 14:44:38 +08:00
|
|
|
amdgpu_bo_unref(&bo);
|
|
|
|
return r;
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
|
|
|
|
2016-07-26 14:13:21 +08:00
|
|
|
static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
|
|
|
|
unsigned long size, int byte_align,
|
|
|
|
struct amdgpu_bo *bo)
|
|
|
|
{
|
2018-04-16 18:27:50 +08:00
|
|
|
struct amdgpu_bo_param bp;
|
2016-07-26 14:13:21 +08:00
|
|
|
int r;
|
|
|
|
|
|
|
|
if (bo->shadow)
|
|
|
|
return 0;
|
|
|
|
|
2018-04-16 18:27:50 +08:00
|
|
|
memset(&bp, 0, sizeof(bp));
|
|
|
|
bp.size = size;
|
|
|
|
bp.byte_align = byte_align;
|
|
|
|
bp.domain = AMDGPU_GEM_DOMAIN_GTT;
|
|
|
|
bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
|
|
|
|
AMDGPU_GEM_CREATE_SHADOW;
|
|
|
|
bp.type = ttm_bo_type_kernel;
|
|
|
|
bp.resv = bo->tbo.resv;
|
|
|
|
|
2018-04-16 17:57:19 +08:00
|
|
|
r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
|
2016-08-17 11:41:30 +08:00
|
|
|
if (!r) {
|
2016-07-26 14:13:21 +08:00
|
|
|
bo->shadow->parent = amdgpu_bo_ref(bo);
|
2016-08-17 11:41:30 +08:00
|
|
|
mutex_lock(&adev->shadow_list_lock);
|
|
|
|
list_add_tail(&bo->shadow_list, &adev->shadow_list);
|
|
|
|
mutex_unlock(&adev->shadow_list_lock);
|
|
|
|
}
|
2016-07-26 14:13:21 +08:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2018-04-16 18:27:50 +08:00
|
|
|
int amdgpu_bo_create(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_bo_param *bp,
|
2015-09-03 23:34:59 +08:00
|
|
|
struct amdgpu_bo **bo_ptr)
|
2015-04-24 17:37:30 +08:00
|
|
|
{
|
2018-04-16 18:27:50 +08:00
|
|
|
u64 flags = bp->flags;
|
2016-07-26 14:13:21 +08:00
|
|
|
int r;
|
2015-04-24 17:37:30 +08:00
|
|
|
|
2018-04-16 18:27:50 +08:00
|
|
|
bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
|
|
|
|
r = amdgpu_bo_do_create(adev, bp, bo_ptr);
|
2016-07-26 14:13:21 +08:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2017-08-18 21:50:17 +08:00
|
|
|
if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
|
2018-04-16 18:27:50 +08:00
|
|
|
if (!bp->resv)
|
2017-08-18 21:50:17 +08:00
|
|
|
WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
|
|
|
|
NULL));
|
2017-01-11 02:06:00 +08:00
|
|
|
|
2018-04-16 18:27:50 +08:00
|
|
|
r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr));
|
2017-01-11 02:06:00 +08:00
|
|
|
|
2018-04-16 18:27:50 +08:00
|
|
|
if (!bp->resv)
|
2017-08-18 21:50:17 +08:00
|
|
|
reservation_object_unlock((*bo_ptr)->tbo.resv);
|
2017-01-11 02:06:00 +08:00
|
|
|
|
2016-07-26 14:13:21 +08:00
|
|
|
if (r)
|
|
|
|
amdgpu_bo_unref(bo_ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return r;
|
2015-04-24 17:37:30 +08:00
|
|
|
}
|
|
|
|
|
2016-08-04 16:51:18 +08:00
|
|
|
int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_ring *ring,
|
|
|
|
struct amdgpu_bo *bo,
|
|
|
|
struct reservation_object *resv,
|
2016-10-25 20:00:45 +08:00
|
|
|
struct dma_fence **fence,
|
2016-08-04 16:51:18 +08:00
|
|
|
bool direct)
|
|
|
|
|
|
|
|
{
|
|
|
|
struct amdgpu_bo *shadow = bo->shadow;
|
|
|
|
uint64_t bo_addr, shadow_addr;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (!shadow)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
bo_addr = amdgpu_bo_gpu_offset(bo);
|
|
|
|
shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
|
|
|
|
|
|
|
|
r = reservation_object_reserve_shared(bo->tbo.resv);
|
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
|
|
|
|
amdgpu_bo_size(bo), resv, fence,
|
2017-06-29 17:46:15 +08:00
|
|
|
direct, false);
|
2016-08-04 16:51:18 +08:00
|
|
|
if (!r)
|
|
|
|
amdgpu_bo_fence(bo, *fence, true);
|
|
|
|
|
|
|
|
err:
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2017-04-21 13:08:43 +08:00
|
|
|
int amdgpu_bo_validate(struct amdgpu_bo *bo)
|
|
|
|
{
|
2017-04-12 20:24:39 +08:00
|
|
|
struct ttm_operation_ctx ctx = { false, false };
|
2017-04-21 13:08:43 +08:00
|
|
|
uint32_t domain;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (bo->pin_count)
|
|
|
|
return 0;
|
|
|
|
|
2017-08-08 19:58:01 +08:00
|
|
|
domain = bo->preferred_domains;
|
2017-04-21 13:08:43 +08:00
|
|
|
|
|
|
|
retry:
|
|
|
|
amdgpu_ttm_placement_from_domain(bo, domain);
|
2017-04-12 20:24:39 +08:00
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
|
2017-04-21 13:08:43 +08:00
|
|
|
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
|
|
|
|
domain = bo->allowed_domains;
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2016-08-04 16:51:18 +08:00
|
|
|
int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_ring *ring,
|
|
|
|
struct amdgpu_bo *bo,
|
|
|
|
struct reservation_object *resv,
|
2016-10-25 20:00:45 +08:00
|
|
|
struct dma_fence **fence,
|
2016-08-04 16:51:18 +08:00
|
|
|
bool direct)
|
|
|
|
|
|
|
|
{
|
|
|
|
struct amdgpu_bo *shadow = bo->shadow;
|
|
|
|
uint64_t bo_addr, shadow_addr;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (!shadow)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
bo_addr = amdgpu_bo_gpu_offset(bo);
|
|
|
|
shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
|
|
|
|
|
|
|
|
r = reservation_object_reserve_shared(bo->tbo.resv);
|
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
|
|
|
|
amdgpu_bo_size(bo), resv, fence,
|
2017-06-29 17:46:15 +08:00
|
|
|
direct, false);
|
2016-08-04 16:51:18 +08:00
|
|
|
if (!r)
|
|
|
|
amdgpu_bo_fence(bo, *fence, true);
|
|
|
|
|
|
|
|
err:
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
|
|
|
|
{
|
2017-07-21 05:45:18 +08:00
|
|
|
void *kptr;
|
2016-03-10 23:21:04 +08:00
|
|
|
long r;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
2015-05-13 20:30:53 +08:00
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
|
|
|
|
return -EPERM;
|
|
|
|
|
2017-07-21 05:45:18 +08:00
|
|
|
kptr = amdgpu_bo_kptr(bo);
|
|
|
|
if (kptr) {
|
|
|
|
if (ptr)
|
|
|
|
*ptr = kptr;
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2016-03-10 23:21:04 +08:00
|
|
|
|
|
|
|
r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
|
|
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (r < 0)
|
|
|
|
return r;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
|
2016-03-10 23:21:04 +08:00
|
|
|
if (r)
|
2015-04-21 04:55:21 +08:00
|
|
|
return r;
|
2016-03-10 23:21:04 +08:00
|
|
|
|
|
|
|
if (ptr)
|
2017-07-21 05:45:18 +08:00
|
|
|
*ptr = amdgpu_bo_kptr(bo);
|
2016-03-10 23:21:04 +08:00
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-07-21 05:45:18 +08:00
|
|
|
void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
|
|
|
|
{
|
|
|
|
bool is_iomem;
|
|
|
|
|
|
|
|
return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
|
|
|
|
}
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
|
|
|
|
{
|
2017-07-21 05:45:18 +08:00
|
|
|
if (bo->kmap.bo)
|
|
|
|
ttm_bo_kunmap(&bo->kmap);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
|
|
|
|
{
|
|
|
|
if (bo == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
ttm_bo_reference(&bo->tbo);
|
|
|
|
return bo;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_unref(struct amdgpu_bo **bo)
|
|
|
|
{
|
|
|
|
struct ttm_buffer_object *tbo;
|
|
|
|
|
|
|
|
if ((*bo) == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
tbo = &((*bo)->tbo);
|
|
|
|
ttm_bo_unref(&tbo);
|
|
|
|
if (tbo == NULL)
|
|
|
|
*bo = NULL;
|
|
|
|
}
|
|
|
|
|
2015-04-24 17:37:30 +08:00
|
|
|
int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
|
|
|
|
u64 min_offset, u64 max_offset,
|
2015-04-21 04:55:21 +08:00
|
|
|
u64 *gpu_addr)
|
|
|
|
{
|
2016-09-15 20:58:48 +08:00
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
|
2017-04-12 20:24:39 +08:00
|
|
|
struct ttm_operation_ctx ctx = { false, false };
|
2015-04-21 04:55:21 +08:00
|
|
|
int r, i;
|
|
|
|
|
2016-02-08 18:08:35 +08:00
|
|
|
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
|
2015-04-21 04:55:21 +08:00
|
|
|
return -EPERM;
|
|
|
|
|
2015-04-24 17:37:30 +08:00
|
|
|
if (WARN_ON_ONCE(min_offset > max_offset))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-04-03 11:31:22 +08:00
|
|
|
/* A shared bo cannot be migrated to VRAM */
|
|
|
|
if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
if (bo->pin_count) {
|
2016-08-18 12:55:13 +08:00
|
|
|
uint32_t mem_type = bo->tbo.mem.mem_type;
|
|
|
|
|
2017-10-23 23:29:36 +08:00
|
|
|
if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
|
2016-08-18 12:55:13 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->pin_count++;
|
|
|
|
if (gpu_addr)
|
|
|
|
*gpu_addr = amdgpu_bo_gpu_offset(bo);
|
|
|
|
|
|
|
|
if (max_offset != 0) {
|
2016-08-18 13:18:09 +08:00
|
|
|
u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
|
2015-04-21 04:55:21 +08:00
|
|
|
WARN_ON_ONCE(max_offset <
|
|
|
|
(amdgpu_bo_gpu_offset(bo) - domain_start));
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2016-08-15 23:00:22 +08:00
|
|
|
|
|
|
|
bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
|
2017-09-11 23:29:26 +08:00
|
|
|
/* force to pin into visible video ram */
|
|
|
|
if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
|
|
|
|
bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
|
2015-04-21 04:55:21 +08:00
|
|
|
amdgpu_ttm_placement_from_domain(bo, domain);
|
|
|
|
for (i = 0; i < bo->placement.num_placement; i++) {
|
2017-09-11 23:29:26 +08:00
|
|
|
unsigned fpfn, lpfn;
|
|
|
|
|
|
|
|
fpfn = min_offset >> PAGE_SHIFT;
|
|
|
|
lpfn = max_offset >> PAGE_SHIFT;
|
|
|
|
|
2015-04-24 17:37:30 +08:00
|
|
|
if (fpfn > bo->placements[i].fpfn)
|
|
|
|
bo->placements[i].fpfn = fpfn;
|
2016-01-19 19:48:14 +08:00
|
|
|
if (!bo->placements[i].lpfn ||
|
|
|
|
(lpfn && lpfn < bo->placements[i].lpfn))
|
2015-04-24 17:37:30 +08:00
|
|
|
bo->placements[i].lpfn = lpfn;
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
|
|
|
|
}
|
|
|
|
|
2017-04-12 20:24:39 +08:00
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
|
2016-08-12 22:50:12 +08:00
|
|
|
if (unlikely(r)) {
|
2016-09-15 20:58:48 +08:00
|
|
|
dev_err(adev->dev, "%p pin failed\n", bo);
|
2016-08-12 22:50:12 +08:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2017-10-27 21:43:14 +08:00
|
|
|
r = amdgpu_ttm_alloc_gart(&bo->tbo);
|
2017-10-20 19:12:12 +08:00
|
|
|
if (unlikely(r)) {
|
|
|
|
dev_err(adev->dev, "%p bind failed\n", bo);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2016-08-12 22:50:12 +08:00
|
|
|
bo->pin_count = 1;
|
2017-10-20 19:12:12 +08:00
|
|
|
if (gpu_addr != NULL)
|
2016-08-12 22:50:12 +08:00
|
|
|
*gpu_addr = amdgpu_bo_gpu_offset(bo);
|
2017-10-20 19:11:00 +08:00
|
|
|
|
|
|
|
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
|
2016-08-12 22:50:12 +08:00
|
|
|
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
|
2016-09-15 20:58:48 +08:00
|
|
|
adev->vram_pin_size += amdgpu_bo_size(bo);
|
2016-08-12 22:50:12 +08:00
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
|
2016-09-15 20:58:48 +08:00
|
|
|
adev->invisible_pin_size += amdgpu_bo_size(bo);
|
2016-08-18 13:17:07 +08:00
|
|
|
} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
|
2016-09-15 20:58:48 +08:00
|
|
|
adev->gart_pin_size += amdgpu_bo_size(bo);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
2016-08-12 22:50:12 +08:00
|
|
|
|
|
|
|
error:
|
2015-04-21 04:55:21 +08:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
|
|
|
|
{
|
2015-04-24 17:37:30 +08:00
|
|
|
return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_unpin(struct amdgpu_bo *bo)
|
|
|
|
{
|
2016-09-15 20:58:48 +08:00
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
|
2017-04-12 20:24:39 +08:00
|
|
|
struct ttm_operation_ctx ctx = { false, false };
|
2015-04-21 04:55:21 +08:00
|
|
|
int r, i;
|
|
|
|
|
|
|
|
if (!bo->pin_count) {
|
2016-09-15 20:58:48 +08:00
|
|
|
dev_warn(adev->dev, "%p unpin not necessary\n", bo);
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
bo->pin_count--;
|
|
|
|
if (bo->pin_count)
|
|
|
|
return 0;
|
|
|
|
for (i = 0; i < bo->placement.num_placement; i++) {
|
|
|
|
bo->placements[i].lpfn = 0;
|
|
|
|
bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
|
|
|
|
}
|
2017-04-12 20:24:39 +08:00
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
|
2016-08-12 22:50:12 +08:00
|
|
|
if (unlikely(r)) {
|
2016-09-15 20:58:48 +08:00
|
|
|
dev_err(adev->dev, "%p validate failed for unpin\n", bo);
|
2016-08-12 22:50:12 +08:00
|
|
|
goto error;
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
2016-08-12 22:50:12 +08:00
|
|
|
|
|
|
|
if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
|
2016-09-15 20:58:48 +08:00
|
|
|
adev->vram_pin_size -= amdgpu_bo_size(bo);
|
2016-08-12 22:50:12 +08:00
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
|
2016-09-15 20:58:48 +08:00
|
|
|
adev->invisible_pin_size -= amdgpu_bo_size(bo);
|
2016-09-09 14:15:30 +08:00
|
|
|
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
|
2016-09-15 20:58:48 +08:00
|
|
|
adev->gart_pin_size -= amdgpu_bo_size(bo);
|
2016-08-12 22:50:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
error:
|
2015-04-21 04:55:21 +08:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
|
2015-07-22 11:29:01 +08:00
|
|
|
if (0 && (adev->flags & AMD_IS_APU)) {
|
2015-04-21 04:55:21 +08:00
|
|
|
/* Useless to evict on IGP chips */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
|
|
|
|
}
|
|
|
|
|
2016-04-01 04:56:22 +08:00
|
|
|
static const char *amdgpu_vram_names[] = {
|
|
|
|
"UNKNOWN",
|
|
|
|
"GDDR1",
|
|
|
|
"DDR2",
|
|
|
|
"GDDR3",
|
|
|
|
"GDDR4",
|
|
|
|
"GDDR5",
|
|
|
|
"HBM",
|
2018-03-09 19:16:55 +08:00
|
|
|
"DDR3",
|
|
|
|
"DDR4",
|
2016-04-01 04:56:22 +08:00
|
|
|
};
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
int amdgpu_bo_init(struct amdgpu_device *adev)
|
|
|
|
{
|
2016-10-24 13:37:48 +08:00
|
|
|
/* reserve PAT memory space to WC for VRAM */
|
2018-01-12 21:52:22 +08:00
|
|
|
arch_io_reserve_memtype_wc(adev->gmc.aper_base,
|
|
|
|
adev->gmc.aper_size);
|
2016-10-24 13:37:48 +08:00
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
/* Add an MTRR for the VRAM */
|
2018-01-12 21:52:22 +08:00
|
|
|
adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
|
|
|
|
adev->gmc.aper_size);
|
2015-04-21 04:55:21 +08:00
|
|
|
DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
|
2018-01-12 21:52:22 +08:00
|
|
|
adev->gmc.mc_vram_size >> 20,
|
|
|
|
(unsigned long long)adev->gmc.aper_size >> 20);
|
2016-04-01 04:56:22 +08:00
|
|
|
DRM_INFO("RAM width %dbits %s\n",
|
2018-01-12 21:52:22 +08:00
|
|
|
adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
|
2015-04-21 04:55:21 +08:00
|
|
|
return amdgpu_ttm_init(adev);
|
|
|
|
}
|
|
|
|
|
2018-04-07 03:54:10 +08:00
|
|
|
int amdgpu_bo_late_init(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
amdgpu_ttm_late_init(adev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
void amdgpu_bo_fini(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
amdgpu_ttm_fini(adev);
|
2018-01-12 21:52:22 +08:00
|
|
|
arch_phys_wc_del(adev->gmc.vram_mtrr);
|
|
|
|
arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
|
|
|
|
struct vm_area_struct *vma)
|
|
|
|
{
|
|
|
|
return ttm_fbdev_mmap(vma, &bo->tbo);
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
|
|
|
|
{
|
2017-03-04 05:03:15 +08:00
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
|
|
|
|
|
|
|
|
if (adev->family <= AMDGPU_FAMILY_CZ &&
|
|
|
|
AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
|
2015-04-21 04:55:21 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
bo->tiling_flags = tiling_flags;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
|
|
|
|
{
|
|
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
|
|
|
|
if (tiling_flags)
|
|
|
|
*tiling_flags = bo->tiling_flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
|
|
|
|
uint32_t metadata_size, uint64_t flags)
|
|
|
|
{
|
|
|
|
void *buffer;
|
|
|
|
|
|
|
|
if (!metadata_size) {
|
|
|
|
if (bo->metadata_size) {
|
|
|
|
kfree(bo->metadata);
|
2016-05-03 10:44:29 +08:00
|
|
|
bo->metadata = NULL;
|
2015-04-21 04:55:21 +08:00
|
|
|
bo->metadata_size = 0;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (metadata == NULL)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-09-22 05:34:39 +08:00
|
|
|
buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
|
2015-04-21 04:55:21 +08:00
|
|
|
if (buffer == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
kfree(bo->metadata);
|
|
|
|
bo->metadata_flags = flags;
|
|
|
|
bo->metadata = buffer;
|
|
|
|
bo->metadata_size = metadata_size;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
|
|
|
|
size_t buffer_size, uint32_t *metadata_size,
|
|
|
|
uint64_t *flags)
|
|
|
|
{
|
|
|
|
if (!buffer && !metadata_size)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (buffer) {
|
|
|
|
if (buffer_size < bo->metadata_size)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (bo->metadata_size)
|
|
|
|
memcpy(buffer, bo->metadata, bo->metadata_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (metadata_size)
|
|
|
|
*metadata_size = bo->metadata_size;
|
|
|
|
if (flags)
|
|
|
|
*flags = bo->metadata_flags;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
|
2016-12-16 00:23:49 +08:00
|
|
|
bool evict,
|
2015-04-21 04:55:21 +08:00
|
|
|
struct ttm_mem_reg *new_mem)
|
|
|
|
{
|
2016-09-15 20:58:48 +08:00
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
|
2016-09-15 21:06:50 +08:00
|
|
|
struct amdgpu_bo *abo;
|
2016-06-07 17:48:52 +08:00
|
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
|
|
|
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
|
|
|
|
return;
|
|
|
|
|
2017-09-16 09:05:19 +08:00
|
|
|
abo = ttm_to_amdgpu_bo(bo);
|
2017-08-03 20:02:13 +08:00
|
|
|
amdgpu_vm_bo_invalidate(adev, abo, evict);
|
2015-04-21 04:55:21 +08:00
|
|
|
|
2017-07-11 23:25:49 +08:00
|
|
|
amdgpu_bo_kunmap(abo);
|
|
|
|
|
2016-12-16 00:26:42 +08:00
|
|
|
/* remember the eviction */
|
|
|
|
if (evict)
|
|
|
|
atomic64_inc(&adev->num_evictions);
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
/* update statistics */
|
|
|
|
if (!new_mem)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* move_notify is called before move happens */
|
2016-09-15 21:06:50 +08:00
|
|
|
trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
|
|
{
|
2016-09-15 20:58:48 +08:00
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
|
2017-04-12 20:24:39 +08:00
|
|
|
struct ttm_operation_ctx ctx = { false, false };
|
2015-05-21 23:03:46 +08:00
|
|
|
struct amdgpu_bo *abo;
|
2017-06-30 23:31:08 +08:00
|
|
|
unsigned long offset, size;
|
|
|
|
int r;
|
2015-04-21 04:55:21 +08:00
|
|
|
|
|
|
|
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
|
|
|
|
return 0;
|
2015-05-21 23:03:46 +08:00
|
|
|
|
2017-09-16 09:05:19 +08:00
|
|
|
abo = ttm_to_amdgpu_bo(bo);
|
2017-06-30 23:31:08 +08:00
|
|
|
|
|
|
|
/* Remember that this BO was accessed by the CPU */
|
|
|
|
abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
|
|
|
|
|
2015-05-21 23:03:46 +08:00
|
|
|
if (bo->mem.mem_type != TTM_PL_VRAM)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
size = bo->mem.num_pages << PAGE_SHIFT;
|
|
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
2018-01-12 21:52:22 +08:00
|
|
|
if ((offset + size) <= adev->gmc.visible_vram_size)
|
2015-05-21 23:03:46 +08:00
|
|
|
return 0;
|
|
|
|
|
2016-03-28 11:53:02 +08:00
|
|
|
/* Can't move a pinned BO to visible VRAM */
|
|
|
|
if (abo->pin_count > 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-05-21 23:03:46 +08:00
|
|
|
/* hurrah the memory is not visible ! */
|
2017-05-18 02:05:08 +08:00
|
|
|
atomic64_inc(&adev->num_vram_cpu_page_faults);
|
2017-06-28 10:33:21 +08:00
|
|
|
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
|
|
|
|
AMDGPU_GEM_DOMAIN_GTT);
|
|
|
|
|
|
|
|
/* Avoid costly evictions; only set GTT as a busy placement */
|
|
|
|
abo->placement.num_busy_placement = 1;
|
|
|
|
abo->placement.busy_placement = &abo->placements[1];
|
|
|
|
|
2017-04-12 20:24:39 +08:00
|
|
|
r = ttm_bo_validate(bo, &abo->placement, &ctx);
|
2017-06-28 10:33:21 +08:00
|
|
|
if (unlikely(r != 0))
|
2015-05-21 23:03:46 +08:00
|
|
|
return r;
|
|
|
|
|
|
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
|
|
/* this should never happen */
|
2017-06-28 10:33:21 +08:00
|
|
|
if (bo->mem.mem_type == TTM_PL_VRAM &&
|
2018-01-12 21:52:22 +08:00
|
|
|
(offset + size) > adev->gmc.visible_vram_size)
|
2015-05-21 23:03:46 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2015-04-21 04:55:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_bo_fence - add fence to buffer object
|
|
|
|
*
|
|
|
|
* @bo: buffer object in question
|
|
|
|
* @fence: fence to add
|
|
|
|
* @shared: true if fence should be added shared
|
|
|
|
*
|
|
|
|
*/
|
2016-10-25 20:00:45 +08:00
|
|
|
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
|
2015-04-21 04:55:21 +08:00
|
|
|
bool shared)
|
|
|
|
{
|
|
|
|
struct reservation_object *resv = bo->tbo.resv;
|
|
|
|
|
|
|
|
if (shared)
|
2015-08-03 11:38:09 +08:00
|
|
|
reservation_object_add_shared_fence(resv, fence);
|
2015-04-21 04:55:21 +08:00
|
|
|
else
|
2015-08-03 11:38:09 +08:00
|
|
|
reservation_object_add_excl_fence(resv, fence);
|
2015-04-21 04:55:21 +08:00
|
|
|
}
|
2016-07-25 23:56:18 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_bo_gpu_offset - return GPU offset of bo
|
|
|
|
* @bo: amdgpu object for which we query the offset
|
|
|
|
*
|
|
|
|
* Returns current GPU offset of the object.
|
|
|
|
*
|
|
|
|
* Note: object should either be pinned or reserved when calling this
|
|
|
|
* function, it might be useful to add check for this for debugging.
|
|
|
|
*/
|
|
|
|
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
|
|
|
|
{
|
|
|
|
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
|
2016-09-05 23:00:57 +08:00
|
|
|
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
|
2017-10-27 20:17:09 +08:00
|
|
|
!amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
|
2016-07-25 23:56:18 +08:00
|
|
|
WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
|
|
|
|
!bo->pin_count);
|
2016-09-07 21:10:44 +08:00
|
|
|
WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
|
2016-08-15 23:00:22 +08:00
|
|
|
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
|
|
|
|
!(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
|
2016-07-25 23:56:18 +08:00
|
|
|
|
|
|
|
return bo->tbo.offset;
|
|
|
|
}
|