2018-12-07 08:53:12 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for UniPhier SoCs
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* Copyright 2018 Socionext Inc.
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* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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2019-12-16 06:39:37 +08:00
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#include <linux/init.h>
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2018-12-07 08:53:12 +08:00
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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#define PCL_PINCTRL0 0x002c
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#define PCL_PERST_PLDN_REGEN BIT(12)
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#define PCL_PERST_NOE_REGEN BIT(11)
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#define PCL_PERST_OUT_REGEN BIT(8)
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#define PCL_PERST_PLDN_REGVAL BIT(4)
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#define PCL_PERST_NOE_REGVAL BIT(3)
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#define PCL_PERST_OUT_REGVAL BIT(0)
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#define PCL_PIPEMON 0x0044
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#define PCL_PCLK_ALIVE BIT(15)
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2019-11-07 12:58:14 +08:00
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#define PCL_MODE 0x8000
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#define PCL_MODE_REGEN BIT(8)
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#define PCL_MODE_REGVAL BIT(0)
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2018-12-07 08:53:12 +08:00
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#define PCL_APP_READY_CTRL 0x8008
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#define PCL_APP_LTSSM_ENABLE BIT(0)
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#define PCL_APP_PM0 0x8078
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#define PCL_SYS_AUX_PWR_DET BIT(8)
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#define PCL_RCV_INT 0x8108
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#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
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#define PCL_CFG_BW_MGT_STATUS BIT(4)
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#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
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#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
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#define PCL_CFG_PME_MSI_STATUS BIT(1)
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#define PCL_RCV_INTX 0x810c
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#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
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#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
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#define PCL_RCV_INTX_MASK_SHIFT 8
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#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
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#define PCL_RCV_INTX_STATUS_SHIFT 0
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#define PCL_STATUS_LINK 0x8140
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#define PCL_RDLH_LINK_UP BIT(1)
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#define PCL_XMLH_LINK_UP BIT(0)
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie {
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2018-12-07 08:53:12 +08:00
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struct dw_pcie pci;
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2021-12-23 09:10:51 +08:00
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void __iomem *base;
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2018-12-07 08:53:12 +08:00
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struct clk *clk;
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struct reset_control *rst;
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struct phy *phy;
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struct irq_domain *legacy_irq_domain;
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};
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#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
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2021-12-23 09:10:51 +08:00
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static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie,
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2018-12-07 08:53:12 +08:00
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bool enable)
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{
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u32 val;
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_APP_READY_CTRL);
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2018-12-07 08:53:12 +08:00
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if (enable)
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val |= PCL_APP_LTSSM_ENABLE;
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else
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val &= ~PCL_APP_LTSSM_ENABLE;
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_APP_READY_CTRL);
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2018-12-07 08:53:12 +08:00
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}
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2021-12-23 09:10:51 +08:00
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static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie)
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2018-12-07 08:53:12 +08:00
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{
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u32 val;
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2019-11-07 12:58:14 +08:00
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/* set RC MODE */
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_MODE);
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2019-11-07 12:58:14 +08:00
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val |= PCL_MODE_REGEN;
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val &= ~PCL_MODE_REGVAL;
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_MODE);
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2019-11-07 12:58:14 +08:00
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2018-12-07 08:53:12 +08:00
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/* use auxiliary power detection */
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_APP_PM0);
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2018-12-07 08:53:12 +08:00
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val |= PCL_SYS_AUX_PWR_DET;
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_APP_PM0);
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2018-12-07 08:53:12 +08:00
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/* assert PERST# */
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_PINCTRL0);
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2018-12-07 08:53:12 +08:00
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val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
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| PCL_PERST_PLDN_REGVAL);
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val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
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| PCL_PERST_PLDN_REGEN;
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_PINCTRL0);
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2018-12-07 08:53:12 +08:00
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2021-12-23 09:10:51 +08:00
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uniphier_pcie_ltssm_enable(pcie, false);
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2018-12-07 08:53:12 +08:00
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usleep_range(100000, 200000);
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/* deassert PERST# */
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_PINCTRL0);
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2018-12-07 08:53:12 +08:00
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val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_PINCTRL0);
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2018-12-07 08:53:12 +08:00
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}
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2021-12-23 09:10:51 +08:00
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static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie)
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2018-12-07 08:53:12 +08:00
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{
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u32 status;
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int ret;
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/* wait PIPE clock */
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2021-12-23 09:10:51 +08:00
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ret = readl_poll_timeout(pcie->base + PCL_PIPEMON, status,
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2018-12-07 08:53:12 +08:00
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status & PCL_PCLK_ALIVE, 100000, 1000000);
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if (ret) {
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2021-12-23 09:10:51 +08:00
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dev_err(pcie->pci.dev,
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2018-12-07 08:53:12 +08:00
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"Failed to initialize controller in RC mode\n");
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return ret;
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}
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return 0;
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}
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static int uniphier_pcie_link_up(struct dw_pcie *pci)
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{
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2018-12-07 08:53:12 +08:00
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u32 val, mask;
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_STATUS_LINK);
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2018-12-07 08:53:12 +08:00
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mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
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return (val & mask) == mask;
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}
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2020-11-06 05:11:53 +08:00
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static int uniphier_pcie_start_link(struct dw_pcie *pci)
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2018-12-07 08:53:12 +08:00
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{
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2018-12-07 08:53:12 +08:00
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2021-12-23 09:10:51 +08:00
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uniphier_pcie_ltssm_enable(pcie, true);
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2018-12-07 08:53:12 +08:00
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2020-11-06 05:11:53 +08:00
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return 0;
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2018-12-07 08:53:12 +08:00
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}
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static void uniphier_pcie_stop_link(struct dw_pcie *pci)
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{
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2018-12-07 08:53:12 +08:00
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2021-12-23 09:10:51 +08:00
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uniphier_pcie_ltssm_enable(pcie, false);
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2018-12-07 08:53:12 +08:00
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}
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2021-12-23 09:10:51 +08:00
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static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie)
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2018-12-07 08:53:12 +08:00
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{
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2021-12-23 09:10:51 +08:00
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writel(PCL_RCV_INT_ALL_ENABLE, pcie->base + PCL_RCV_INT);
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writel(PCL_RCV_INTX_ALL_ENABLE, pcie->base + PCL_RCV_INTX);
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2018-12-07 08:53:12 +08:00
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}
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2021-12-23 09:10:51 +08:00
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2018-12-07 08:53:12 +08:00
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static void uniphier_pcie_irq_mask(struct irq_data *d)
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{
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2022-06-24 22:34:25 +08:00
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struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
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2018-12-07 08:53:12 +08:00
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2021-09-18 08:22:59 +08:00
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unsigned long flags;
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2018-12-07 08:53:12 +08:00
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u32 val;
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2021-09-18 08:22:59 +08:00
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raw_spin_lock_irqsave(&pp->lock, flags);
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_RCV_INTX);
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2018-12-07 08:53:12 +08:00
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val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_RCV_INTX);
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2021-09-18 08:22:59 +08:00
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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2018-12-07 08:53:12 +08:00
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}
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static void uniphier_pcie_irq_unmask(struct irq_data *d)
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{
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2022-06-24 22:34:25 +08:00
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struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
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2018-12-07 08:53:12 +08:00
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2021-09-18 08:22:59 +08:00
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unsigned long flags;
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2018-12-07 08:53:12 +08:00
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u32 val;
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2021-09-18 08:22:59 +08:00
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raw_spin_lock_irqsave(&pp->lock, flags);
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_RCV_INTX);
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2018-12-07 08:53:12 +08:00
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val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_RCV_INTX);
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2021-09-18 08:22:59 +08:00
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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2018-12-07 08:53:12 +08:00
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}
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static struct irq_chip uniphier_pcie_irq_chip = {
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.name = "PCI",
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.irq_mask = uniphier_pcie_irq_mask,
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.irq_unmask = uniphier_pcie_irq_unmask,
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};
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static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops uniphier_intx_domain_ops = {
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.map = uniphier_pcie_intx_map,
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};
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static void uniphier_pcie_irq_handler(struct irq_desc *desc)
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{
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2022-06-24 22:34:25 +08:00
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struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
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2018-12-07 08:53:12 +08:00
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2018-12-07 08:53:12 +08:00
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long reg;
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2021-08-03 00:26:19 +08:00
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u32 val, bit;
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2018-12-07 08:53:12 +08:00
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/* INT for debug */
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_RCV_INT);
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2018-12-07 08:53:12 +08:00
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if (val & PCL_CFG_BW_MGT_STATUS)
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dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
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if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
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dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
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if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
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dev_dbg(pci->dev, "Root Error\n");
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if (val & PCL_CFG_PME_MSI_STATUS)
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dev_dbg(pci->dev, "PME Interrupt\n");
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2021-12-23 09:10:51 +08:00
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writel(val, pcie->base + PCL_RCV_INT);
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2018-12-07 08:53:12 +08:00
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/* INTx */
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chained_irq_enter(chip, desc);
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2021-12-23 09:10:51 +08:00
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val = readl(pcie->base + PCL_RCV_INTX);
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2018-12-07 08:53:12 +08:00
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reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
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2021-08-03 00:26:19 +08:00
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for_each_set_bit(bit, ®, PCI_NUM_INTX)
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2021-12-23 09:10:51 +08:00
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generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
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2018-12-07 08:53:12 +08:00
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chained_irq_exit(chip, desc);
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}
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2022-06-24 22:34:25 +08:00
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static int uniphier_pcie_config_legacy_irq(struct dw_pcie_rp *pp)
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2018-12-07 08:53:12 +08:00
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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2021-12-23 09:10:51 +08:00
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struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
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2018-12-07 08:53:12 +08:00
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struct device_node *np = pci->dev->of_node;
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struct device_node *np_intc;
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2019-02-27 12:40:37 +08:00
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int ret = 0;
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2018-12-07 08:53:12 +08:00
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np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
|
|
|
|
if (!np_intc) {
|
|
|
|
dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
pp->irq = irq_of_parse_and_map(np_intc, 0);
|
|
|
|
if (!pp->irq) {
|
|
|
|
dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
|
2019-02-27 12:40:37 +08:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out_put_node;
|
2018-12-07 08:53:12 +08:00
|
|
|
}
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
|
2018-12-07 08:53:12 +08:00
|
|
|
&uniphier_intx_domain_ops, pp);
|
2021-12-23 09:10:51 +08:00
|
|
|
if (!pcie->legacy_irq_domain) {
|
2018-12-07 08:53:12 +08:00
|
|
|
dev_err(pci->dev, "Failed to get INTx domain\n");
|
2019-02-27 12:40:37 +08:00
|
|
|
ret = -ENODEV;
|
|
|
|
goto out_put_node;
|
2018-12-07 08:53:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
|
|
|
|
pp);
|
|
|
|
|
2019-02-27 12:40:37 +08:00
|
|
|
out_put_node:
|
|
|
|
of_node_put(np_intc);
|
|
|
|
return ret;
|
2018-12-07 08:53:12 +08:00
|
|
|
}
|
|
|
|
|
2022-06-24 22:34:25 +08:00
|
|
|
static int uniphier_pcie_host_init(struct dw_pcie_rp *pp)
|
2018-12-07 08:53:12 +08:00
|
|
|
{
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
2021-12-23 09:10:51 +08:00
|
|
|
struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
|
2018-12-07 08:53:12 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = uniphier_pcie_config_legacy_irq(pp);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
uniphier_pcie_irq_enable(pcie);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
|
|
|
|
.host_init = uniphier_pcie_host_init,
|
|
|
|
};
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
static int uniphier_pcie_host_enable(struct uniphier_pcie *pcie)
|
2018-12-07 08:53:12 +08:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
ret = clk_prepare_enable(pcie->clk);
|
2018-12-07 08:53:12 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
ret = reset_control_deassert(pcie->rst);
|
2018-12-07 08:53:12 +08:00
|
|
|
if (ret)
|
|
|
|
goto out_clk_disable;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
uniphier_pcie_init_rc(pcie);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
ret = phy_init(pcie->phy);
|
2018-12-07 08:53:12 +08:00
|
|
|
if (ret)
|
|
|
|
goto out_rst_assert;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
ret = uniphier_pcie_wait_rc(pcie);
|
2018-12-07 08:53:12 +08:00
|
|
|
if (ret)
|
|
|
|
goto out_phy_exit;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_phy_exit:
|
2021-12-23 09:10:51 +08:00
|
|
|
phy_exit(pcie->phy);
|
2018-12-07 08:53:12 +08:00
|
|
|
out_rst_assert:
|
2021-12-23 09:10:51 +08:00
|
|
|
reset_control_assert(pcie->rst);
|
2018-12-07 08:53:12 +08:00
|
|
|
out_clk_disable:
|
2021-12-23 09:10:51 +08:00
|
|
|
clk_disable_unprepare(pcie->clk);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
2020-11-06 05:11:53 +08:00
|
|
|
.start_link = uniphier_pcie_start_link,
|
2018-12-07 08:53:12 +08:00
|
|
|
.stop_link = uniphier_pcie_stop_link,
|
|
|
|
.link_up = uniphier_pcie_link_up,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int uniphier_pcie_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
2021-12-23 09:10:51 +08:00
|
|
|
struct uniphier_pcie *pcie;
|
2018-12-07 08:53:12 +08:00
|
|
|
int ret;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
|
|
|
if (!pcie)
|
2018-12-07 08:53:12 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->pci.dev = dev;
|
|
|
|
pcie->pci.ops = &dw_pcie_ops;
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->base = devm_platform_ioremap_resource_byname(pdev, "link");
|
|
|
|
if (IS_ERR(pcie->base))
|
|
|
|
return PTR_ERR(pcie->base);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->clk = devm_clk_get(dev, NULL);
|
|
|
|
if (IS_ERR(pcie->clk))
|
|
|
|
return PTR_ERR(pcie->clk);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->rst = devm_reset_control_get_shared(dev, NULL);
|
|
|
|
if (IS_ERR(pcie->rst))
|
|
|
|
return PTR_ERR(pcie->rst);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
|
|
|
|
if (IS_ERR(pcie->phy))
|
|
|
|
return PTR_ERR(pcie->phy);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
platform_set_drvdata(pdev, pcie);
|
2018-12-07 08:53:12 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
ret = uniphier_pcie_host_enable(pcie);
|
2018-12-07 08:53:12 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
pcie->pci.pp.ops = &uniphier_pcie_host_ops;
|
2020-11-06 05:11:56 +08:00
|
|
|
|
2021-12-23 09:10:51 +08:00
|
|
|
return dw_pcie_host_init(&pcie->pci.pp);
|
2018-12-07 08:53:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id uniphier_pcie_match[] = {
|
|
|
|
{ .compatible = "socionext,uniphier-pcie", },
|
|
|
|
{ /* sentinel */ },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver uniphier_pcie_driver = {
|
|
|
|
.probe = uniphier_pcie_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "uniphier-pcie",
|
|
|
|
.of_match_table = uniphier_pcie_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
builtin_platform_driver(uniphier_pcie_driver);
|