2018-01-27 02:50:27 +08:00
|
|
|
// SPDX-License-Identifier: GPL-2.0
|
2015-10-30 09:02:51 +08:00
|
|
|
/*
|
2015-11-27 01:17:05 +08:00
|
|
|
* PCIe host controller driver for HiSilicon SoCs
|
2015-10-30 09:02:51 +08:00
|
|
|
*
|
|
|
|
* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
|
|
|
|
*
|
2015-11-27 01:17:05 +08:00
|
|
|
* Authors: Zhou Wang <wangzhou1@hisilicon.com>
|
|
|
|
* Dacai Zhu <zhudacai@hisilicon.com>
|
|
|
|
* Gabriele Paoloni <gabriele.paoloni@huawei.com>
|
2015-10-30 09:02:51 +08:00
|
|
|
*/
|
|
|
|
#include <linux/interrupt.h>
|
2016-07-03 07:13:25 +08:00
|
|
|
#include <linux/init.h>
|
2015-10-30 09:02:51 +08:00
|
|
|
#include <linux/platform_device.h>
|
2016-12-01 14:45:35 +08:00
|
|
|
#include <linux/pci.h>
|
|
|
|
#include <linux/pci-acpi.h>
|
|
|
|
#include <linux/pci-ecam.h>
|
2018-05-31 09:12:37 +08:00
|
|
|
#include "../../pci.h"
|
2016-12-01 14:45:35 +08:00
|
|
|
|
2017-02-06 14:25:04 +08:00
|
|
|
#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
|
2016-12-01 14:45:35 +08:00
|
|
|
|
2021-12-24 05:37:48 +08:00
|
|
|
struct hisi_pcie {
|
|
|
|
void __iomem *reg_base;
|
|
|
|
};
|
|
|
|
|
2017-02-07 22:41:09 +08:00
|
|
|
static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
|
|
int size, u32 *val)
|
2016-12-01 14:45:35 +08:00
|
|
|
{
|
|
|
|
struct pci_config_window *cfg = bus->sysdata;
|
|
|
|
int dev = PCI_SLOT(devfn);
|
|
|
|
|
|
|
|
if (bus->number == cfg->busr.start) {
|
|
|
|
/* access only one slot on each root port */
|
|
|
|
if (dev > 0)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
else
|
|
|
|
return pci_generic_config_read32(bus, devfn, where,
|
|
|
|
size, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return pci_generic_config_read(bus, devfn, where, size, val);
|
|
|
|
}
|
|
|
|
|
2017-02-07 22:41:09 +08:00
|
|
|
static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
|
|
int where, int size, u32 val)
|
2016-12-01 14:45:35 +08:00
|
|
|
{
|
|
|
|
struct pci_config_window *cfg = bus->sysdata;
|
|
|
|
int dev = PCI_SLOT(devfn);
|
|
|
|
|
|
|
|
if (bus->number == cfg->busr.start) {
|
|
|
|
/* access only one slot on each root port */
|
|
|
|
if (dev > 0)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
else
|
|
|
|
return pci_generic_config_write32(bus, devfn, where,
|
|
|
|
size, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return pci_generic_config_write(bus, devfn, where, size, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where)
|
|
|
|
{
|
|
|
|
struct pci_config_window *cfg = bus->sysdata;
|
2021-12-24 05:37:48 +08:00
|
|
|
struct hisi_pcie *pcie = cfg->priv;
|
2016-12-01 14:45:35 +08:00
|
|
|
|
|
|
|
if (bus->number == cfg->busr.start)
|
2021-12-24 05:37:48 +08:00
|
|
|
return pcie->reg_base + where;
|
2016-12-01 14:45:35 +08:00
|
|
|
else
|
|
|
|
return pci_ecam_map_bus(bus, devfn, where);
|
|
|
|
}
|
|
|
|
|
2017-02-06 14:25:04 +08:00
|
|
|
#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
|
|
|
|
|
2016-12-01 14:45:35 +08:00
|
|
|
static int hisi_pcie_init(struct pci_config_window *cfg)
|
|
|
|
{
|
|
|
|
struct device *dev = cfg->parent;
|
2021-12-24 05:37:48 +08:00
|
|
|
struct hisi_pcie *pcie;
|
2016-12-01 14:45:35 +08:00
|
|
|
struct acpi_device *adev = to_acpi_device(dev);
|
|
|
|
struct acpi_pci_root *root = acpi_driver_data(adev);
|
|
|
|
struct resource *res;
|
|
|
|
int ret;
|
|
|
|
|
2021-12-24 05:37:48 +08:00
|
|
|
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
|
|
|
if (!pcie)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2016-12-01 14:45:35 +08:00
|
|
|
/*
|
|
|
|
* Retrieve RC base and size from a HISI0081 device with _UID
|
|
|
|
* matching our segment.
|
|
|
|
*/
|
|
|
|
res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
|
|
|
|
if (!res)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "can't get rc base address\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2021-12-24 05:37:48 +08:00
|
|
|
pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
|
|
|
|
if (!pcie->reg_base)
|
2016-12-01 14:45:35 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2021-12-24 05:37:48 +08:00
|
|
|
cfg->priv = pcie;
|
2016-12-01 14:45:35 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-10 07:49:21 +08:00
|
|
|
const struct pci_ecam_ops hisi_pcie_ops = {
|
2016-12-01 14:45:35 +08:00
|
|
|
.init = hisi_pcie_init,
|
|
|
|
.pci_ops = {
|
|
|
|
.map_bus = hisi_pcie_map_bus,
|
2017-02-07 22:41:09 +08:00
|
|
|
.read = hisi_pcie_rd_conf,
|
|
|
|
.write = hisi_pcie_wr_conf,
|
2016-12-01 14:45:35 +08:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI_HISI
|
2015-10-30 09:02:51 +08:00
|
|
|
|
2017-02-06 14:25:04 +08:00
|
|
|
static int hisi_pcie_platform_init(struct pci_config_window *cfg)
|
|
|
|
{
|
|
|
|
struct device *dev = cfg->parent;
|
2021-12-24 05:37:48 +08:00
|
|
|
struct hisi_pcie *pcie;
|
2017-02-06 14:25:04 +08:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct resource *res;
|
2021-12-24 05:37:48 +08:00
|
|
|
|
|
|
|
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
|
|
|
if (!pcie)
|
|
|
|
return -ENOMEM;
|
2017-02-06 14:25:04 +08:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "missing \"reg[1]\"property\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-12-24 05:37:48 +08:00
|
|
|
pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
|
|
|
|
if (!pcie->reg_base)
|
2017-02-06 14:25:04 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2021-12-24 05:37:48 +08:00
|
|
|
cfg->priv = pcie;
|
2017-02-06 14:25:04 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-05 01:59:16 +08:00
|
|
|
static const struct pci_ecam_ops hisi_pcie_platform_ops = {
|
2017-02-06 14:25:04 +08:00
|
|
|
.init = hisi_pcie_platform_init,
|
|
|
|
.pci_ops = {
|
|
|
|
.map_bus = hisi_pcie_map_bus,
|
2017-02-07 22:41:09 +08:00
|
|
|
.read = hisi_pcie_rd_conf,
|
|
|
|
.write = hisi_pcie_wr_conf,
|
2017-02-06 14:25:04 +08:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
|
|
|
|
{
|
2017-03-23 21:18:17 +08:00
|
|
|
.compatible = "hisilicon,hip06-pcie-ecam",
|
2020-04-10 07:49:21 +08:00
|
|
|
.data = &hisi_pcie_platform_ops,
|
2017-02-06 14:25:04 +08:00
|
|
|
},
|
2017-03-23 21:18:17 +08:00
|
|
|
{
|
|
|
|
.compatible = "hisilicon,hip07-pcie-ecam",
|
2020-04-10 07:49:21 +08:00
|
|
|
.data = &hisi_pcie_platform_ops,
|
2017-03-23 21:18:17 +08:00
|
|
|
},
|
2017-02-06 14:25:04 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver hisi_pcie_almost_ecam_driver = {
|
2020-04-10 07:49:23 +08:00
|
|
|
.probe = pci_host_common_probe,
|
2017-02-06 14:25:04 +08:00
|
|
|
.driver = {
|
|
|
|
.name = "hisi-pcie-almost-ecam",
|
|
|
|
.of_match_table = hisi_pcie_almost_ecam_of_match,
|
2017-04-21 04:36:25 +08:00
|
|
|
.suppress_bind_attrs = true,
|
2017-02-06 14:25:04 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
builtin_platform_driver(hisi_pcie_almost_ecam_driver);
|
|
|
|
|
|
|
|
#endif
|
2016-12-01 14:45:35 +08:00
|
|
|
#endif
|