2005-06-24 13:01:16 +08:00
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/*
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* arch/xtensa/kernel/vmlinux.lds.S
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*
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* Xtensa linker script
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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2013-01-05 08:57:17 +08:00
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* Copyright (C) 2001 - 2008 Tensilica Inc.
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2005-06-24 13:01:16 +08:00
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*
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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*/
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2019-10-30 05:13:47 +08:00
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#define RO_EXCEPTION_TABLE_ALIGN 16
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2005-06-24 13:01:16 +08:00
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#include <asm-generic/vmlinux.lds.h>
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2009-09-24 22:36:19 +08:00
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#include <asm/page.h>
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#include <asm/thread_info.h>
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2005-06-24 13:01:16 +08:00
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2019-01-02 11:41:55 +08:00
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#include <asm/core.h>
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2012-12-03 19:01:43 +08:00
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#include <asm/vectors.h>
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2018-08-14 09:14:14 +08:00
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2005-06-24 13:01:16 +08:00
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OUTPUT_ARCH(xtensa)
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ENTRY(_start)
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2006-12-10 18:18:48 +08:00
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#ifdef __XTENSA_EB__
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2005-06-24 13:01:16 +08:00
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jiffies = jiffies_64 + 4;
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#else
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jiffies = jiffies_64;
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#endif
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/* Note: In the following macros, it would be nice to specify only the
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vector name and section kind and construct "sym" and "section" using
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CPP concatenation, but that does not work reliably. Concatenating a
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string with "." produces an invalid token. CPP will not print a
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warning because it thinks this is an assembly file, but it leaves
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them as multiple tokens and there may or may not be whitespace
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between them. */
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/* Macro for a relocation entry */
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#define RELOCATE_ENTRY(sym, section) \
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LONG(sym ## _start); \
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LONG(sym ## _end); \
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LONG(LOADADDR(section))
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2020-02-01 12:11:24 +08:00
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#if !defined(CONFIG_VECTORS_ADDR) && XCHAL_HAVE_VECBASE
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#define MERGED_VECTORS 1
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#else
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#define MERGED_VECTORS 0
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#endif
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2017-12-04 12:55:35 +08:00
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/*
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2020-02-01 12:11:24 +08:00
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* Macro to define a section for a vector. When MERGED_VECTORS is 0
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* code for every vector is located with other init data. At startup
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2017-12-04 12:55:35 +08:00
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* time head.S copies code for every vector to its final position according
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* to description recorded in the corresponding RELOCATE_ENTRY.
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2005-06-24 13:01:16 +08:00
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*/
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2020-02-01 13:25:03 +08:00
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#define SECTION_VECTOR4(sym, section, addr, prevsec) \
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2017-12-04 12:55:35 +08:00
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section addr : AT(((LOADADDR(prevsec) + SIZEOF(prevsec)) + 3) & ~ 3) \
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2005-06-24 13:01:16 +08:00
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{ \
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. = ALIGN(4); \
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sym ## _start = ABSOLUTE(.); \
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*(section) \
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sym ## _end = ABSOLUTE(.); \
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}
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2020-02-01 13:25:03 +08:00
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#define SECTION_VECTOR2(section, addr) \
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2017-01-05 02:40:49 +08:00
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. = addr; \
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*(section)
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2005-06-24 13:01:16 +08:00
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/*
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* Mapping of input sections to output sections when linking.
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*/
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SECTIONS
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{
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2006-12-10 18:18:48 +08:00
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. = KERNELOFFSET;
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2005-06-24 13:01:16 +08:00
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/* .text section */
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_text = .;
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_stext = .;
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.text :
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{
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2009-04-26 10:10:57 +08:00
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/* The HEAD_TEXT section must be the first section! */
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HEAD_TEXT
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2017-01-05 02:40:49 +08:00
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2020-02-01 12:11:24 +08:00
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#if MERGED_VECTORS
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2020-02-01 13:25:03 +08:00
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. = ALIGN(PAGE_SIZE);
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_vecbase = .;
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2017-01-05 02:40:49 +08:00
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.WindowVectors.text, WINDOW_VECTORS_VADDR)
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2017-01-05 02:40:49 +08:00
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#if XCHAL_EXCM_LEVEL >= 2
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.Level2InterruptVector.text, INTLEVEL2_VECTOR_VADDR)
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2017-01-05 02:40:49 +08:00
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.Level3InterruptVector.text, INTLEVEL3_VECTOR_VADDR)
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2017-01-05 02:40:49 +08:00
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.Level4InterruptVector.text, INTLEVEL4_VECTOR_VADDR)
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2017-01-05 02:40:49 +08:00
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.Level5InterruptVector.text, INTLEVEL5_VECTOR_VADDR)
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2017-01-05 02:40:49 +08:00
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.Level6InterruptVector.text, INTLEVEL6_VECTOR_VADDR)
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2017-01-05 02:40:49 +08:00
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#endif
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR2 (.DebugInterruptVector.text, DEBUG_VECTOR_VADDR)
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SECTION_VECTOR2 (.KernelExceptionVector.text, KERNEL_VECTOR_VADDR)
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SECTION_VECTOR2 (.UserExceptionVector.text, USER_VECTOR_VADDR)
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SECTION_VECTOR2 (.DoubleExceptionVector.text, DOUBLEEXC_VECTOR_VADDR)
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2020-02-01 10:48:43 +08:00
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2020-02-01 13:25:03 +08:00
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*(.exception.text)
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2017-01-05 02:40:49 +08:00
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#endif
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2017-12-04 12:55:35 +08:00
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IRQENTRY_TEXT
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SOFTIRQENTRY_TEXT
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ENTRY_TEXT
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2009-04-21 15:34:15 +08:00
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TEXT_TEXT
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2017-12-04 12:55:35 +08:00
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SCHED_TEXT
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CPUIDLE_TEXT
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LOCK_TEXT
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2019-10-15 02:33:44 +08:00
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*(.fixup)
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2005-06-24 13:01:16 +08:00
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}
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_etext = .;
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2007-06-01 08:47:01 +08:00
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PROVIDE (etext = .);
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2005-06-24 13:01:16 +08:00
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. = ALIGN(16);
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2019-10-30 05:13:33 +08:00
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RO_DATA(4096)
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2005-06-24 13:01:16 +08:00
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/* Data section */
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2017-01-04 09:57:51 +08:00
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#ifdef CONFIG_XIP_KERNEL
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INIT_TEXT_SECTION(PAGE_SIZE)
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#else
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2012-06-21 03:52:58 +08:00
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_sdata = .;
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2019-10-30 05:13:35 +08:00
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RW_DATA(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, THREAD_SIZE)
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2005-06-24 13:01:16 +08:00
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_edata = .;
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/* Initialization code and data: */
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2009-09-24 22:36:19 +08:00
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. = ALIGN(PAGE_SIZE);
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2005-06-24 13:01:16 +08:00
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__init_begin = .;
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2009-09-24 22:36:19 +08:00
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INIT_TEXT_SECTION(PAGE_SIZE)
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2005-06-24 13:01:16 +08:00
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.init.data :
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{
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2008-01-20 21:15:03 +08:00
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INIT_DATA
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2017-01-04 09:57:51 +08:00
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}
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#endif
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.init.rodata :
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{
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2005-06-24 13:01:16 +08:00
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. = ALIGN(0x4);
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__tagtable_begin = .;
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*(.taglist)
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__tagtable_end = .;
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2007-06-01 08:47:01 +08:00
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. = ALIGN(16);
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__boot_reloc_table_start = ABSOLUTE(.);
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2020-02-01 12:11:24 +08:00
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#if !MERGED_VECTORS
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2007-06-01 08:47:01 +08:00
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RELOCATE_ENTRY(_WindowVectors_text,
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.WindowVectors.text);
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2013-01-05 08:57:17 +08:00
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#if XCHAL_EXCM_LEVEL >= 2
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RELOCATE_ENTRY(_Level2InterruptVector_text,
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.Level2InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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RELOCATE_ENTRY(_Level3InterruptVector_text,
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.Level3InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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RELOCATE_ENTRY(_Level4InterruptVector_text,
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.Level4InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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RELOCATE_ENTRY(_Level5InterruptVector_text,
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.Level5InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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RELOCATE_ENTRY(_Level6InterruptVector_text,
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.Level6InterruptVector.text);
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#endif
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2007-06-01 08:47:01 +08:00
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RELOCATE_ENTRY(_KernelExceptionVector_text,
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.KernelExceptionVector.text);
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RELOCATE_ENTRY(_UserExceptionVector_text,
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.UserExceptionVector.text);
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RELOCATE_ENTRY(_DoubleExceptionVector_text,
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.DoubleExceptionVector.text);
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2007-12-31 14:00:54 +08:00
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RELOCATE_ENTRY(_DebugInterruptVector_text,
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.DebugInterruptVector.text);
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2020-02-01 10:48:43 +08:00
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RELOCATE_ENTRY(_exception_text,
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.exception.text);
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2017-01-05 02:40:49 +08:00
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#endif
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2017-01-04 09:57:51 +08:00
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#ifdef CONFIG_XIP_KERNEL
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RELOCATE_ENTRY(_xip_data, .data);
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RELOCATE_ENTRY(_xip_init_data, .init.data);
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2020-02-01 13:25:03 +08:00
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#endif
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2013-10-17 06:42:26 +08:00
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#if defined(CONFIG_SMP)
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RELOCATE_ENTRY(_SecondaryResetVector_text,
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.SecondaryResetVector.text);
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#endif
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2007-06-01 08:47:01 +08:00
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__boot_reloc_table_end = ABSOLUTE(.) ;
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2005-06-24 13:01:16 +08:00
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2009-09-24 22:36:19 +08:00
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INIT_SETUP(XCHAL_ICACHE_LINESIZE)
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INIT_CALLS
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CON_INITCALL
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INIT_RAM_FS
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2005-06-24 13:01:16 +08:00
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}
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2007-06-01 08:47:01 +08:00
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2011-03-25 01:50:09 +08:00
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PERCPU_SECTION(XCHAL_ICACHE_LINESIZE)
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2007-06-01 08:47:01 +08:00
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2005-06-24 13:01:16 +08:00
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/* We need this dummy segment here */
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. = ALIGN(4);
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.dummy : { LONG(0) }
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2020-02-01 13:25:03 +08:00
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#undef LAST
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#define LAST .dummy
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2020-02-01 12:11:24 +08:00
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#if !MERGED_VECTORS
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2005-06-24 13:01:16 +08:00
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/* The vectors are relocated to the real position at startup time */
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2020-02-01 13:25:03 +08:00
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SECTION_VECTOR4 (_WindowVectors_text,
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2005-06-24 13:01:16 +08:00
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.WindowVectors.text,
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2017-12-04 12:55:35 +08:00
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WINDOW_VECTORS_VADDR,
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2005-06-24 13:01:16 +08:00
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.dummy)
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2020-02-01 13:25:03 +08:00
|
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SECTION_VECTOR4 (_DebugInterruptVector_text,
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2005-06-24 13:01:16 +08:00
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.DebugInterruptVector.text,
|
2012-12-03 19:01:43 +08:00
|
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DEBUG_VECTOR_VADDR,
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2017-12-04 12:55:35 +08:00
|
|
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.WindowVectors.text)
|
2013-01-05 08:57:17 +08:00
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#undef LAST
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#define LAST .DebugInterruptVector.text
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#if XCHAL_EXCM_LEVEL >= 2
|
2020-02-01 13:25:03 +08:00
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SECTION_VECTOR4 (_Level2InterruptVector_text,
|
2013-01-05 08:57:17 +08:00
|
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.Level2InterruptVector.text,
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2012-12-03 19:01:43 +08:00
|
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INTLEVEL2_VECTOR_VADDR,
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2017-12-04 12:55:35 +08:00
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LAST)
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2013-01-05 08:57:17 +08:00
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# undef LAST
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# define LAST .Level2InterruptVector.text
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#endif
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|
#if XCHAL_EXCM_LEVEL >= 3
|
2020-02-01 13:25:03 +08:00
|
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SECTION_VECTOR4 (_Level3InterruptVector_text,
|
2013-01-05 08:57:17 +08:00
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.Level3InterruptVector.text,
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2012-12-03 19:01:43 +08:00
|
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INTLEVEL3_VECTOR_VADDR,
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2017-12-04 12:55:35 +08:00
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LAST)
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2013-01-05 08:57:17 +08:00
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# undef LAST
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# define LAST .Level3InterruptVector.text
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_Level4InterruptVector_text,
|
2013-01-05 08:57:17 +08:00
|
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.Level4InterruptVector.text,
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2012-12-03 19:01:43 +08:00
|
|
|
INTLEVEL4_VECTOR_VADDR,
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2017-12-04 12:55:35 +08:00
|
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LAST)
|
2013-01-05 08:57:17 +08:00
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# undef LAST
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# define LAST .Level4InterruptVector.text
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#endif
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|
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|
#if XCHAL_EXCM_LEVEL >= 5
|
2020-02-01 13:25:03 +08:00
|
|
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SECTION_VECTOR4 (_Level5InterruptVector_text,
|
2013-01-05 08:57:17 +08:00
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.Level5InterruptVector.text,
|
2012-12-03 19:01:43 +08:00
|
|
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INTLEVEL5_VECTOR_VADDR,
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2017-12-04 12:55:35 +08:00
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LAST)
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2013-01-05 08:57:17 +08:00
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# undef LAST
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# define LAST .Level5InterruptVector.text
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#endif
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|
#if XCHAL_EXCM_LEVEL >= 6
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_Level6InterruptVector_text,
|
2013-01-05 08:57:17 +08:00
|
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.Level6InterruptVector.text,
|
2012-12-03 19:01:43 +08:00
|
|
|
INTLEVEL6_VECTOR_VADDR,
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2017-12-04 12:55:35 +08:00
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|
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LAST)
|
2013-01-05 08:57:17 +08:00
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|
# undef LAST
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# define LAST .Level6InterruptVector.text
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|
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|
#endif
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_KernelExceptionVector_text,
|
2005-06-24 13:01:16 +08:00
|
|
|
.KernelExceptionVector.text,
|
2012-12-03 19:01:43 +08:00
|
|
|
KERNEL_VECTOR_VADDR,
|
2017-12-04 12:55:35 +08:00
|
|
|
LAST)
|
|
|
|
#undef LAST
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_UserExceptionVector_text,
|
2005-06-24 13:01:16 +08:00
|
|
|
.UserExceptionVector.text,
|
2012-12-03 19:01:43 +08:00
|
|
|
USER_VECTOR_VADDR,
|
2017-12-04 12:55:35 +08:00
|
|
|
.KernelExceptionVector.text)
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_DoubleExceptionVector_text,
|
2005-06-24 13:01:16 +08:00
|
|
|
.DoubleExceptionVector.text,
|
2012-12-03 19:01:43 +08:00
|
|
|
DOUBLEEXC_VECTOR_VADDR,
|
2017-12-04 12:55:35 +08:00
|
|
|
.UserExceptionVector.text)
|
2020-02-01 10:48:43 +08:00
|
|
|
#define LAST .DoubleExceptionVector.text
|
2013-10-17 06:42:26 +08:00
|
|
|
|
2017-01-05 02:40:49 +08:00
|
|
|
#endif
|
2020-02-01 13:25:03 +08:00
|
|
|
#if defined(CONFIG_SMP)
|
2013-10-17 06:42:26 +08:00
|
|
|
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_SecondaryResetVector_text,
|
2013-10-17 06:42:26 +08:00
|
|
|
.SecondaryResetVector.text,
|
|
|
|
RESET_VECTOR1_VADDR,
|
2020-02-01 13:25:03 +08:00
|
|
|
LAST)
|
2020-02-01 10:48:43 +08:00
|
|
|
#undef LAST
|
|
|
|
#define LAST .SecondaryResetVector.text
|
2013-10-17 06:42:26 +08:00
|
|
|
|
2020-02-01 10:48:43 +08:00
|
|
|
#endif
|
2020-02-01 12:11:24 +08:00
|
|
|
#if !MERGED_VECTORS
|
2020-02-01 13:25:03 +08:00
|
|
|
SECTION_VECTOR4 (_exception_text,
|
2020-02-01 10:48:43 +08:00
|
|
|
.exception.text,
|
|
|
|
,
|
|
|
|
LAST)
|
|
|
|
#undef LAST
|
|
|
|
#define LAST .exception.text
|
2013-10-17 06:42:26 +08:00
|
|
|
|
|
|
|
#endif
|
2020-02-01 10:48:43 +08:00
|
|
|
. = (LOADADDR(LAST) + SIZEOF(LAST) + 3) & ~ 3;
|
2013-10-17 06:42:26 +08:00
|
|
|
|
2020-02-01 12:11:24 +08:00
|
|
|
.dummy1 : AT(ADDR(.dummy1)) { LONG(0) }
|
2009-09-24 22:36:19 +08:00
|
|
|
. = ALIGN(PAGE_SIZE);
|
2005-06-24 13:01:16 +08:00
|
|
|
|
2017-01-04 09:57:51 +08:00
|
|
|
#ifndef CONFIG_XIP_KERNEL
|
2005-06-24 13:01:16 +08:00
|
|
|
__init_end = .;
|
|
|
|
|
2009-09-24 22:36:19 +08:00
|
|
|
BSS_SECTION(0, 8192, 0)
|
2017-01-04 09:57:51 +08:00
|
|
|
#endif
|
2007-06-01 08:47:01 +08:00
|
|
|
|
2005-06-24 13:01:16 +08:00
|
|
|
_end = .;
|
|
|
|
|
2017-01-04 09:57:51 +08:00
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
|
|
. = CONFIG_XIP_DATA_ADDR;
|
|
|
|
|
|
|
|
_xip_start = .;
|
|
|
|
|
|
|
|
#undef LOAD_OFFSET
|
|
|
|
#define LOAD_OFFSET \
|
2020-02-01 12:11:24 +08:00
|
|
|
(CONFIG_XIP_DATA_ADDR - (LOADADDR(.dummy1) + SIZEOF(.dummy1) + 3) & ~ 3)
|
2017-01-04 09:57:51 +08:00
|
|
|
|
|
|
|
_xip_data_start = .;
|
|
|
|
_sdata = .;
|
2019-12-04 04:46:44 +08:00
|
|
|
RW_DATA(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, THREAD_SIZE)
|
2017-01-04 09:57:51 +08:00
|
|
|
_edata = .;
|
|
|
|
_xip_data_end = .;
|
|
|
|
|
|
|
|
/* Initialization data: */
|
|
|
|
|
|
|
|
STRUCT_ALIGN();
|
|
|
|
|
|
|
|
_xip_init_data_start = .;
|
|
|
|
__init_begin = .;
|
|
|
|
.init.data :
|
|
|
|
{
|
|
|
|
INIT_DATA
|
|
|
|
}
|
|
|
|
_xip_init_data_end = .;
|
|
|
|
__init_end = .;
|
|
|
|
BSS_SECTION(0, 8192, 0)
|
|
|
|
|
|
|
|
_xip_end = .;
|
|
|
|
|
|
|
|
#undef LOAD_OFFSET
|
|
|
|
#endif
|
|
|
|
|
2018-10-30 09:30:46 +08:00
|
|
|
DWARF_DEBUG
|
2005-06-24 13:01:16 +08:00
|
|
|
|
2018-10-30 16:28:56 +08:00
|
|
|
.xt.prop 0 : { KEEP(*(.xt.prop .xt.prop.* .gnu.linkonce.prop.*)) }
|
|
|
|
.xt.insn 0 : { KEEP(*(.xt.insn .xt.insn.* .gnu.linkonce.x*)) }
|
|
|
|
.xt.lit 0 : { KEEP(*(.xt.lit .xt.lit.* .gnu.linkonce.p*)) }
|
linker script: unify usage of discard definition
Discarded sections in different archs share some commonality but have
considerable differences. This led to linker script for each arch
implementing its own /DISCARD/ definition, which makes maintaining
tedious and adding new entries error-prone.
This patch makes all linker scripts to move discard definitions to the
end of the linker script and use the common DISCARDS macro. As ld
uses the first matching section definition, archs can include default
discarded sections by including them earlier in the linker script.
ia64 is notable because it first throws away some ia64 specific
subsections and then include the rest of the sections into the final
image, so those sections must be discarded before the inclusion.
defconfig compile tested for x86, x86-64, powerpc, powerpc64, ia64,
alpha, sparc, sparc64 and s390. Michal Simek tested microblaze.
Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Michal Simek <monstr@monstr.eu>
Cc: linux-arch@vger.kernel.org
Cc: Michal Simek <monstr@monstr.eu>
Cc: microblaze-uclinux@itee.uq.edu.au
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Tony Luck <tony.luck@intel.com>
2009-07-09 10:27:40 +08:00
|
|
|
|
|
|
|
/* Sections to be discarded */
|
|
|
|
DISCARDS
|
2005-06-24 13:01:16 +08:00
|
|
|
}
|