2015-08-12 22:43:39 +08:00
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/circ_buf.h>
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#include "i915_drv.h"
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#include "intel_guc.h"
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2015-08-12 22:43:41 +08:00
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/**
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2015-10-20 07:10:54 +08:00
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* DOC: GuC-based command submission
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2015-08-12 22:43:41 +08:00
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*
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* i915_guc_client:
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* We use the term client to avoid confusion with contexts. A i915_guc_client is
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* equivalent to GuC object guc_context_desc. This context descriptor is
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* allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
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* and workqueue for it. Also the process descriptor (guc_process_desc), which
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* is mapped to client space. So the client can write Work Item then ring the
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* doorbell.
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*
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* To simplify the implementation, we allocate one gem object that contains all
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* pages for doorbell, process descriptor and workqueue.
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*
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* The Scratch registers:
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* There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
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* a value to the action register (SOFT_SCRATCH_0) along with any data. It then
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* triggers an interrupt on the GuC via another register write (0xC4C8).
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* Firmware writes a success/fail code back to the action register after
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* processes the request. The kernel driver polls waiting for this update and
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* then proceeds.
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* See host2guc_action()
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*
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* Doorbells:
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* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
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* mapped into process space.
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*
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* Work Items:
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* There are several types of work items that the host may place into a
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* workqueue, each with its own requirements and limitations. Currently only
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* WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
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* represents in-order queue. The kernel driver packs ring tail pointer and an
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* ELSP context descriptor dword into Work Item.
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* See guc_add_workqueue_item()
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*
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*/
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/*
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* Read GuC command/status register (SOFT_SCRATCH_0)
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* Return true if it contains a response rather than a command
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*/
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static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
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u32 *status)
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{
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u32 val = I915_READ(SOFT_SCRATCH(0));
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*status = val;
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return GUC2HOST_IS_RESPONSE(val);
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}
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static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 status;
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int i;
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int ret;
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if (WARN_ON(len < 1 || len > 15))
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return -EINVAL;
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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dev_priv->guc.action_count += 1;
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dev_priv->guc.action_cmd = data[0];
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for (i = 0; i < len; i++)
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I915_WRITE(SOFT_SCRATCH(i), data[i]);
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POSTING_READ(SOFT_SCRATCH(i - 1));
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I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
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2016-07-06 22:30:11 +08:00
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/*
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* Fast commands should complete in less than 10us, so sample quickly
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* up to that length of time, then switch to a slower sleep-wait loop.
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* No HOST2GUC command should ever take longer than 10ms.
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*/
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ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10);
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if (ret)
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ret = wait_for(host2guc_action_response(dev_priv, &status), 10);
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2015-08-12 22:43:41 +08:00
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if (status != GUC2HOST_STATUS_SUCCESS) {
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/*
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* Either the GuC explicitly returned an error (which
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* we convert to -EIO here) or no response at all was
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* received within the timeout limit (-ETIMEDOUT)
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*/
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if (ret != -ETIMEDOUT)
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ret = -EIO;
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DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
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"status=0x%08X response=0x%08X\n",
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data[0], ret, status,
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I915_READ(SOFT_SCRATCH(15)));
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dev_priv->guc.action_fail += 1;
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dev_priv->guc.action_err = ret;
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}
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dev_priv->guc.action_status = status;
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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return ret;
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}
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/*
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* Tell the GuC to allocate or deallocate a specific doorbell
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*/
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static int host2guc_allocate_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
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data[1] = client->ctx_index;
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return host2guc_action(guc, data, 2);
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}
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static int host2guc_release_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
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data[1] = client->ctx_index;
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return host2guc_action(guc, data, 2);
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}
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2015-08-19 05:34:47 +08:00
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static int host2guc_sample_forcewake(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 data[2];
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data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
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2015-09-26 02:46:56 +08:00
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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2016-06-21 22:07:14 +08:00
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if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
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2015-09-26 02:46:56 +08:00
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data[1] = 0;
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else
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/* bit 0 and 1 are for Render and Media domain separately */
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data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
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return host2guc_action(guc, data, ARRAY_SIZE(data));
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2015-08-19 05:34:47 +08:00
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}
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2015-08-12 22:43:41 +08:00
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/*
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* Initialise, update, or clear doorbell data shared with the GuC
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*
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* These functions modify shared data and so need access to the mapped
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* client object which contains the page being used for the doorbell
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*/
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2016-06-14 00:57:32 +08:00
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static int guc_update_doorbell_id(struct intel_guc *guc,
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struct i915_guc_client *client,
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u16 new_id)
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2015-08-12 22:43:41 +08:00
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{
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2016-06-14 00:57:32 +08:00
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struct sg_table *sg = guc->ctx_pool_obj->pages;
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void *doorbell_bitmap = guc->doorbell_bitmap;
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2015-08-12 22:43:41 +08:00
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struct guc_doorbell_info *doorbell;
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2016-06-14 00:57:32 +08:00
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struct guc_context_desc desc;
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size_t len;
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2015-08-12 22:43:41 +08:00
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2016-04-19 23:08:34 +08:00
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doorbell = client->client_base + client->doorbell_offset;
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2015-08-12 22:43:41 +08:00
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2016-06-14 00:57:32 +08:00
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if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
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test_bit(client->doorbell_id, doorbell_bitmap)) {
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/* Deactivate the old doorbell */
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doorbell->db_status = GUC_DOORBELL_DISABLED;
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(void)host2guc_release_doorbell(guc, client);
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__clear_bit(client->doorbell_id, doorbell_bitmap);
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}
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/* Update the GuC's idea of the doorbell ID */
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len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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desc.db_id = new_id;
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len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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client->doorbell_id = new_id;
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if (new_id == GUC_INVALID_DOORBELL_ID)
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return 0;
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/* Activate the new doorbell */
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__set_bit(new_id, doorbell_bitmap);
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2015-08-12 22:43:41 +08:00
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doorbell->cookie = 0;
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2016-06-14 00:57:32 +08:00
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doorbell->db_status = GUC_DOORBELL_ENABLED;
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return host2guc_allocate_doorbell(guc, client);
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}
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static int guc_init_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client,
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uint16_t db_id)
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{
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return guc_update_doorbell_id(guc, client, db_id);
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2015-08-12 22:43:41 +08:00
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}
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static void guc_disable_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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2016-06-14 00:57:32 +08:00
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(void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
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2015-08-12 22:43:41 +08:00
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/* XXX: wait for any interrupts */
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/* XXX: wait for workqueue to drain */
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}
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2016-06-14 00:57:33 +08:00
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static uint16_t
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select_doorbell_register(struct intel_guc *guc, uint32_t priority)
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{
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/*
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* The bitmap tracks which doorbell registers are currently in use.
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* It is split into two halves; the first half is used for normal
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* priority contexts, the second half for high-priority ones.
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* Note that logically higher priorities are numerically less than
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* normal ones, so the test below means "is it high-priority?"
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*/
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const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
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const uint16_t half = GUC_MAX_DOORBELLS / 2;
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const uint16_t start = hi_pri ? half : 0;
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const uint16_t end = start + half;
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uint16_t id;
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id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
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if (id == end)
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id = GUC_INVALID_DOORBELL_ID;
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DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
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hi_pri ? "high" : "normal", id);
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return id;
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}
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2015-08-12 22:43:41 +08:00
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/*
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* Select, assign and relase doorbell cachelines
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*
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* These functions track which doorbell cachelines are in use.
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* The data they manipulate is protected by the host2guc lock.
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*/
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static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
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{
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const uint32_t cacheline_size = cache_line_size();
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uint32_t offset;
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/* Doorbell uses a single cache line within a page */
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offset = offset_in_page(guc->db_cacheline);
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/* Moving to next cache line to reduce contention */
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guc->db_cacheline += cacheline_size;
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DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
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offset, guc->db_cacheline, cacheline_size);
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return offset;
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}
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/*
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* Initialise the process descriptor shared with the GuC firmware.
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*/
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static void guc_init_proc_desc(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_process_desc *desc;
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2016-04-19 23:08:34 +08:00
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desc = client->client_base + client->proc_desc_offset;
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2015-08-12 22:43:41 +08:00
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memset(desc, 0, sizeof(*desc));
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/*
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* XXX: pDoorbell and WQVBaseAddress are pointers in process address
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* space for ring3 clients (set them as in mmap_ioctl) or kernel
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* space for kernel clients (map on demand instead? May make debug
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* easier to have it mapped).
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*/
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desc->wq_base_addr = 0;
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desc->db_base_addr = 0;
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desc->context_id = client->ctx_index;
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desc->wq_size_bytes = client->wq_size;
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desc->wq_status = WQ_STATUS_ACTIVE;
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desc->priority = client->priority;
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}
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/*
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* Initialise/clear the context descriptor shared with the GuC firmware.
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*
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* This descriptor tells the GuC where (in GGTT space) to find the important
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* data structures relating to this client (doorbell, process descriptor,
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* write queue, etc).
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*/
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static void guc_init_ctx_desc(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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2016-04-19 23:08:36 +08:00
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struct drm_i915_gem_object *client_obj = client->client_obj;
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2016-01-24 03:58:14 +08:00
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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2016-03-16 19:00:36 +08:00
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struct intel_engine_cs *engine;
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2016-05-24 21:53:34 +08:00
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struct i915_gem_context *ctx = client->owner;
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2015-08-12 22:43:41 +08:00
|
|
|
struct guc_context_desc desc;
|
|
|
|
struct sg_table *sg;
|
2016-04-19 23:08:36 +08:00
|
|
|
u32 gfx_addr;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
|
|
|
memset(&desc, 0, sizeof(desc));
|
|
|
|
|
|
|
|
desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
|
|
|
|
desc.context_id = client->ctx_index;
|
|
|
|
desc.priority = client->priority;
|
|
|
|
desc.db_id = client->doorbell_id;
|
|
|
|
|
2016-05-24 21:53:37 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
|
|
|
struct intel_context *ce = &ctx->engine[engine->id];
|
2016-03-16 19:00:36 +08:00
|
|
|
struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id];
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
|
|
|
|
/* TODO: We have a design issue to be solved here. Only when we
|
|
|
|
* receive the first batch, we know which engine is used by the
|
|
|
|
* user. But here GuC expects the lrc and ring to be pinned. It
|
|
|
|
* is not an issue for default context, which is the only one
|
|
|
|
* for now who owns a GuC client. But for future owner of GuC
|
|
|
|
* client, need to make sure lrc is pinned prior to enter here.
|
|
|
|
*/
|
2016-05-24 21:53:37 +08:00
|
|
|
if (!ce->state)
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
break; /* XXX: continue? */
|
|
|
|
|
2016-05-24 21:53:37 +08:00
|
|
|
lrc->context_desc = lower_32_bits(ce->lrc_desc);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
|
|
|
|
/* The state page is after PPHWSP */
|
2016-05-24 21:53:37 +08:00
|
|
|
gfx_addr = i915_gem_obj_ggtt_offset(ce->state);
|
2016-04-19 23:08:36 +08:00
|
|
|
lrc->ring_lcra = gfx_addr + LRC_STATE_PN * PAGE_SIZE;
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
|
2016-03-16 19:00:36 +08:00
|
|
|
(engine->guc_id << GUC_ELC_ENGINE_OFFSET);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
|
2016-05-24 21:53:37 +08:00
|
|
|
obj = ce->ringbuf->obj;
|
2016-04-19 23:08:36 +08:00
|
|
|
gfx_addr = i915_gem_obj_ggtt_offset(obj);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
|
2016-04-19 23:08:36 +08:00
|
|
|
lrc->ring_begin = gfx_addr;
|
|
|
|
lrc->ring_end = gfx_addr + obj->base.size - 1;
|
|
|
|
lrc->ring_next_free_location = gfx_addr;
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
lrc->ring_current_tail_pointer_value = 0;
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
desc.engines_used |= (1 << engine->guc_id);
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(desc.engines_used == 0);
|
|
|
|
|
2015-08-12 22:43:41 +08:00
|
|
|
/*
|
2016-04-19 23:08:36 +08:00
|
|
|
* The doorbell, process descriptor, and workqueue are all parts
|
|
|
|
* of the client object, which the GuC will reference via the GGTT
|
2015-08-12 22:43:41 +08:00
|
|
|
*/
|
2016-04-19 23:08:36 +08:00
|
|
|
gfx_addr = i915_gem_obj_ggtt_offset(client_obj);
|
|
|
|
desc.db_trigger_phy = sg_dma_address(client_obj->pages->sgl) +
|
|
|
|
client->doorbell_offset;
|
|
|
|
desc.db_trigger_cpu = (uintptr_t)client->client_base +
|
|
|
|
client->doorbell_offset;
|
|
|
|
desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
|
|
|
|
desc.process_desc = gfx_addr + client->proc_desc_offset;
|
|
|
|
desc.wq_addr = gfx_addr + client->wq_offset;
|
2015-08-12 22:43:41 +08:00
|
|
|
desc.wq_size = client->wq_size;
|
|
|
|
|
|
|
|
/*
|
2016-05-24 21:53:34 +08:00
|
|
|
* XXX: Take LRCs from an existing context if this is not an
|
2015-08-12 22:43:41 +08:00
|
|
|
* IsKMDCreatedContext client
|
|
|
|
*/
|
|
|
|
desc.desc_private = (uintptr_t)client;
|
|
|
|
|
|
|
|
/* Pool context is pinned already */
|
|
|
|
sg = guc->ctx_pool_obj->pages;
|
|
|
|
sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
|
|
|
|
sizeof(desc) * client->ctx_index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void guc_fini_ctx_desc(struct intel_guc *guc,
|
|
|
|
struct i915_guc_client *client)
|
|
|
|
{
|
|
|
|
struct guc_context_desc desc;
|
|
|
|
struct sg_table *sg;
|
|
|
|
|
|
|
|
memset(&desc, 0, sizeof(desc));
|
|
|
|
|
|
|
|
sg = guc->ctx_pool_obj->pages;
|
|
|
|
sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
|
|
|
|
sizeof(desc) * client->ctx_index);
|
|
|
|
}
|
|
|
|
|
2016-05-13 22:36:32 +08:00
|
|
|
/**
|
|
|
|
* i915_guc_wq_check_space() - check that the GuC can accept a request
|
|
|
|
* @request: request associated with the commands
|
|
|
|
*
|
|
|
|
* Return: 0 if space is available
|
|
|
|
* -EAGAIN if space is not currently available
|
|
|
|
*
|
|
|
|
* This function must be called (and must return 0) before a request
|
|
|
|
* is submitted to the GuC via i915_guc_submit() below. Once a result
|
|
|
|
* of 0 has been returned, it remains valid until (but only until)
|
|
|
|
* the next call to submit().
|
|
|
|
*
|
|
|
|
* This precheck allows the caller to determine in advance that space
|
|
|
|
* will be available for the next submission before committing resources
|
|
|
|
* to it, and helps avoid late failures with complicated recovery paths.
|
|
|
|
*/
|
|
|
|
int i915_guc_wq_check_space(struct drm_i915_gem_request *request)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
2016-05-13 22:36:33 +08:00
|
|
|
const size_t wqi_size = sizeof(struct guc_wq_item);
|
2016-05-13 22:36:32 +08:00
|
|
|
struct i915_guc_client *gc = request->i915->guc.execbuf_client;
|
2015-08-12 22:43:41 +08:00
|
|
|
struct guc_process_desc *desc;
|
2016-05-13 22:36:33 +08:00
|
|
|
u32 freespace;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:32 +08:00
|
|
|
GEM_BUG_ON(gc == NULL);
|
2015-12-17 03:45:55 +08:00
|
|
|
|
2016-04-19 23:08:34 +08:00
|
|
|
desc = gc->client_base + gc->proc_desc_offset;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:33 +08:00
|
|
|
freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
|
|
|
|
if (likely(freespace >= wqi_size))
|
|
|
|
return 0;
|
2015-12-03 08:56:29 +08:00
|
|
|
|
2016-05-13 22:36:33 +08:00
|
|
|
gc->no_wq_space += 1;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:33 +08:00
|
|
|
return -EAGAIN;
|
2015-08-12 22:43:41 +08:00
|
|
|
}
|
|
|
|
|
2016-05-13 22:36:34 +08:00
|
|
|
static void guc_add_workqueue_item(struct i915_guc_client *gc,
|
|
|
|
struct drm_i915_gem_request *rq)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
2016-05-13 22:36:34 +08:00
|
|
|
/* wqi_len is in DWords, and does not include the one-word header */
|
|
|
|
const size_t wqi_size = sizeof(struct guc_wq_item);
|
|
|
|
const u32 wqi_len = wqi_size/sizeof(u32) - 1;
|
2016-04-19 23:08:35 +08:00
|
|
|
struct guc_process_desc *desc;
|
2015-08-12 22:43:41 +08:00
|
|
|
struct guc_wq_item *wqi;
|
|
|
|
void *base;
|
2016-05-13 22:36:34 +08:00
|
|
|
u32 freespace, tail, wq_off, wq_page;
|
2015-12-17 03:45:55 +08:00
|
|
|
|
2016-04-19 23:08:35 +08:00
|
|
|
desc = gc->client_base + gc->proc_desc_offset;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:34 +08:00
|
|
|
/* Free space is guaranteed, see i915_guc_wq_check_space() above */
|
|
|
|
freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
|
|
|
|
GEM_BUG_ON(freespace < wqi_size);
|
|
|
|
|
|
|
|
/* The GuC firmware wants the tail index in QWords, not bytes */
|
|
|
|
tail = rq->tail;
|
|
|
|
GEM_BUG_ON(tail & 7);
|
|
|
|
tail >>= 3;
|
|
|
|
GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
|
2015-08-12 22:43:41 +08:00
|
|
|
|
|
|
|
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
|
|
|
|
* should not have the case where structure wqi is across page, neither
|
|
|
|
* wrapped to the beginning. This simplifies the implementation below.
|
|
|
|
*
|
|
|
|
* XXX: if not the case, we need save data to a temp wqi and copy it to
|
|
|
|
* workqueue buffer dw by dw.
|
|
|
|
*/
|
2016-05-13 22:36:34 +08:00
|
|
|
BUILD_BUG_ON(wqi_size != 16);
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:34 +08:00
|
|
|
/* postincrement WQ tail for next time */
|
|
|
|
wq_off = gc->wq_tail;
|
|
|
|
gc->wq_tail += wqi_size;
|
|
|
|
gc->wq_tail &= gc->wq_size - 1;
|
|
|
|
GEM_BUG_ON(wq_off & (wqi_size - 1));
|
|
|
|
|
|
|
|
/* WQ starts from the page after doorbell / process_desc */
|
|
|
|
wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT;
|
2015-08-12 22:43:41 +08:00
|
|
|
wq_off &= PAGE_SIZE - 1;
|
2016-05-13 22:36:34 +08:00
|
|
|
base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, wq_page));
|
2015-08-12 22:43:41 +08:00
|
|
|
wqi = (struct guc_wq_item *)((char *)base + wq_off);
|
|
|
|
|
2016-05-13 22:36:34 +08:00
|
|
|
/* Now fill in the 4-word work queue item */
|
2015-08-12 22:43:41 +08:00
|
|
|
wqi->header = WQ_TYPE_INORDER |
|
2016-05-13 22:36:34 +08:00
|
|
|
(wqi_len << WQ_LEN_SHIFT) |
|
2016-03-16 19:00:38 +08:00
|
|
|
(rq->engine->guc_id << WQ_TARGET_SHIFT) |
|
2015-08-12 22:43:41 +08:00
|
|
|
WQ_NO_WCFLUSH_WAIT;
|
|
|
|
|
|
|
|
/* The GuC wants only the low-order word of the context descriptor */
|
2016-03-16 19:00:38 +08:00
|
|
|
wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx,
|
|
|
|
rq->engine);
|
2015-08-12 22:43:41 +08:00
|
|
|
|
|
|
|
wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
|
2016-05-13 22:36:34 +08:00
|
|
|
wqi->fence_id = rq->seqno;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
|
|
|
kunmap_atomic(base);
|
|
|
|
}
|
|
|
|
|
2016-06-14 00:57:31 +08:00
|
|
|
static int guc_ring_doorbell(struct i915_guc_client *gc)
|
|
|
|
{
|
|
|
|
struct guc_process_desc *desc;
|
|
|
|
union guc_doorbell_qw db_cmp, db_exc, db_ret;
|
|
|
|
union guc_doorbell_qw *db;
|
|
|
|
int attempt = 2, ret = -EAGAIN;
|
|
|
|
|
|
|
|
desc = gc->client_base + gc->proc_desc_offset;
|
|
|
|
|
|
|
|
/* Update the tail so it is visible to GuC */
|
|
|
|
desc->tail = gc->wq_tail;
|
|
|
|
|
|
|
|
/* current cookie */
|
|
|
|
db_cmp.db_status = GUC_DOORBELL_ENABLED;
|
|
|
|
db_cmp.cookie = gc->cookie;
|
|
|
|
|
|
|
|
/* cookie to be updated */
|
|
|
|
db_exc.db_status = GUC_DOORBELL_ENABLED;
|
|
|
|
db_exc.cookie = gc->cookie + 1;
|
|
|
|
if (db_exc.cookie == 0)
|
|
|
|
db_exc.cookie = 1;
|
|
|
|
|
|
|
|
/* pointer of current doorbell cacheline */
|
|
|
|
db = gc->client_base + gc->doorbell_offset;
|
|
|
|
|
|
|
|
while (attempt--) {
|
|
|
|
/* lets ring the doorbell */
|
|
|
|
db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
|
|
|
|
db_cmp.value_qw, db_exc.value_qw);
|
|
|
|
|
|
|
|
/* if the exchange was successfully executed */
|
|
|
|
if (db_ret.value_qw == db_cmp.value_qw) {
|
|
|
|
/* db was successfully rung */
|
|
|
|
gc->cookie = db_exc.cookie;
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: doorbell was lost and need to acquire it again */
|
|
|
|
if (db_ret.db_status == GUC_DOORBELL_DISABLED)
|
|
|
|
break;
|
|
|
|
|
|
|
|
DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
|
|
|
|
db_cmp.cookie, db_ret.cookie);
|
|
|
|
|
|
|
|
/* update the cookie to newly read cookie from GuC */
|
|
|
|
db_cmp.cookie = db_ret.cookie;
|
|
|
|
db_exc.cookie = db_ret.cookie + 1;
|
|
|
|
if (db_exc.cookie == 0)
|
|
|
|
db_exc.cookie = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:41 +08:00
|
|
|
/**
|
|
|
|
* i915_guc_submit() - Submit commands through GuC
|
2015-10-20 07:10:54 +08:00
|
|
|
* @rq: request associated with the commands
|
2015-08-12 22:43:41 +08:00
|
|
|
*
|
2016-05-13 22:36:32 +08:00
|
|
|
* Return: 0 on success, otherwise an errno.
|
|
|
|
* (Note: nonzero really shouldn't happen!)
|
|
|
|
*
|
|
|
|
* The caller must have already called i915_guc_wq_check_space() above
|
|
|
|
* with a result of 0 (success) since the last request submission. This
|
|
|
|
* guarantees that there is space in the work queue for the new request,
|
|
|
|
* so enqueuing the item cannot fail.
|
|
|
|
*
|
|
|
|
* Bad Things Will Happen if the caller violates this protocol e.g. calls
|
|
|
|
* submit() when check() says there's no space, or calls submit() multiple
|
|
|
|
* times with no intervening check().
|
|
|
|
*
|
|
|
|
* The only error here arises if the doorbell hardware isn't functioning
|
|
|
|
* as expected, which really shouln't happen.
|
2015-08-12 22:43:41 +08:00
|
|
|
*/
|
2016-05-13 22:36:32 +08:00
|
|
|
int i915_guc_submit(struct drm_i915_gem_request *rq)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
2016-06-20 22:18:07 +08:00
|
|
|
unsigned int engine_id = rq->engine->id;
|
2016-05-13 22:36:32 +08:00
|
|
|
struct intel_guc *guc = &rq->i915->guc;
|
|
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
2016-05-13 22:36:34 +08:00
|
|
|
int b_ret;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:34 +08:00
|
|
|
guc_add_workqueue_item(client, rq);
|
|
|
|
b_ret = guc_ring_doorbell(client);
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-01-24 03:58:14 +08:00
|
|
|
client->submissions[engine_id] += 1;
|
2016-05-13 22:36:34 +08:00
|
|
|
client->retcode = b_ret;
|
|
|
|
if (b_ret)
|
2015-08-12 22:43:41 +08:00
|
|
|
client->b_fail += 1;
|
2016-05-13 22:36:34 +08:00
|
|
|
|
2016-01-24 03:58:14 +08:00
|
|
|
guc->submissions[engine_id] += 1;
|
|
|
|
guc->last_seqno[engine_id] = rq->seqno;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
2016-05-13 22:36:34 +08:00
|
|
|
return b_ret;
|
2015-08-12 22:43:41 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Everything below here is concerned with setup & teardown, and is
|
|
|
|
* therefore not part of the somewhat time-critical batch-submission
|
|
|
|
* path of i915_guc_submit() above.
|
|
|
|
*/
|
|
|
|
|
2015-08-12 22:43:39 +08:00
|
|
|
/**
|
|
|
|
* gem_allocate_guc_obj() - Allocate gem object for GuC usage
|
2016-06-11 01:29:25 +08:00
|
|
|
* @dev_priv: driver private data structure
|
2015-08-12 22:43:39 +08:00
|
|
|
* @size: size of object
|
|
|
|
*
|
|
|
|
* This is a wrapper to create a gem obj. In order to use it inside GuC, the
|
|
|
|
* object needs to be pinned lifetime. Also we must pin it to gtt space other
|
|
|
|
* than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
|
|
|
|
*
|
|
|
|
* Return: A drm_i915_gem_object if successful, otherwise NULL.
|
|
|
|
*/
|
2016-06-11 01:29:25 +08:00
|
|
|
static struct drm_i915_gem_object *
|
|
|
|
gem_allocate_guc_obj(struct drm_i915_private *dev_priv, u32 size)
|
2015-08-12 22:43:39 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
|
2016-07-05 17:40:23 +08:00
|
|
|
obj = i915_gem_object_create(&dev_priv->drm, size);
|
2016-04-25 20:32:13 +08:00
|
|
|
if (IS_ERR(obj))
|
2015-08-12 22:43:39 +08:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (i915_gem_object_get_pages(obj)) {
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
|
|
|
|
PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) {
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
|
|
|
|
I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
|
|
|
|
|
|
|
|
return obj;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* gem_release_guc_obj() - Release gem object allocated for GuC usage
|
|
|
|
* @obj: gem obj to be released
|
2015-11-25 22:21:30 +08:00
|
|
|
*/
|
2015-08-12 22:43:39 +08:00
|
|
|
static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
|
|
|
|
{
|
|
|
|
if (!obj)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (i915_gem_obj_is_pinned(obj))
|
|
|
|
i915_gem_object_ggtt_unpin(obj);
|
|
|
|
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
}
|
|
|
|
|
2016-06-11 01:29:25 +08:00
|
|
|
static void
|
|
|
|
guc_client_free(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_guc_client *client)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
|
|
|
|
if (!client)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX: wait for any outstanding submissions before freeing memory.
|
|
|
|
* Be sure to drop any locks
|
|
|
|
*/
|
|
|
|
|
2016-04-19 23:08:34 +08:00
|
|
|
if (client->client_base) {
|
|
|
|
/*
|
2016-06-14 00:57:32 +08:00
|
|
|
* If we got as far as setting up a doorbell, make sure we
|
|
|
|
* shut it down before unmapping & deallocating the memory.
|
2016-04-19 23:08:34 +08:00
|
|
|
*/
|
2016-06-14 00:57:32 +08:00
|
|
|
guc_disable_doorbell(guc, client);
|
2016-04-19 23:08:34 +08:00
|
|
|
|
|
|
|
kunmap(kmap_to_page(client->client_base));
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:41 +08:00
|
|
|
gem_release_guc_obj(client->client_obj);
|
|
|
|
|
|
|
|
if (client->ctx_index != GUC_INVALID_CTX_ID) {
|
|
|
|
guc_fini_ctx_desc(guc, client);
|
|
|
|
ida_simple_remove(&guc->ctx_ids, client->ctx_index);
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(client);
|
|
|
|
}
|
|
|
|
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-14 00:57:34 +08:00
|
|
|
/*
|
|
|
|
* Borrow the first client to set up & tear down every doorbell
|
|
|
|
* in turn, to ensure that all doorbell h/w is (re)initialised.
|
|
|
|
*/
|
|
|
|
static void guc_init_doorbell_hw(struct intel_guc *guc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
|
|
struct i915_guc_client *client = guc->execbuf_client;
|
|
|
|
uint16_t db_id, i;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
db_id = client->doorbell_id;
|
|
|
|
|
|
|
|
for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
|
|
|
|
i915_reg_t drbreg = GEN8_DRBREGL(i);
|
|
|
|
u32 value = I915_READ(drbreg);
|
|
|
|
|
|
|
|
err = guc_update_doorbell_id(guc, client, i);
|
|
|
|
|
|
|
|
/* Report update failure or unexpectedly active doorbell */
|
|
|
|
if (err || (i != db_id && (value & GUC_DOORBELL_ENABLED)))
|
|
|
|
DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) was 0x%x, err %d\n",
|
|
|
|
i, drbreg.reg, value, err);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Restore to original value */
|
|
|
|
err = guc_update_doorbell_id(guc, client, db_id);
|
|
|
|
if (err)
|
|
|
|
DRM_ERROR("Failed to restore doorbell to %d, err %d\n",
|
|
|
|
db_id, err);
|
|
|
|
|
|
|
|
for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
|
|
|
|
i915_reg_t drbreg = GEN8_DRBREGL(i);
|
|
|
|
u32 value = I915_READ(drbreg);
|
|
|
|
|
|
|
|
if (i != db_id && (value & GUC_DOORBELL_ENABLED))
|
|
|
|
DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) finally 0x%x\n",
|
|
|
|
i, drbreg.reg, value);
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:41 +08:00
|
|
|
/**
|
|
|
|
* guc_client_alloc() - Allocate an i915_guc_client
|
2016-06-11 01:29:25 +08:00
|
|
|
* @dev_priv: driver private data structure
|
2015-08-12 22:43:41 +08:00
|
|
|
* @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
|
|
|
|
* The kernel client to replace ExecList submission is created with
|
|
|
|
* NORMAL priority. Priority of a client for scheduler can be HIGH,
|
|
|
|
* while a preemption context can use CRITICAL.
|
2015-10-20 07:10:54 +08:00
|
|
|
* @ctx: the context that owns the client (we use the default render
|
|
|
|
* context)
|
2015-08-12 22:43:41 +08:00
|
|
|
*
|
2016-04-19 23:08:34 +08:00
|
|
|
* Return: An i915_guc_client object if success, else NULL.
|
2015-08-12 22:43:41 +08:00
|
|
|
*/
|
2016-06-11 01:29:25 +08:00
|
|
|
static struct i915_guc_client *
|
|
|
|
guc_client_alloc(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t priority,
|
|
|
|
struct i915_gem_context *ctx)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
|
|
|
struct i915_guc_client *client;
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
struct drm_i915_gem_object *obj;
|
2016-06-14 00:57:32 +08:00
|
|
|
uint16_t db_id;
|
2015-08-12 22:43:41 +08:00
|
|
|
|
|
|
|
client = kzalloc(sizeof(*client), GFP_KERNEL);
|
|
|
|
if (!client)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
client->doorbell_id = GUC_INVALID_DOORBELL_ID;
|
|
|
|
client->priority = priority;
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
client->owner = ctx;
|
2015-08-12 22:43:41 +08:00
|
|
|
client->guc = guc;
|
|
|
|
|
|
|
|
client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
|
|
|
|
GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
|
|
|
|
if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
|
|
|
|
client->ctx_index = GUC_INVALID_CTX_ID;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The first page is doorbell/proc_desc. Two followed pages are wq. */
|
2016-06-11 01:29:25 +08:00
|
|
|
obj = gem_allocate_guc_obj(dev_priv, GUC_DB_SIZE + GUC_WQ_SIZE);
|
2015-08-12 22:43:41 +08:00
|
|
|
if (!obj)
|
|
|
|
goto err;
|
|
|
|
|
2016-04-19 23:08:34 +08:00
|
|
|
/* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
|
2015-08-12 22:43:41 +08:00
|
|
|
client->client_obj = obj;
|
2016-04-19 23:08:34 +08:00
|
|
|
client->client_base = kmap(i915_gem_object_get_page(obj, 0));
|
2015-08-12 22:43:41 +08:00
|
|
|
client->wq_offset = GUC_DB_SIZE;
|
|
|
|
client->wq_size = GUC_WQ_SIZE;
|
|
|
|
|
2016-06-14 00:57:33 +08:00
|
|
|
db_id = select_doorbell_register(guc, client->priority);
|
|
|
|
if (db_id == GUC_INVALID_DOORBELL_ID)
|
|
|
|
/* XXX: evict a doorbell instead? */
|
|
|
|
goto err;
|
|
|
|
|
2015-08-12 22:43:41 +08:00
|
|
|
client->doorbell_offset = select_doorbell_cacheline(guc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Since the doorbell only requires a single cacheline, we can save
|
|
|
|
* space by putting the application process descriptor in the same
|
|
|
|
* page. Use the half of the page that doesn't include the doorbell.
|
|
|
|
*/
|
|
|
|
if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
|
|
|
|
client->proc_desc_offset = 0;
|
|
|
|
else
|
|
|
|
client->proc_desc_offset = (GUC_DB_SIZE / 2);
|
|
|
|
|
|
|
|
guc_init_proc_desc(guc, client);
|
|
|
|
guc_init_ctx_desc(guc, client);
|
2016-06-14 00:57:32 +08:00
|
|
|
if (guc_init_doorbell(guc, client, db_id))
|
2015-08-12 22:43:41 +08:00
|
|
|
goto err;
|
|
|
|
|
2016-06-14 00:57:32 +08:00
|
|
|
DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u\n",
|
|
|
|
priority, client, client->ctx_index);
|
|
|
|
DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
|
|
|
|
client->doorbell_id, client->doorbell_offset);
|
2015-08-12 22:43:41 +08:00
|
|
|
|
|
|
|
return client;
|
|
|
|
|
|
|
|
err:
|
|
|
|
DRM_ERROR("FAILED to create priority %u GuC client!\n", priority);
|
|
|
|
|
2016-06-11 01:29:25 +08:00
|
|
|
guc_client_free(dev_priv, client);
|
2015-08-12 22:43:41 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:40 +08:00
|
|
|
static void guc_create_log(struct intel_guc *guc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
unsigned long offset;
|
|
|
|
uint32_t size, flags;
|
|
|
|
|
|
|
|
if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
|
|
|
|
i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
|
|
|
|
|
|
|
|
/* The first page is to save log buffer state. Allocate one
|
|
|
|
* extra page for others in case for overlap */
|
|
|
|
size = (1 + GUC_LOG_DPC_PAGES + 1 +
|
|
|
|
GUC_LOG_ISR_PAGES + 1 +
|
|
|
|
GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
|
|
|
|
|
|
|
|
obj = guc->log_obj;
|
|
|
|
if (!obj) {
|
2016-06-11 01:29:25 +08:00
|
|
|
obj = gem_allocate_guc_obj(dev_priv, size);
|
2015-08-12 22:43:40 +08:00
|
|
|
if (!obj) {
|
|
|
|
/* logging will be off */
|
|
|
|
i915.guc_log_level = -1;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
guc->log_obj = obj;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* each allocated unit is a page */
|
|
|
|
flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
|
|
|
|
(GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
|
|
|
|
(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
|
|
|
|
(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
|
|
|
|
|
|
|
|
offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */
|
|
|
|
guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
|
|
|
|
}
|
|
|
|
|
2015-12-19 04:00:10 +08:00
|
|
|
static void init_guc_policies(struct guc_policies *policies)
|
|
|
|
{
|
|
|
|
struct guc_policy *policy;
|
|
|
|
u32 p, i;
|
|
|
|
|
|
|
|
policies->dpc_promote_time = 500000;
|
|
|
|
policies->max_num_work_items = POLICY_MAX_NUM_WI;
|
|
|
|
|
|
|
|
for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
|
2016-01-24 03:58:14 +08:00
|
|
|
for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
|
2015-12-19 04:00:10 +08:00
|
|
|
policy = &policies->policy[p][i];
|
|
|
|
|
|
|
|
policy->execution_quantum = 1000000;
|
|
|
|
policy->preemption_time = 500000;
|
|
|
|
policy->fault_time = 250000;
|
|
|
|
policy->policy_flags = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
policies->is_valid = 1;
|
|
|
|
}
|
|
|
|
|
2015-12-19 04:00:09 +08:00
|
|
|
static void guc_create_ads(struct intel_guc *guc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct guc_ads *ads;
|
2015-12-19 04:00:10 +08:00
|
|
|
struct guc_policies *policies;
|
2015-12-19 04:00:11 +08:00
|
|
|
struct guc_mmio_reg_state *reg_state;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2015-12-19 04:00:09 +08:00
|
|
|
struct page *page;
|
2016-03-24 19:20:38 +08:00
|
|
|
u32 size;
|
2015-12-19 04:00:09 +08:00
|
|
|
|
|
|
|
/* The ads obj includes the struct itself and buffers passed to GuC */
|
2015-12-19 04:00:11 +08:00
|
|
|
size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
|
|
|
|
sizeof(struct guc_mmio_reg_state) +
|
|
|
|
GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
|
2015-12-19 04:00:09 +08:00
|
|
|
|
|
|
|
obj = guc->ads_obj;
|
|
|
|
if (!obj) {
|
2016-06-11 01:29:25 +08:00
|
|
|
obj = gem_allocate_guc_obj(dev_priv, PAGE_ALIGN(size));
|
2015-12-19 04:00:09 +08:00
|
|
|
if (!obj)
|
|
|
|
return;
|
|
|
|
|
|
|
|
guc->ads_obj = obj;
|
|
|
|
}
|
|
|
|
|
|
|
|
page = i915_gem_object_get_page(obj, 0);
|
|
|
|
ads = kmap(page);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The GuC requires a "Golden Context" when it reinitialises
|
|
|
|
* engines after a reset. Here we use the Render ring default
|
|
|
|
* context, which must already exist and be pinned in the GGTT,
|
|
|
|
* so its address won't change after we've told the GuC where
|
|
|
|
* to find it.
|
|
|
|
*/
|
2016-03-16 19:00:38 +08:00
|
|
|
engine = &dev_priv->engine[RCS];
|
2016-03-16 19:00:36 +08:00
|
|
|
ads->golden_context_lrca = engine->status_page.gfx_addr;
|
2015-12-19 04:00:09 +08:00
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv)
|
2016-03-16 19:00:36 +08:00
|
|
|
ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
|
2015-12-19 04:00:09 +08:00
|
|
|
|
2015-12-19 04:00:10 +08:00
|
|
|
/* GuC scheduling policies */
|
|
|
|
policies = (void *)ads + sizeof(struct guc_ads);
|
|
|
|
init_guc_policies(policies);
|
|
|
|
|
|
|
|
ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) +
|
|
|
|
sizeof(struct guc_ads);
|
|
|
|
|
2015-12-19 04:00:11 +08:00
|
|
|
/* MMIO reg state */
|
|
|
|
reg_state = (void *)policies + sizeof(struct guc_policies);
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2016-03-16 19:00:36 +08:00
|
|
|
reg_state->mmio_white_list[engine->guc_id].mmio_start =
|
|
|
|
engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
|
2015-12-19 04:00:11 +08:00
|
|
|
|
|
|
|
/* Nothing to be saved or restored for now. */
|
2016-03-16 19:00:36 +08:00
|
|
|
reg_state->mmio_white_list[engine->guc_id].count = 0;
|
2015-12-19 04:00:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
ads->reg_state_addr = ads->scheduler_policies +
|
|
|
|
sizeof(struct guc_policies);
|
|
|
|
|
|
|
|
ads->reg_state_buffer = ads->reg_state_addr +
|
|
|
|
sizeof(struct guc_mmio_reg_state);
|
|
|
|
|
2015-12-19 04:00:09 +08:00
|
|
|
kunmap(page);
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:39 +08:00
|
|
|
/*
|
|
|
|
* Set up the memory resources to be shared with the GuC. At this point,
|
|
|
|
* we require just one object that can be mapped through the GGTT.
|
|
|
|
*/
|
2016-06-11 01:29:26 +08:00
|
|
|
int i915_guc_submission_init(struct drm_i915_private *dev_priv)
|
2015-08-12 22:43:39 +08:00
|
|
|
{
|
|
|
|
const size_t ctxsize = sizeof(struct guc_context_desc);
|
|
|
|
const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
|
|
|
|
const size_t gemsize = round_up(poolsize, PAGE_SIZE);
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
|
drm/i915/guc: disable GuC submission earlier during GuC (re)load
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
internal detail of the submission code. So here we remove the call from
the loader (which is too late, really, because the GuC has already been
reloaded at this point) and put it into guc_submission_init() instead.
This means that any preexisting client is destroyed *before* the GuC
(re)load and then recreated after, iff the firmware was successfully
loaded. If the GuC reload fails, we don't recreate the client, so
fallback to execlists mode (if active) won't leak the client object
(previously, the now-unusable client would have been left allocated,
and leaked if the driver were unloaded).
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-06-07 16:14:50 +08:00
|
|
|
/* Wipe bitmap & delete client in case of reinitialisation */
|
|
|
|
bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
|
2016-06-11 01:29:26 +08:00
|
|
|
i915_guc_submission_disable(dev_priv);
|
drm/i915/guc: disable GuC submission earlier during GuC (re)load
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
internal detail of the submission code. So here we remove the call from
the loader (which is too late, really, because the GuC has already been
reloaded at this point) and put it into guc_submission_init() instead.
This means that any preexisting client is destroyed *before* the GuC
(re)load and then recreated after, iff the firmware was successfully
loaded. If the GuC reload fails, we don't recreate the client, so
fallback to execlists mode (if active) won't leak the client object
(previously, the now-unusable client would have been left allocated,
and leaked if the driver were unloaded).
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-06-07 16:14:50 +08:00
|
|
|
|
2015-08-12 22:43:39 +08:00
|
|
|
if (!i915.enable_guc_submission)
|
|
|
|
return 0; /* not enabled */
|
|
|
|
|
|
|
|
if (guc->ctx_pool_obj)
|
|
|
|
return 0; /* already allocated */
|
|
|
|
|
2016-06-11 01:29:25 +08:00
|
|
|
guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv, gemsize);
|
2015-08-12 22:43:39 +08:00
|
|
|
if (!guc->ctx_pool_obj)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ida_init(&guc->ctx_ids);
|
2015-08-12 22:43:40 +08:00
|
|
|
guc_create_log(guc);
|
2015-12-19 04:00:09 +08:00
|
|
|
guc_create_ads(guc);
|
|
|
|
|
2015-08-12 22:43:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-11 01:29:26 +08:00
|
|
|
int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
struct i915_guc_client *client;
|
|
|
|
|
|
|
|
/* client for execbuf submission */
|
2016-06-11 01:29:25 +08:00
|
|
|
client = guc_client_alloc(dev_priv,
|
2016-05-24 21:53:40 +08:00
|
|
|
GUC_CTX_PRIORITY_KMD_NORMAL,
|
|
|
|
dev_priv->kernel_context);
|
2015-08-12 22:43:41 +08:00
|
|
|
if (!client) {
|
|
|
|
DRM_ERROR("Failed to create execbuf guc_client\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
guc->execbuf_client = client;
|
2015-08-19 05:34:47 +08:00
|
|
|
host2guc_sample_forcewake(guc, client);
|
drm/i915/guc: (re)initialise doorbell h/w when enabling GuC submission
During a hibernate/resume cycle, the whole system is reset, including
the GuC and the doorbell hardware. Then the system is booted up, drivers
are loaded, etc -- the GuC firmware may be loaded and set running at
this point. But then, the booted kernel is replaced by the hibernated
image, and this resumed kernel will also try to reload the GuC firmware
(which will fail). To recover, we reset the GuC and try again (which
should work). But this GuC reset doesn't also reset the doorbell
hardware, so it can be left in a state inconsistent with that assumed
by the driver and/or the newly-loaded GuC firmware.
It would be better if the GuC reset also cleared all doorbell state,
but that's not how the hardware currently works; also, the driver cannot
directly reprogram the doorbell hardware (only the GuC can do that).
So this patch cycles through all doorbells, assigning and releasing each
in turn, so that all the doorbell hardware is left in a consistent
state, no matter how it was programmed by the previously-running kernel
and/or GuC firmware.
v2: don't use kmap_atomic() now that client page 0 is kept mapped.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465837054-16245-2-git-send-email-david.s.gordon@intel.com
2016-06-14 00:57:34 +08:00
|
|
|
guc_init_doorbell_hw(guc);
|
2015-08-19 05:34:47 +08:00
|
|
|
|
2015-08-12 22:43:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-11 01:29:26 +08:00
|
|
|
void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
|
2015-08-12 22:43:41 +08:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
|
2016-06-11 01:29:25 +08:00
|
|
|
guc_client_free(dev_priv, guc->execbuf_client);
|
2015-08-12 22:43:41 +08:00
|
|
|
guc->execbuf_client = NULL;
|
|
|
|
}
|
|
|
|
|
2016-06-11 01:29:26 +08:00
|
|
|
void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
|
2015-08-12 22:43:39 +08:00
|
|
|
{
|
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
|
2015-12-19 04:00:09 +08:00
|
|
|
gem_release_guc_obj(dev_priv->guc.ads_obj);
|
|
|
|
guc->ads_obj = NULL;
|
|
|
|
|
2015-08-12 22:43:40 +08:00
|
|
|
gem_release_guc_obj(dev_priv->guc.log_obj);
|
|
|
|
guc->log_obj = NULL;
|
|
|
|
|
2015-08-12 22:43:39 +08:00
|
|
|
if (guc->ctx_pool_obj)
|
|
|
|
ida_destroy(&guc->ctx_ids);
|
|
|
|
gem_release_guc_obj(guc->ctx_pool_obj);
|
|
|
|
guc->ctx_pool_obj = NULL;
|
|
|
|
}
|
2015-10-01 00:46:37 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_guc_suspend() - notify GuC entering suspend state
|
|
|
|
* @dev: drm device
|
|
|
|
*/
|
|
|
|
int intel_guc_suspend(struct drm_device *dev)
|
|
|
|
{
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-10-01 00:46:37 +08:00
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-05-24 21:53:34 +08:00
|
|
|
struct i915_gem_context *ctx;
|
2015-10-01 00:46:37 +08:00
|
|
|
u32 data[3];
|
|
|
|
|
2016-05-20 18:42:42 +08:00
|
|
|
if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
|
2015-10-01 00:46:37 +08:00
|
|
|
return 0;
|
|
|
|
|
2016-01-20 03:02:54 +08:00
|
|
|
ctx = dev_priv->kernel_context;
|
2015-10-01 00:46:37 +08:00
|
|
|
|
|
|
|
data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
|
|
|
|
/* any value greater than GUC_POWER_D0 */
|
|
|
|
data[1] = GUC_POWER_D1;
|
|
|
|
/* first page is shared data with GuC */
|
|
|
|
data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
|
|
|
|
|
|
|
|
return host2guc_action(guc, data, ARRAY_SIZE(data));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_guc_resume() - notify GuC resuming from suspend state
|
|
|
|
* @dev: drm device
|
|
|
|
*/
|
|
|
|
int intel_guc_resume(struct drm_device *dev)
|
|
|
|
{
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-10-01 00:46:37 +08:00
|
|
|
struct intel_guc *guc = &dev_priv->guc;
|
2016-05-24 21:53:34 +08:00
|
|
|
struct i915_gem_context *ctx;
|
2015-10-01 00:46:37 +08:00
|
|
|
u32 data[3];
|
|
|
|
|
2016-05-20 18:42:42 +08:00
|
|
|
if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
|
2015-10-01 00:46:37 +08:00
|
|
|
return 0;
|
|
|
|
|
2016-01-20 03:02:54 +08:00
|
|
|
ctx = dev_priv->kernel_context;
|
2015-10-01 00:46:37 +08:00
|
|
|
|
|
|
|
data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
|
|
|
|
data[1] = GUC_POWER_D0;
|
|
|
|
/* first page is shared data with GuC */
|
|
|
|
data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
|
|
|
|
|
|
|
|
return host2guc_action(guc, data, ARRAY_SIZE(data));
|
|
|
|
}
|