crypto: x86/aria - implement aria-avx2
aria-avx2 implementation uses AVX2, AES-NI, and GFNI.
It supports 32way parallel processing.
So, byteslicing code is changed to support 32way parallel.
And it exports some aria-avx functions such as encrypt() and decrypt().
There are two main logics, s-box layer and diffusion layer.
These codes are the same as aria-avx implementation.
But some instruction are exchanged because they don't support 256bit
registers.
Also, AES-NI doesn't support 256bit register.
So, aesenclast and aesdeclast are used twice like below:
vextracti128 $1, ymm0, xmm6;
vaesenclast xmm7, xmm0, xmm0;
vaesenclast xmm7, xmm6, xmm6;
vinserti128 $1, xmm6, ymm0, ymm0;
Benchmark with modprobe tcrypt mode=610 num_mb=8192, i3-12100:
ARIA-AVX2 with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) encryption
tcrypt: 1 operation in 2003 cycles (1024 bytes)
tcrypt: 1 operation in 5867 cycles (4096 bytes)
tcrypt: 1 operation in 2358 cycles (1024 bytes)
tcrypt: 1 operation in 7295 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) decryption
tcrypt: 1 operation in 2004 cycles (1024 bytes)
tcrypt: 1 operation in 5956 cycles (4096 bytes)
tcrypt: 1 operation in 2409 cycles (1024 bytes)
tcrypt: 1 operation in 7564 cycles (4096 bytes)
ARIA-AVX with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) encryption
tcrypt: 1 operation in 2761 cycles (1024 bytes)
tcrypt: 1 operation in 9390 cycles (4096 bytes)
tcrypt: 1 operation in 3401 cycles (1024 bytes)
tcrypt: 1 operation in 11876 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) decryption
tcrypt: 1 operation in 2735 cycles (1024 bytes)
tcrypt: 1 operation in 9424 cycles (4096 bytes)
tcrypt: 1 operation in 3369 cycles (1024 bytes)
tcrypt: 1 operation in 11954 cycles (4096 bytes)
Signed-off-by: Taehee Yoo <ap420073@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-01-01 17:12:51 +08:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Glue Code for the AVX2/AES-NI/GFNI assembler implementation of the ARIA Cipher
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*
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* Copyright (c) 2022 Taehee Yoo <ap420073@gmail.com>
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*/
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#include <crypto/algapi.h>
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#include <crypto/internal/simd.h>
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#include <crypto/aria.h>
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#include <linux/crypto.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include "ecb_cbc_helpers.h"
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#include "aria-avx.h"
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asmlinkage void aria_aesni_avx2_encrypt_32way(const void *ctx, u8 *dst,
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const u8 *src);
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EXPORT_SYMBOL_GPL(aria_aesni_avx2_encrypt_32way);
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asmlinkage void aria_aesni_avx2_decrypt_32way(const void *ctx, u8 *dst,
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const u8 *src);
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EXPORT_SYMBOL_GPL(aria_aesni_avx2_decrypt_32way);
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asmlinkage void aria_aesni_avx2_ctr_crypt_32way(const void *ctx, u8 *dst,
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const u8 *src,
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u8 *keystream, u8 *iv);
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EXPORT_SYMBOL_GPL(aria_aesni_avx2_ctr_crypt_32way);
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2023-01-15 20:15:35 +08:00
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#ifdef CONFIG_AS_GFNI
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crypto: x86/aria - implement aria-avx2
aria-avx2 implementation uses AVX2, AES-NI, and GFNI.
It supports 32way parallel processing.
So, byteslicing code is changed to support 32way parallel.
And it exports some aria-avx functions such as encrypt() and decrypt().
There are two main logics, s-box layer and diffusion layer.
These codes are the same as aria-avx implementation.
But some instruction are exchanged because they don't support 256bit
registers.
Also, AES-NI doesn't support 256bit register.
So, aesenclast and aesdeclast are used twice like below:
vextracti128 $1, ymm0, xmm6;
vaesenclast xmm7, xmm0, xmm0;
vaesenclast xmm7, xmm6, xmm6;
vinserti128 $1, xmm6, ymm0, ymm0;
Benchmark with modprobe tcrypt mode=610 num_mb=8192, i3-12100:
ARIA-AVX2 with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) encryption
tcrypt: 1 operation in 2003 cycles (1024 bytes)
tcrypt: 1 operation in 5867 cycles (4096 bytes)
tcrypt: 1 operation in 2358 cycles (1024 bytes)
tcrypt: 1 operation in 7295 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) decryption
tcrypt: 1 operation in 2004 cycles (1024 bytes)
tcrypt: 1 operation in 5956 cycles (4096 bytes)
tcrypt: 1 operation in 2409 cycles (1024 bytes)
tcrypt: 1 operation in 7564 cycles (4096 bytes)
ARIA-AVX with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) encryption
tcrypt: 1 operation in 2761 cycles (1024 bytes)
tcrypt: 1 operation in 9390 cycles (4096 bytes)
tcrypt: 1 operation in 3401 cycles (1024 bytes)
tcrypt: 1 operation in 11876 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) decryption
tcrypt: 1 operation in 2735 cycles (1024 bytes)
tcrypt: 1 operation in 9424 cycles (4096 bytes)
tcrypt: 1 operation in 3369 cycles (1024 bytes)
tcrypt: 1 operation in 11954 cycles (4096 bytes)
Signed-off-by: Taehee Yoo <ap420073@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-01-01 17:12:51 +08:00
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asmlinkage void aria_aesni_avx2_gfni_encrypt_32way(const void *ctx, u8 *dst,
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const u8 *src);
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EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_encrypt_32way);
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asmlinkage void aria_aesni_avx2_gfni_decrypt_32way(const void *ctx, u8 *dst,
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const u8 *src);
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EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_decrypt_32way);
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asmlinkage void aria_aesni_avx2_gfni_ctr_crypt_32way(const void *ctx, u8 *dst,
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const u8 *src,
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u8 *keystream, u8 *iv);
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EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_ctr_crypt_32way);
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2023-01-15 20:15:35 +08:00
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#endif /* CONFIG_AS_GFNI */
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crypto: x86/aria - implement aria-avx2
aria-avx2 implementation uses AVX2, AES-NI, and GFNI.
It supports 32way parallel processing.
So, byteslicing code is changed to support 32way parallel.
And it exports some aria-avx functions such as encrypt() and decrypt().
There are two main logics, s-box layer and diffusion layer.
These codes are the same as aria-avx implementation.
But some instruction are exchanged because they don't support 256bit
registers.
Also, AES-NI doesn't support 256bit register.
So, aesenclast and aesdeclast are used twice like below:
vextracti128 $1, ymm0, xmm6;
vaesenclast xmm7, xmm0, xmm0;
vaesenclast xmm7, xmm6, xmm6;
vinserti128 $1, xmm6, ymm0, ymm0;
Benchmark with modprobe tcrypt mode=610 num_mb=8192, i3-12100:
ARIA-AVX2 with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) encryption
tcrypt: 1 operation in 2003 cycles (1024 bytes)
tcrypt: 1 operation in 5867 cycles (4096 bytes)
tcrypt: 1 operation in 2358 cycles (1024 bytes)
tcrypt: 1 operation in 7295 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) decryption
tcrypt: 1 operation in 2004 cycles (1024 bytes)
tcrypt: 1 operation in 5956 cycles (4096 bytes)
tcrypt: 1 operation in 2409 cycles (1024 bytes)
tcrypt: 1 operation in 7564 cycles (4096 bytes)
ARIA-AVX with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) encryption
tcrypt: 1 operation in 2761 cycles (1024 bytes)
tcrypt: 1 operation in 9390 cycles (4096 bytes)
tcrypt: 1 operation in 3401 cycles (1024 bytes)
tcrypt: 1 operation in 11876 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) decryption
tcrypt: 1 operation in 2735 cycles (1024 bytes)
tcrypt: 1 operation in 9424 cycles (4096 bytes)
tcrypt: 1 operation in 3369 cycles (1024 bytes)
tcrypt: 1 operation in 11954 cycles (4096 bytes)
Signed-off-by: Taehee Yoo <ap420073@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-01-01 17:12:51 +08:00
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static struct aria_avx_ops aria_ops;
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struct aria_avx2_request_ctx {
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u8 keystream[ARIA_AESNI_AVX2_PARALLEL_BLOCK_SIZE];
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};
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static int ecb_do_encrypt(struct skcipher_request *req, const u32 *rkey)
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{
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ECB_WALK_START(req, ARIA_BLOCK_SIZE, ARIA_AESNI_PARALLEL_BLOCKS);
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ECB_BLOCK(ARIA_AESNI_AVX2_PARALLEL_BLOCKS, aria_ops.aria_encrypt_32way);
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ECB_BLOCK(ARIA_AESNI_PARALLEL_BLOCKS, aria_ops.aria_encrypt_16way);
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ECB_BLOCK(1, aria_encrypt);
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ECB_WALK_END();
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}
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static int ecb_do_decrypt(struct skcipher_request *req, const u32 *rkey)
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{
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ECB_WALK_START(req, ARIA_BLOCK_SIZE, ARIA_AESNI_PARALLEL_BLOCKS);
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ECB_BLOCK(ARIA_AESNI_AVX2_PARALLEL_BLOCKS, aria_ops.aria_decrypt_32way);
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ECB_BLOCK(ARIA_AESNI_PARALLEL_BLOCKS, aria_ops.aria_decrypt_16way);
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ECB_BLOCK(1, aria_decrypt);
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ECB_WALK_END();
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}
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static int aria_avx2_ecb_encrypt(struct skcipher_request *req)
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{
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct aria_ctx *ctx = crypto_skcipher_ctx(tfm);
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return ecb_do_encrypt(req, ctx->enc_key[0]);
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}
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static int aria_avx2_ecb_decrypt(struct skcipher_request *req)
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{
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct aria_ctx *ctx = crypto_skcipher_ctx(tfm);
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return ecb_do_decrypt(req, ctx->dec_key[0]);
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}
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static int aria_avx2_set_key(struct crypto_skcipher *tfm, const u8 *key,
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unsigned int keylen)
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{
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return aria_set_key(&tfm->base, key, keylen);
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}
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static int aria_avx2_ctr_encrypt(struct skcipher_request *req)
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{
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struct aria_avx2_request_ctx *req_ctx = skcipher_request_ctx(req);
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct aria_ctx *ctx = crypto_skcipher_ctx(tfm);
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struct skcipher_walk walk;
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unsigned int nbytes;
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int err;
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err = skcipher_walk_virt(&walk, req, false);
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while ((nbytes = walk.nbytes) > 0) {
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const u8 *src = walk.src.virt.addr;
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u8 *dst = walk.dst.virt.addr;
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while (nbytes >= ARIA_AESNI_AVX2_PARALLEL_BLOCK_SIZE) {
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kernel_fpu_begin();
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aria_ops.aria_ctr_crypt_32way(ctx, dst, src,
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&req_ctx->keystream[0],
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walk.iv);
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kernel_fpu_end();
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dst += ARIA_AESNI_AVX2_PARALLEL_BLOCK_SIZE;
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src += ARIA_AESNI_AVX2_PARALLEL_BLOCK_SIZE;
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nbytes -= ARIA_AESNI_AVX2_PARALLEL_BLOCK_SIZE;
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}
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while (nbytes >= ARIA_AESNI_PARALLEL_BLOCK_SIZE) {
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kernel_fpu_begin();
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aria_ops.aria_ctr_crypt_16way(ctx, dst, src,
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&req_ctx->keystream[0],
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walk.iv);
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kernel_fpu_end();
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dst += ARIA_AESNI_PARALLEL_BLOCK_SIZE;
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src += ARIA_AESNI_PARALLEL_BLOCK_SIZE;
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nbytes -= ARIA_AESNI_PARALLEL_BLOCK_SIZE;
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}
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while (nbytes >= ARIA_BLOCK_SIZE) {
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memcpy(&req_ctx->keystream[0], walk.iv, ARIA_BLOCK_SIZE);
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crypto_inc(walk.iv, ARIA_BLOCK_SIZE);
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aria_encrypt(ctx, &req_ctx->keystream[0],
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&req_ctx->keystream[0]);
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crypto_xor_cpy(dst, src, &req_ctx->keystream[0],
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ARIA_BLOCK_SIZE);
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dst += ARIA_BLOCK_SIZE;
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src += ARIA_BLOCK_SIZE;
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nbytes -= ARIA_BLOCK_SIZE;
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}
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if (walk.nbytes == walk.total && nbytes > 0) {
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memcpy(&req_ctx->keystream[0], walk.iv,
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ARIA_BLOCK_SIZE);
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crypto_inc(walk.iv, ARIA_BLOCK_SIZE);
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aria_encrypt(ctx, &req_ctx->keystream[0],
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&req_ctx->keystream[0]);
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crypto_xor_cpy(dst, src, &req_ctx->keystream[0],
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nbytes);
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dst += nbytes;
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src += nbytes;
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nbytes = 0;
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}
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err = skcipher_walk_done(&walk, nbytes);
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}
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return err;
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}
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static int aria_avx2_init_tfm(struct crypto_skcipher *tfm)
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{
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crypto_skcipher_set_reqsize(tfm, sizeof(struct aria_avx2_request_ctx));
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return 0;
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}
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static struct skcipher_alg aria_algs[] = {
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{
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.base.cra_name = "__ecb(aria)",
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.base.cra_driver_name = "__ecb-aria-avx2",
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.base.cra_priority = 500,
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.base.cra_flags = CRYPTO_ALG_INTERNAL,
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.base.cra_blocksize = ARIA_BLOCK_SIZE,
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.base.cra_ctxsize = sizeof(struct aria_ctx),
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.base.cra_module = THIS_MODULE,
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.min_keysize = ARIA_MIN_KEY_SIZE,
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.max_keysize = ARIA_MAX_KEY_SIZE,
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.setkey = aria_avx2_set_key,
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.encrypt = aria_avx2_ecb_encrypt,
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.decrypt = aria_avx2_ecb_decrypt,
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}, {
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.base.cra_name = "__ctr(aria)",
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.base.cra_driver_name = "__ctr-aria-avx2",
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.base.cra_priority = 500,
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.base.cra_flags = CRYPTO_ALG_INTERNAL |
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CRYPTO_ALG_SKCIPHER_REQSIZE_LARGE,
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.base.cra_blocksize = 1,
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.base.cra_ctxsize = sizeof(struct aria_ctx),
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.base.cra_module = THIS_MODULE,
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.min_keysize = ARIA_MIN_KEY_SIZE,
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.max_keysize = ARIA_MAX_KEY_SIZE,
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.ivsize = ARIA_BLOCK_SIZE,
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.chunksize = ARIA_BLOCK_SIZE,
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.setkey = aria_avx2_set_key,
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.encrypt = aria_avx2_ctr_encrypt,
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.decrypt = aria_avx2_ctr_encrypt,
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.init = aria_avx2_init_tfm,
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}
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};
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static struct simd_skcipher_alg *aria_simd_algs[ARRAY_SIZE(aria_algs)];
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static int __init aria_avx2_init(void)
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{
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const char *feature_name;
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if (!boot_cpu_has(X86_FEATURE_AVX) ||
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!boot_cpu_has(X86_FEATURE_AVX2) ||
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!boot_cpu_has(X86_FEATURE_AES) ||
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!boot_cpu_has(X86_FEATURE_OSXSAVE)) {
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pr_info("AVX2 or AES-NI instructions are not detected.\n");
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return -ENODEV;
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}
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if (!cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM,
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&feature_name)) {
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pr_info("CPU feature '%s' is not supported.\n", feature_name);
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return -ENODEV;
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}
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2023-01-15 20:15:35 +08:00
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if (boot_cpu_has(X86_FEATURE_GFNI) && IS_ENABLED(CONFIG_AS_GFNI)) {
|
crypto: x86/aria - implement aria-avx2
aria-avx2 implementation uses AVX2, AES-NI, and GFNI.
It supports 32way parallel processing.
So, byteslicing code is changed to support 32way parallel.
And it exports some aria-avx functions such as encrypt() and decrypt().
There are two main logics, s-box layer and diffusion layer.
These codes are the same as aria-avx implementation.
But some instruction are exchanged because they don't support 256bit
registers.
Also, AES-NI doesn't support 256bit register.
So, aesenclast and aesdeclast are used twice like below:
vextracti128 $1, ymm0, xmm6;
vaesenclast xmm7, xmm0, xmm0;
vaesenclast xmm7, xmm6, xmm6;
vinserti128 $1, xmm6, ymm0, ymm0;
Benchmark with modprobe tcrypt mode=610 num_mb=8192, i3-12100:
ARIA-AVX2 with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) encryption
tcrypt: 1 operation in 2003 cycles (1024 bytes)
tcrypt: 1 operation in 5867 cycles (4096 bytes)
tcrypt: 1 operation in 2358 cycles (1024 bytes)
tcrypt: 1 operation in 7295 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx2) decryption
tcrypt: 1 operation in 2004 cycles (1024 bytes)
tcrypt: 1 operation in 5956 cycles (4096 bytes)
tcrypt: 1 operation in 2409 cycles (1024 bytes)
tcrypt: 1 operation in 7564 cycles (4096 bytes)
ARIA-AVX with GFNI(128bit and 256bit)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) encryption
tcrypt: 1 operation in 2761 cycles (1024 bytes)
tcrypt: 1 operation in 9390 cycles (4096 bytes)
tcrypt: 1 operation in 3401 cycles (1024 bytes)
tcrypt: 1 operation in 11876 cycles (4096 bytes)
testing speed of multibuffer ecb(aria) (ecb-aria-avx) decryption
tcrypt: 1 operation in 2735 cycles (1024 bytes)
tcrypt: 1 operation in 9424 cycles (4096 bytes)
tcrypt: 1 operation in 3369 cycles (1024 bytes)
tcrypt: 1 operation in 11954 cycles (4096 bytes)
Signed-off-by: Taehee Yoo <ap420073@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-01-01 17:12:51 +08:00
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aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;
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aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;
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aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;
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aria_ops.aria_encrypt_32way = aria_aesni_avx2_gfni_encrypt_32way;
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aria_ops.aria_decrypt_32way = aria_aesni_avx2_gfni_decrypt_32way;
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aria_ops.aria_ctr_crypt_32way = aria_aesni_avx2_gfni_ctr_crypt_32way;
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} else {
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aria_ops.aria_encrypt_16way = aria_aesni_avx_encrypt_16way;
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aria_ops.aria_decrypt_16way = aria_aesni_avx_decrypt_16way;
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aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_ctr_crypt_16way;
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aria_ops.aria_encrypt_32way = aria_aesni_avx2_encrypt_32way;
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aria_ops.aria_decrypt_32way = aria_aesni_avx2_decrypt_32way;
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aria_ops.aria_ctr_crypt_32way = aria_aesni_avx2_ctr_crypt_32way;
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}
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return simd_register_skciphers_compat(aria_algs,
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ARRAY_SIZE(aria_algs),
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aria_simd_algs);
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}
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static void __exit aria_avx2_exit(void)
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{
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simd_unregister_skciphers(aria_algs, ARRAY_SIZE(aria_algs),
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aria_simd_algs);
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}
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module_init(aria_avx2_init);
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module_exit(aria_avx2_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Taehee Yoo <ap420073@gmail.com>");
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MODULE_DESCRIPTION("ARIA Cipher Algorithm, AVX2/AES-NI/GFNI optimized");
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MODULE_ALIAS_CRYPTO("aria");
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MODULE_ALIAS_CRYPTO("aria-aesni-avx2");
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