2017-11-03 18:28:30 +08:00
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// SPDX-License-Identifier: GPL-2.0
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/**
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* debug.h - DesignWare USB3 DRD Controller Debug Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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2014-08-20 05:37:22 +08:00
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#ifndef __DWC3_DEBUG_H
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#define __DWC3_DEBUG_H
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include "core.h"
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2014-08-20 05:37:22 +08:00
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/**
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* dwc3_gadget_ep_cmd_string - returns endpoint command string
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* @cmd: command code
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*/
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static inline const char *
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dwc3_gadget_ep_cmd_string(u8 cmd)
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{
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switch (cmd) {
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case DWC3_DEPCMD_DEPSTARTCFG:
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return "Start New Configuration";
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case DWC3_DEPCMD_ENDTRANSFER:
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return "End Transfer";
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case DWC3_DEPCMD_UPDATETRANSFER:
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return "Update Transfer";
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case DWC3_DEPCMD_STARTTRANSFER:
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return "Start Transfer";
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case DWC3_DEPCMD_CLEARSTALL:
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return "Clear Stall";
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case DWC3_DEPCMD_SETSTALL:
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return "Set Stall";
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case DWC3_DEPCMD_GETEPSTATE:
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return "Get Endpoint State";
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case DWC3_DEPCMD_SETTRANSFRESOURCE:
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return "Set Endpoint Transfer Resource";
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case DWC3_DEPCMD_SETEPCONFIG:
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return "Set Endpoint Configuration";
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default:
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return "UNKNOWN command";
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}
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}
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/**
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* dwc3_gadget_generic_cmd_string - returns generic command string
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* @cmd: command code
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*/
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static inline const char *
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dwc3_gadget_generic_cmd_string(u8 cmd)
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{
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switch (cmd) {
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case DWC3_DGCMD_SET_LMP:
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return "Set LMP";
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case DWC3_DGCMD_SET_PERIODIC_PAR:
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return "Set Periodic Parameters";
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case DWC3_DGCMD_XMIT_FUNCTION:
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return "Transmit Function Wake Device Notification";
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case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO:
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return "Set Scratchpad Buffer Array Address Lo";
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case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI:
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return "Set Scratchpad Buffer Array Address Hi";
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case DWC3_DGCMD_SELECTED_FIFO_FLUSH:
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return "Selected FIFO Flush";
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case DWC3_DGCMD_ALL_FIFO_FLUSH:
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return "All FIFO Flush";
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case DWC3_DGCMD_SET_ENDPOINT_NRDY:
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return "Set Endpoint NRDY";
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case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK:
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return "Run SoC Bus Loopback Test";
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default:
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return "UNKNOWN";
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}
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}
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/**
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* dwc3_gadget_link_string - returns link name
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* @link_state: link state code
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*/
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static inline const char *
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dwc3_gadget_link_string(enum dwc3_link_state link_state)
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{
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switch (link_state) {
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case DWC3_LINK_STATE_U0:
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return "U0";
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case DWC3_LINK_STATE_U1:
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return "U1";
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case DWC3_LINK_STATE_U2:
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return "U2";
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case DWC3_LINK_STATE_U3:
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return "U3";
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case DWC3_LINK_STATE_SS_DIS:
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return "SS.Disabled";
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case DWC3_LINK_STATE_RX_DET:
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return "RX.Detect";
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case DWC3_LINK_STATE_SS_INACT:
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return "SS.Inactive";
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case DWC3_LINK_STATE_POLL:
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return "Polling";
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case DWC3_LINK_STATE_RECOV:
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return "Recovery";
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case DWC3_LINK_STATE_HRESET:
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return "Hot Reset";
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case DWC3_LINK_STATE_CMPLY:
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return "Compliance";
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case DWC3_LINK_STATE_LPBK:
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return "Loopback";
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case DWC3_LINK_STATE_RESET:
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return "Reset";
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case DWC3_LINK_STATE_RESUME:
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return "Resume";
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default:
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return "UNKNOWN link state\n";
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}
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}
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2017-03-31 19:44:09 +08:00
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/**
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* dwc3_trb_type_string - returns TRB type as a string
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* @type: the type of the TRB
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*/
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static inline const char *dwc3_trb_type_string(unsigned int type)
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{
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switch (type) {
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case DWC3_TRBCTL_NORMAL:
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return "normal";
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case DWC3_TRBCTL_CONTROL_SETUP:
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return "setup";
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case DWC3_TRBCTL_CONTROL_STATUS2:
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return "status2";
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case DWC3_TRBCTL_CONTROL_STATUS3:
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return "status3";
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case DWC3_TRBCTL_CONTROL_DATA:
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return "data";
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case DWC3_TRBCTL_ISOCHRONOUS_FIRST:
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return "isoc-first";
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case DWC3_TRBCTL_ISOCHRONOUS:
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return "isoc";
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case DWC3_TRBCTL_LINK_TRB:
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return "link";
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default:
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return "UNKNOWN";
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}
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}
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2016-09-26 18:22:21 +08:00
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static inline const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
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{
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switch (state) {
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case EP0_UNCONNECTED:
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return "Unconnected";
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case EP0_SETUP_PHASE:
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return "Setup Phase";
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case EP0_DATA_PHASE:
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return "Data Phase";
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case EP0_STATUS_PHASE:
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return "Status Phase";
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default:
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return "UNKNOWN";
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}
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}
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2014-08-20 05:37:22 +08:00
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/**
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* dwc3_gadget_event_string - returns event name
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* @event: the event code
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*/
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2016-05-23 16:10:08 +08:00
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static inline const char *
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2017-04-28 16:28:35 +08:00
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dwc3_gadget_event_string(char *str, const struct dwc3_event_devt *event)
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2014-08-20 05:37:22 +08:00
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{
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2016-05-23 16:10:08 +08:00
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enum dwc3_link_state state = event->event_info & DWC3_LINK_STATE_MASK;
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switch (event->type) {
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_DISCONNECT:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Disconnect: [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_RESET:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Reset [%s]", dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_CONNECT_DONE:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Connection Done [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Link Change [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_WAKEUP:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "WakeUp [%s]", dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_EOPF:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "End-Of-Frame [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_SOF:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Start-Of-Frame [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Erratic Error [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_CMD_CMPL:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Command Complete [%s]",
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_OVERFLOW:
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2016-05-23 16:10:08 +08:00
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sprintf(str, "Overflow [%s]", dwc3_gadget_link_string(state));
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break;
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default:
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sprintf(str, "UNKNOWN");
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2014-08-20 05:37:22 +08:00
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}
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2016-05-23 16:10:08 +08:00
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return str;
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2014-08-20 05:37:22 +08:00
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}
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usb: dwc3: trace: decode ctrl request
Instead of *always* dumping raw ctrl bytes, let's decode standard
requests which will make the lives of those debugging DWC3 quite a bit
easier.
Output will now look like so:
irq/34-dwc3-1594 [000] d..1 107.573081: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 107.573694: dwc3_ctrl_req: Set Address(Addr = 01)
irq/34-dwc3-1594 [000] d..1 107.588319: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 107.588816: dwc3_ctrl_req: Get Configuration Descriptor(Index = 0, Length = 9)
irq/34-dwc3-1594 [000] d..1 107.589191: dwc3_ctrl_req: Set Configuration(Config = 3)
irq/34-dwc3-1594 [000] d..1 107.589846: dwc3_ctrl_req: Get BOS Descriptor(Index = 0, Length = 5)
irq/34-dwc3-1594 [000] d..1 107.590146: dwc3_ctrl_req: Get BOS Descriptor(Index = 0, Length = 22)
irq/34-dwc3-1594 [000] d..1 107.590546: dwc3_ctrl_req: Get Configuration Descriptor(Index = 0, Length = 9)
irq/34-dwc3-1594 [000] d..1 107.590840: dwc3_ctrl_req: Get Configuration Descriptor(Index = 0, Length = 69)
irq/34-dwc3-1594 [000] d..1 107.591138: dwc3_ctrl_req: Get Configuration Descriptor(Index = 1, Length = 9)
irq/34-dwc3-1594 [000] d..1 107.591541: dwc3_ctrl_req: Get Configuration Descriptor(Index = 1, Length = 32)
irq/34-dwc3-1594 [000] d..1 107.591834: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 114.701005: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 114.721080: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 114.722709: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 114.728979: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 114.730544: dwc3_ctrl_req: Get Device Qualifier Descriptor(Index = 0, Length = 10)
irq/34-dwc3-1594 [000] d..1 115.776018: dwc3_ctrl_req: Get Configuration Descriptor(Index = 0, Length = 9)
irq/34-dwc3-1594 [000] d..1 115.776760: dwc3_ctrl_req: Set Configuration(Config = 0)
irq/34-dwc3-1594 [000] d..1 115.777676: dwc3_ctrl_req: Get Configuration(Length = 1)
irq/34-dwc3-1594 [000] d..1 115.924797: dwc3_ctrl_req: Get Device Descriptor(Index = 0, Length = 18)
irq/34-dwc3-1594 [000] d..1 115.929025: dwc3_ctrl_req: Get String Descriptor(Index = 0, Length = 500)
irq/34-dwc3-1594 [000] d..1 115.929566: dwc3_ctrl_req: Get String Descriptor(Index = 1, Length = 500)
irq/34-dwc3-1594 [000] d..1 115.930911: dwc3_ctrl_req: Get String Descriptor(Index = 0, Length = 500)
irq/34-dwc3-1594 [000] d..1 115.931528: dwc3_ctrl_req: Get String Descriptor(Index = 2, Length = 500)
irq/34-dwc3-1594 [000] d..1 115.932950: dwc3_ctrl_req: Get String Descriptor(Index = 0, Length = 500)
irq/34-dwc3-1594 [000] d..1 115.933533: dwc3_ctrl_req: Get String Descriptor(Index = 3, Length = 500)
Note that Class and Vendor requests won't be decoded for obvious
reasons. Those will be printed as a raw sequence of bytes.
This patch has been tested against a normal host (both Linux and
Windows) and USB30CV Chapter 9 tests.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-04-26 21:09:09 +08:00
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static inline void dwc3_decode_get_status(__u8 t, __u16 i, __u16 l, char *str)
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{
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switch (t & USB_RECIP_MASK) {
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case USB_RECIP_INTERFACE:
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sprintf(str, "Get Interface Status(Intf = %d, Length = %d)",
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i, l);
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break;
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case USB_RECIP_ENDPOINT:
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sprintf(str, "Get Endpoint Status(ep%d%s)",
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i & ~USB_DIR_IN,
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i & USB_DIR_IN ? "in" : "out");
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break;
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}
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}
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static inline void dwc3_decode_set_clear_feature(__u8 t, __u8 b, __u16 v,
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__u16 i, char *str)
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{
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switch (t & USB_RECIP_MASK) {
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case USB_RECIP_DEVICE:
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sprintf(str, "%s Device Feature(%s%s)",
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b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
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({char *s;
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switch (v) {
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case USB_DEVICE_SELF_POWERED:
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s = "Self Powered";
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break;
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|
|
case USB_DEVICE_REMOTE_WAKEUP:
|
|
|
|
s = "Remote Wakeup";
|
|
|
|
break;
|
|
|
|
case USB_DEVICE_TEST_MODE:
|
|
|
|
s = "Test Mode";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
s = "UNKNOWN";
|
|
|
|
} s; }),
|
|
|
|
v == USB_DEVICE_TEST_MODE ?
|
|
|
|
({ char *s;
|
|
|
|
switch (i) {
|
|
|
|
case TEST_J:
|
|
|
|
s = ": TEST_J";
|
|
|
|
break;
|
|
|
|
case TEST_K:
|
|
|
|
s = ": TEST_K";
|
|
|
|
break;
|
|
|
|
case TEST_SE0_NAK:
|
|
|
|
s = ": TEST_SE0_NAK";
|
|
|
|
break;
|
|
|
|
case TEST_PACKET:
|
|
|
|
s = ": TEST_PACKET";
|
|
|
|
break;
|
|
|
|
case TEST_FORCE_EN:
|
|
|
|
s = ": TEST_FORCE_EN";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
s = ": UNKNOWN";
|
|
|
|
} s; }) : "");
|
|
|
|
break;
|
|
|
|
case USB_RECIP_INTERFACE:
|
|
|
|
sprintf(str, "%s Interface Feature(%s)",
|
|
|
|
b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
|
|
|
|
v == USB_INTRF_FUNC_SUSPEND ?
|
|
|
|
"Function Suspend" : "UNKNOWN");
|
|
|
|
break;
|
|
|
|
case USB_RECIP_ENDPOINT:
|
|
|
|
sprintf(str, "%s Endpoint Feature(%s ep%d%s)",
|
|
|
|
b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
|
|
|
|
v == USB_ENDPOINT_HALT ? "Halt" : "UNKNOWN",
|
|
|
|
i & ~USB_DIR_IN,
|
|
|
|
i & USB_DIR_IN ? "in" : "out");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_set_address(__u16 v, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Set Address(Addr = %02x)", v);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_get_set_descriptor(__u8 t, __u8 b, __u16 v,
|
|
|
|
__u16 i, __u16 l, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "%s %s Descriptor(Index = %d, Length = %d)",
|
|
|
|
b == USB_REQ_GET_DESCRIPTOR ? "Get" : "Set",
|
|
|
|
({ char *s;
|
|
|
|
switch (v >> 8) {
|
|
|
|
case USB_DT_DEVICE:
|
|
|
|
s = "Device";
|
|
|
|
break;
|
|
|
|
case USB_DT_CONFIG:
|
|
|
|
s = "Configuration";
|
|
|
|
break;
|
|
|
|
case USB_DT_STRING:
|
|
|
|
s = "String";
|
|
|
|
break;
|
|
|
|
case USB_DT_INTERFACE:
|
|
|
|
s = "Interface";
|
|
|
|
break;
|
|
|
|
case USB_DT_ENDPOINT:
|
|
|
|
s = "Endpoint";
|
|
|
|
break;
|
|
|
|
case USB_DT_DEVICE_QUALIFIER:
|
|
|
|
s = "Device Qualifier";
|
|
|
|
break;
|
|
|
|
case USB_DT_OTHER_SPEED_CONFIG:
|
|
|
|
s = "Other Speed Config";
|
|
|
|
break;
|
|
|
|
case USB_DT_INTERFACE_POWER:
|
|
|
|
s = "Interface Power";
|
|
|
|
break;
|
|
|
|
case USB_DT_OTG:
|
|
|
|
s = "OTG";
|
|
|
|
break;
|
|
|
|
case USB_DT_DEBUG:
|
|
|
|
s = "Debug";
|
|
|
|
break;
|
|
|
|
case USB_DT_INTERFACE_ASSOCIATION:
|
|
|
|
s = "Interface Association";
|
|
|
|
break;
|
|
|
|
case USB_DT_BOS:
|
|
|
|
s = "BOS";
|
|
|
|
break;
|
|
|
|
case USB_DT_DEVICE_CAPABILITY:
|
|
|
|
s = "Device Capability";
|
|
|
|
break;
|
|
|
|
case USB_DT_PIPE_USAGE:
|
|
|
|
s = "Pipe Usage";
|
|
|
|
break;
|
|
|
|
case USB_DT_SS_ENDPOINT_COMP:
|
|
|
|
s = "SS Endpoint Companion";
|
|
|
|
break;
|
|
|
|
case USB_DT_SSP_ISOC_ENDPOINT_COMP:
|
|
|
|
s = "SSP Isochronous Endpoint Companion";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
s = "UNKNOWN";
|
|
|
|
break;
|
|
|
|
} s; }), v & 0xff, l);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static inline void dwc3_decode_get_configuration(__u16 l, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Get Configuration(Length = %d)", l);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_set_configuration(__u8 v, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Set Configuration(Config = %d)", v);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_get_intf(__u16 i, __u16 l, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Get Interface(Intf = %d, Length = %d)", i, l);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_set_intf(__u8 v, __u16 i, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Set Interface(Intf = %d, Alt.Setting = %d)", i, v);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_synch_frame(__u16 i, __u16 l, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Synch Frame(Endpoint = %d, Length = %d)", i, l);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_set_sel(__u16 l, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Set SEL(Length = %d)", l);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dwc3_decode_set_isoch_delay(__u8 v, char *str)
|
|
|
|
{
|
|
|
|
sprintf(str, "Set Isochronous Delay(Delay = %d ns)", v);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_decode_ctrl - returns a string represetion of ctrl request
|
|
|
|
*/
|
|
|
|
static inline const char *dwc3_decode_ctrl(char *str, __u8 bRequestType,
|
|
|
|
__u8 bRequest, __u16 wValue, __u16 wIndex, __u16 wLength)
|
|
|
|
{
|
|
|
|
switch (bRequest) {
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
|
|
dwc3_decode_get_status(bRequestType, wIndex, wLength, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
|
|
dwc3_decode_set_clear_feature(bRequestType, bRequest, wValue,
|
|
|
|
wIndex, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
|
|
dwc3_decode_set_address(wValue, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
|
|
case USB_REQ_SET_DESCRIPTOR:
|
|
|
|
dwc3_decode_get_set_descriptor(bRequestType, bRequest, wValue,
|
|
|
|
wIndex, wLength, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
|
|
dwc3_decode_get_configuration(wLength, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
|
|
dwc3_decode_set_configuration(wValue, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_GET_INTERFACE:
|
|
|
|
dwc3_decode_get_intf(wIndex, wLength, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
|
|
dwc3_decode_set_intf(wValue, wIndex, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SYNCH_FRAME:
|
|
|
|
dwc3_decode_synch_frame(wIndex, wLength, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_SEL:
|
|
|
|
dwc3_decode_set_sel(wLength, str);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_ISOCH_DELAY:
|
|
|
|
dwc3_decode_set_isoch_delay(wValue, str);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
sprintf(str, "%02x %02x %02x %02x %02x %02x %02x %02x",
|
|
|
|
bRequestType, bRequest,
|
|
|
|
cpu_to_le16(wValue) & 0xff,
|
|
|
|
cpu_to_le16(wValue) >> 8,
|
|
|
|
cpu_to_le16(wIndex) & 0xff,
|
|
|
|
cpu_to_le16(wIndex) >> 8,
|
|
|
|
cpu_to_le16(wLength) & 0xff,
|
|
|
|
cpu_to_le16(wLength) >> 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
return str;
|
|
|
|
}
|
|
|
|
|
2014-08-20 05:37:22 +08:00
|
|
|
/**
|
|
|
|
* dwc3_ep_event_string - returns event name
|
|
|
|
* @event: then event code
|
|
|
|
*/
|
2016-05-23 16:10:08 +08:00
|
|
|
static inline const char *
|
2017-04-28 16:28:35 +08:00
|
|
|
dwc3_ep_event_string(char *str, const struct dwc3_event_depevt *event,
|
|
|
|
u32 ep0state)
|
2014-08-20 05:37:22 +08:00
|
|
|
{
|
2016-05-23 16:10:08 +08:00
|
|
|
u8 epnum = event->endpoint_number;
|
2016-09-26 18:23:34 +08:00
|
|
|
size_t len;
|
2016-05-23 16:10:08 +08:00
|
|
|
int status;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sprintf(str, "ep%d%s: ", epnum >> 1,
|
2016-08-24 19:32:39 +08:00
|
|
|
(epnum & 1) ? "in" : "out");
|
2016-05-23 16:10:08 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return "UNKNOWN";
|
|
|
|
|
|
|
|
switch (event->endpoint_event) {
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_XFERCOMPLETE:
|
2016-05-23 16:10:08 +08:00
|
|
|
strcat(str, "Transfer Complete");
|
2016-09-26 18:23:34 +08:00
|
|
|
len = strlen(str);
|
|
|
|
|
|
|
|
if (epnum <= 1)
|
|
|
|
sprintf(str + len, " [%s]", dwc3_ep0_state_string(ep0state));
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_XFERINPROGRESS:
|
2016-05-23 16:10:08 +08:00
|
|
|
strcat(str, "Transfer In-Progress");
|
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_XFERNOTREADY:
|
2016-05-23 16:10:08 +08:00
|
|
|
strcat(str, "Transfer Not Ready");
|
|
|
|
status = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
|
|
|
|
strcat(str, status ? " (Active)" : " (Not Active)");
|
2016-09-26 17:54:04 +08:00
|
|
|
|
|
|
|
/* Control Endpoints */
|
|
|
|
if (epnum <= 1) {
|
|
|
|
int phase = DEPEVT_STATUS_CONTROL_PHASE(event->status);
|
|
|
|
|
|
|
|
switch (phase) {
|
|
|
|
case DEPEVT_STATUS_CONTROL_DATA:
|
|
|
|
strcat(str, " [Data Phase]");
|
|
|
|
break;
|
|
|
|
case DEPEVT_STATUS_CONTROL_STATUS:
|
|
|
|
strcat(str, " [Status Phase]");
|
|
|
|
}
|
|
|
|
}
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_RXTXFIFOEVT:
|
2016-05-23 16:10:08 +08:00
|
|
|
strcat(str, "FIFO");
|
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_STREAMEVT:
|
2016-05-23 16:10:08 +08:00
|
|
|
status = event->status;
|
|
|
|
|
|
|
|
switch (status) {
|
|
|
|
case DEPEVT_STREAMEVT_FOUND:
|
|
|
|
sprintf(str + ret, " Stream %d Found",
|
|
|
|
event->parameters);
|
|
|
|
break;
|
|
|
|
case DEPEVT_STREAMEVT_NOTFOUND:
|
|
|
|
default:
|
|
|
|
strcat(str, " Stream Not Found");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_EPCMDCMPLT:
|
2016-05-23 16:10:08 +08:00
|
|
|
strcat(str, "Endpoint Command Complete");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
sprintf(str, "UNKNOWN");
|
2014-08-20 05:37:22 +08:00
|
|
|
}
|
|
|
|
|
2016-05-23 16:10:08 +08:00
|
|
|
return str;
|
2014-08-20 05:37:22 +08:00
|
|
|
}
|
|
|
|
|
2014-08-20 05:49:20 +08:00
|
|
|
/**
|
|
|
|
* dwc3_gadget_event_type_string - return event name
|
|
|
|
* @event: the event code
|
|
|
|
*/
|
|
|
|
static inline const char *dwc3_gadget_event_type_string(u8 event)
|
|
|
|
{
|
|
|
|
switch (event) {
|
|
|
|
case DWC3_DEVICE_EVENT_DISCONNECT:
|
|
|
|
return "Disconnect";
|
|
|
|
case DWC3_DEVICE_EVENT_RESET:
|
|
|
|
return "Reset";
|
|
|
|
case DWC3_DEVICE_EVENT_CONNECT_DONE:
|
|
|
|
return "Connect Done";
|
|
|
|
case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
|
|
|
|
return "Link Status Change";
|
|
|
|
case DWC3_DEVICE_EVENT_WAKEUP:
|
|
|
|
return "Wake-Up";
|
|
|
|
case DWC3_DEVICE_EVENT_HIBER_REQ:
|
|
|
|
return "Hibernation";
|
|
|
|
case DWC3_DEVICE_EVENT_EOPF:
|
|
|
|
return "End of Periodic Frame";
|
|
|
|
case DWC3_DEVICE_EVENT_SOF:
|
|
|
|
return "Start of Frame";
|
|
|
|
case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
|
|
|
|
return "Erratic Error";
|
|
|
|
case DWC3_DEVICE_EVENT_CMD_CMPL:
|
|
|
|
return "Command Complete";
|
|
|
|
case DWC3_DEVICE_EVENT_OVERFLOW:
|
|
|
|
return "Overflow";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-28 16:28:35 +08:00
|
|
|
static inline const char *dwc3_decode_event(char *str, u32 event, u32 ep0state)
|
2016-05-23 16:10:08 +08:00
|
|
|
{
|
|
|
|
const union dwc3_event evt = (union dwc3_event) event;
|
|
|
|
|
|
|
|
if (evt.type.is_devspec)
|
2017-04-28 16:28:35 +08:00
|
|
|
return dwc3_gadget_event_string(str, &evt.devt);
|
2016-05-23 16:10:08 +08:00
|
|
|
else
|
2017-04-28 16:28:35 +08:00
|
|
|
return dwc3_ep_event_string(str, &evt.depevt, ep0state);
|
2016-05-23 16:10:08 +08:00
|
|
|
}
|
|
|
|
|
2016-05-23 19:02:33 +08:00
|
|
|
static inline const char *dwc3_ep_cmd_status_string(int status)
|
|
|
|
{
|
|
|
|
switch (status) {
|
|
|
|
case -ETIMEDOUT:
|
|
|
|
return "Timed Out";
|
|
|
|
case 0:
|
|
|
|
return "Successful";
|
|
|
|
case DEPEVT_TRANSFER_NO_RESOURCE:
|
|
|
|
return "No Resource";
|
|
|
|
case DEPEVT_TRANSFER_BUS_EXPIRY:
|
|
|
|
return "Bus Expiry";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-23 19:16:19 +08:00
|
|
|
static inline const char *dwc3_gadget_generic_cmd_status_string(int status)
|
|
|
|
{
|
|
|
|
switch (status) {
|
|
|
|
case -ETIMEDOUT:
|
|
|
|
return "Timed Out";
|
|
|
|
case 0:
|
|
|
|
return "Successful";
|
|
|
|
case 1:
|
|
|
|
return "Error";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-09-30 19:12:34 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
2016-04-12 19:10:18 +08:00
|
|
|
extern void dwc3_debugfs_init(struct dwc3 *);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
extern void dwc3_debugfs_exit(struct dwc3 *);
|
|
|
|
#else
|
2016-04-12 19:10:18 +08:00
|
|
|
static inline void dwc3_debugfs_init(struct dwc3 *d)
|
|
|
|
{ }
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
static inline void dwc3_debugfs_exit(struct dwc3 *d)
|
|
|
|
{ }
|
|
|
|
#endif
|
2014-08-20 05:37:22 +08:00
|
|
|
#endif /* __DWC3_DEBUG_H */
|