2022-06-07 22:11:11 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-06-18 14:47:26 +08:00
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/*
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* AM33XX Power Management register bits
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*
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* This file is automatically generated from the AM33XX hardware databases.
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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2020-07-19 18:30:33 +08:00
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
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2012-06-18 14:47:26 +08:00
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
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#define AM33XX_CLKOUT2DIV_SHIFT 3
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2012-09-20 08:05:15 +08:00
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#define AM33XX_CLKOUT2DIV_WIDTH 3
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2012-06-18 14:47:26 +08:00
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#define AM33XX_CLKOUT2EN_SHIFT 7
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#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
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2012-06-18 14:47:26 +08:00
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#define AM33XX_CLKSEL_0_0_SHIFT 0
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#define AM33XX_CLKSEL_0_0_WIDTH 1
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2012-06-18 14:47:26 +08:00
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#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
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#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
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#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
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#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
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#define AM33XX_CLKTRCTRL_SHIFT 0
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#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
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#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
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#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
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2012-06-18 14:47:26 +08:00
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#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
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#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
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#define AM33XX_DPLL_EN_MASK (0x7 << 0)
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#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
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#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
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#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
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#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
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#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
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#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
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2012-06-18 14:47:26 +08:00
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#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
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#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
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#define AM33XX_IDLEST_SHIFT 16
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#define AM33XX_IDLEST_MASK (0x3 << 16)
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#define AM33XX_MODULEMODE_SHIFT 0
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#define AM33XX_MODULEMODE_MASK (0x3 << 0)
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#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
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#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
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#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
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#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
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#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
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#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
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#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
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#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
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#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
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#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
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#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
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#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
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#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
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#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
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#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
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#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
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#endif
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