[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
/*
|
2008-03-28 02:51:41 +08:00
|
|
|
* arch/arm/mach-orion5x/common.c
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
*
|
2008-03-28 02:51:41 +08:00
|
|
|
* Core functions for Marvell Orion 5x SoCs
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
*
|
|
|
|
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
|
|
|
|
*
|
2008-03-28 02:51:41 +08:00
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
2007-10-24 03:14:42 +08:00
|
|
|
#include <linux/platform_device.h>
|
2011-05-15 19:32:48 +08:00
|
|
|
#include <linux/dma-mapping.h>
|
2007-10-24 03:14:42 +08:00
|
|
|
#include <linux/serial_8250.h>
|
2007-11-12 15:51:36 +08:00
|
|
|
#include <linux/mv643xx_i2c.h>
|
2008-03-28 02:51:39 +08:00
|
|
|
#include <linux/ata_platform.h>
|
2011-11-05 18:13:41 +08:00
|
|
|
#include <linux/delay.h>
|
2011-12-15 15:15:07 +08:00
|
|
|
#include <linux/clk-provider.h>
|
2013-04-25 23:10:04 +08:00
|
|
|
#include <linux/cpu.h>
|
2008-09-25 22:23:48 +08:00
|
|
|
#include <net/dsa.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
#include <asm/page.h>
|
2008-03-01 04:12:57 +08:00
|
|
|
#include <asm/setup.h>
|
2012-03-29 01:30:01 +08:00
|
|
|
#include <asm/system_misc.h>
|
2008-03-01 04:12:57 +08:00
|
|
|
#include <asm/mach/arch.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
#include <asm/mach/map.h>
|
2008-03-28 02:51:40 +08:00
|
|
|
#include <asm/mach/time.h>
|
2010-10-15 22:50:26 +08:00
|
|
|
#include <mach/bridge-regs.h>
|
2008-08-05 23:14:15 +08:00
|
|
|
#include <mach/hardware.h>
|
|
|
|
#include <mach/orion5x.h>
|
2012-08-24 21:21:54 +08:00
|
|
|
#include <linux/platform_data/mtd-orion_nand.h>
|
|
|
|
#include <linux/platform_data/usb-ehci-orion.h>
|
2008-08-09 19:44:58 +08:00
|
|
|
#include <plat/time.h>
|
2011-05-15 19:32:41 +08:00
|
|
|
#include <plat/common.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
#include "common.h"
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* I/O Address Mapping
|
|
|
|
****************************************************************************/
|
2008-03-28 02:51:41 +08:00
|
|
|
static struct map_desc orion5x_io_desc[] __initdata = {
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
{
|
2012-09-11 20:27:21 +08:00
|
|
|
.virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
|
2008-03-28 02:51:41 +08:00
|
|
|
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
|
|
|
|
.length = ORION5X_REGS_SIZE,
|
2008-05-10 22:30:01 +08:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2012-09-11 20:27:21 +08:00
|
|
|
.virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
|
2008-03-28 02:51:41 +08:00
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_WA_SIZE,
|
2008-05-10 22:30:01 +08:00
|
|
|
.type = MT_DEVICE,
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-28 02:51:41 +08:00
|
|
|
void __init orion5x_map_io(void)
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
{
|
2008-03-28 02:51:41 +08:00
|
|
|
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
|
|
|
}
|
2007-10-24 03:14:42 +08:00
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
|
2011-12-15 15:15:07 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* CLK tree
|
|
|
|
****************************************************************************/
|
|
|
|
static struct clk *tclk;
|
|
|
|
|
2012-11-16 23:39:45 +08:00
|
|
|
void __init clk_init(void)
|
2011-12-15 15:15:07 +08:00
|
|
|
{
|
|
|
|
tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
|
|
|
|
orion5x_tclk);
|
2012-04-06 23:17:26 +08:00
|
|
|
|
|
|
|
orion_clkdev_init(tclk);
|
2011-12-15 15:15:07 +08:00
|
|
|
}
|
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI0
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_ehci0_init(void)
|
|
|
|
{
|
2012-02-08 22:52:47 +08:00
|
|
|
orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
|
|
|
|
EHCI_PHY_ORION);
|
2008-04-22 11:37:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI1
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_ehci1_init(void)
|
|
|
|
{
|
2011-12-08 04:48:08 +08:00
|
|
|
orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
|
2008-04-22 11:37:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-10-31 18:42:41 +08:00
|
|
|
/*****************************************************************************
|
2011-05-15 19:32:40 +08:00
|
|
|
* GE00
|
2007-10-31 18:42:41 +08:00
|
|
|
****************************************************************************/
|
2008-03-28 02:51:41 +08:00
|
|
|
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
|
2007-10-31 18:42:41 +08:00
|
|
|
{
|
2011-12-08 04:48:08 +08:00
|
|
|
orion_ge00_init(eth_data,
|
2011-05-15 19:32:44 +08:00
|
|
|
ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
|
2012-07-26 18:15:46 +08:00
|
|
|
IRQ_ORION5X_ETH_ERR,
|
|
|
|
MV643XX_TX_CSUM_DEFAULT_LIMIT);
|
2007-10-31 18:42:41 +08:00
|
|
|
}
|
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
|
2008-09-25 22:23:48 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* Ethernet switch
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
|
|
|
|
{
|
2011-05-15 19:32:44 +08:00
|
|
|
orion_ge00_switch_init(d, irq);
|
2008-09-25 22:23:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-11-12 15:51:36 +08:00
|
|
|
/*****************************************************************************
|
2008-04-22 11:37:12 +08:00
|
|
|
* I2C
|
2007-11-12 15:51:36 +08:00
|
|
|
****************************************************************************/
|
2008-04-22 11:37:12 +08:00
|
|
|
void __init orion5x_i2c_init(void)
|
|
|
|
{
|
2011-05-15 19:32:45 +08:00
|
|
|
orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
|
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-01-30 06:33:32 +08:00
|
|
|
/*****************************************************************************
|
2008-04-22 11:37:12 +08:00
|
|
|
* SATA
|
2008-01-30 06:33:32 +08:00
|
|
|
****************************************************************************/
|
2008-03-28 02:51:41 +08:00
|
|
|
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
|
2008-01-30 06:33:32 +08:00
|
|
|
{
|
2011-12-08 04:48:08 +08:00
|
|
|
orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
|
2008-01-30 06:33:32 +08:00
|
|
|
}
|
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 12:55:06 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* SPI
|
|
|
|
****************************************************************************/
|
2013-10-23 22:12:51 +08:00
|
|
|
void __init orion5x_spi_init(void)
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 12:55:06 +08:00
|
|
|
{
|
2012-04-06 23:17:26 +08:00
|
|
|
orion_spi_init(SPI_PHYS_BASE);
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 12:55:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-03-28 02:51:40 +08:00
|
|
|
/*****************************************************************************
|
2008-04-22 11:37:12 +08:00
|
|
|
* UART0
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_uart0_init(void)
|
|
|
|
{
|
2011-05-15 19:32:41 +08:00
|
|
|
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
|
2011-12-24 10:06:34 +08:00
|
|
|
IRQ_ORION5X_UART0, tclk);
|
2008-04-22 11:37:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART1
|
2008-03-28 02:51:40 +08:00
|
|
|
****************************************************************************/
|
2008-04-22 11:37:12 +08:00
|
|
|
void __init orion5x_uart1_init(void)
|
|
|
|
{
|
2011-05-15 19:32:41 +08:00
|
|
|
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
|
2011-12-24 10:06:34 +08:00
|
|
|
IRQ_ORION5X_UART1, tclk);
|
2008-04-22 11:37:12 +08:00
|
|
|
}
|
2008-03-28 02:51:40 +08:00
|
|
|
|
2008-06-17 18:25:12 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* XOR engine
|
|
|
|
****************************************************************************/
|
|
|
|
void __init orion5x_xor_init(void)
|
|
|
|
{
|
2011-12-08 04:48:08 +08:00
|
|
|
orion_xor0_init(ORION5X_XOR_PHYS_BASE,
|
2011-05-15 19:32:48 +08:00
|
|
|
ORION5X_XOR_PHYS_BASE + 0x200,
|
|
|
|
IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
|
2008-06-17 18:25:12 +08:00
|
|
|
}
|
|
|
|
|
2011-05-15 19:32:51 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* Cryptographic Engines and Security Accelerator (CESA)
|
|
|
|
****************************************************************************/
|
|
|
|
static void __init orion5x_crypto_init(void)
|
2009-05-08 04:59:24 +08:00
|
|
|
{
|
2013-07-26 21:17:42 +08:00
|
|
|
mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
|
|
|
|
ORION_MBUS_SRAM_ATTR,
|
|
|
|
ORION5X_SRAM_PHYS_BASE,
|
|
|
|
ORION5X_SRAM_SIZE);
|
2011-05-15 19:32:51 +08:00
|
|
|
orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
|
|
|
|
SZ_8K, IRQ_ORION5X_CESA);
|
2009-05-08 04:59:24 +08:00
|
|
|
}
|
2008-06-17 18:25:12 +08:00
|
|
|
|
2009-02-25 06:59:22 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* Watchdog
|
|
|
|
****************************************************************************/
|
2013-10-23 22:12:51 +08:00
|
|
|
static void __init orion5x_wdt_init(void)
|
2009-02-25 06:59:22 +08:00
|
|
|
{
|
2012-03-04 23:57:31 +08:00
|
|
|
orion_wdt_init();
|
2009-02-25 06:59:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* Time handling
|
|
|
|
****************************************************************************/
|
2010-10-15 22:50:26 +08:00
|
|
|
void __init orion5x_init_early(void)
|
|
|
|
{
|
2013-03-22 00:59:18 +08:00
|
|
|
u32 rev, dev;
|
|
|
|
const char *mbus_soc_name;
|
|
|
|
|
2010-10-15 22:50:26 +08:00
|
|
|
orion_time_set_base(TIMER_VIRT_BASE);
|
2012-09-24 13:54:33 +08:00
|
|
|
|
2013-03-22 00:59:18 +08:00
|
|
|
/* Initialize the MBUS driver */
|
|
|
|
orion5x_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F5281_DEV_ID)
|
|
|
|
mbus_soc_name = "marvell,orion5x-88f5281-mbus";
|
|
|
|
else if (dev == MV88F5182_DEV_ID)
|
|
|
|
mbus_soc_name = "marvell,orion5x-88f5182-mbus";
|
|
|
|
else if (dev == MV88F5181_DEV_ID)
|
|
|
|
mbus_soc_name = "marvell,orion5x-88f5181-mbus";
|
|
|
|
else if (dev == MV88F6183_DEV_ID)
|
|
|
|
mbus_soc_name = "marvell,orion5x-88f6183-mbus";
|
|
|
|
else
|
|
|
|
mbus_soc_name = NULL;
|
|
|
|
mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
|
|
|
|
ORION5X_BRIDGE_WINS_SZ,
|
|
|
|
ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
|
|
|
|
}
|
|
|
|
|
|
|
|
void orion5x_setup_wins(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The PCIe windows will no longer be statically allocated
|
|
|
|
* here once Orion5x is migrated to the pci-mvebu driver.
|
|
|
|
*/
|
2013-07-26 21:17:42 +08:00
|
|
|
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
|
|
|
|
ORION_MBUS_PCIE_IO_ATTR,
|
|
|
|
ORION5X_PCIE_IO_PHYS_BASE,
|
2013-03-22 00:59:18 +08:00
|
|
|
ORION5X_PCIE_IO_SIZE,
|
2013-07-26 21:17:42 +08:00
|
|
|
ORION5X_PCIE_IO_BUS_BASE);
|
|
|
|
mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
|
|
|
|
ORION_MBUS_PCIE_MEM_ATTR,
|
|
|
|
ORION5X_PCIE_MEM_PHYS_BASE,
|
|
|
|
ORION5X_PCIE_MEM_SIZE);
|
|
|
|
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
|
|
|
|
ORION_MBUS_PCI_IO_ATTR,
|
|
|
|
ORION5X_PCI_IO_PHYS_BASE,
|
2013-03-22 00:59:18 +08:00
|
|
|
ORION5X_PCI_IO_SIZE,
|
2013-07-26 21:17:42 +08:00
|
|
|
ORION5X_PCI_IO_BUS_BASE);
|
|
|
|
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
|
|
|
|
ORION_MBUS_PCI_MEM_ATTR,
|
|
|
|
ORION5X_PCI_MEM_PHYS_BASE,
|
|
|
|
ORION5X_PCI_MEM_SIZE);
|
2010-10-15 22:50:26 +08:00
|
|
|
}
|
|
|
|
|
2008-08-29 11:55:51 +08:00
|
|
|
int orion5x_tclk;
|
|
|
|
|
2013-10-23 22:12:51 +08:00
|
|
|
static int __init orion5x_find_tclk(void)
|
2008-08-29 11:55:51 +08:00
|
|
|
{
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 12:55:06 +08:00
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
orion5x_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F6183_DEV_ID &&
|
|
|
|
(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
|
|
|
|
return 133333333;
|
|
|
|
|
2008-08-29 11:55:51 +08:00
|
|
|
return 166666667;
|
|
|
|
}
|
|
|
|
|
2012-11-09 03:40:59 +08:00
|
|
|
void __init orion5x_timer_init(void)
|
2008-03-28 02:51:40 +08:00
|
|
|
{
|
2008-08-29 11:55:51 +08:00
|
|
|
orion5x_tclk = orion5x_find_tclk();
|
2010-10-15 22:50:26 +08:00
|
|
|
|
|
|
|
orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
|
|
|
|
IRQ_ORION5X_BRIDGE, orion5x_tclk);
|
2008-03-28 02:51:40 +08:00
|
|
|
}
|
|
|
|
|
2008-04-22 11:37:12 +08:00
|
|
|
|
2007-10-24 03:14:42 +08:00
|
|
|
/*****************************************************************************
|
|
|
|
* General
|
|
|
|
****************************************************************************/
|
|
|
|
/*
|
2008-04-26 04:31:32 +08:00
|
|
|
* Identify device ID and rev from PCIe configuration header space '0'.
|
2007-10-24 03:14:42 +08:00
|
|
|
*/
|
2012-11-16 23:39:45 +08:00
|
|
|
void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
|
2007-10-24 03:14:42 +08:00
|
|
|
{
|
2008-03-28 02:51:41 +08:00
|
|
|
orion5x_pcie_id(dev, rev);
|
2007-10-24 03:14:42 +08:00
|
|
|
|
|
|
|
if (*dev == MV88F5281_DEV_ID) {
|
|
|
|
if (*rev == MV88F5281_REV_D2) {
|
|
|
|
*dev_name = "MV88F5281-D2";
|
|
|
|
} else if (*rev == MV88F5281_REV_D1) {
|
|
|
|
*dev_name = "MV88F5281-D1";
|
2008-08-09 21:17:27 +08:00
|
|
|
} else if (*rev == MV88F5281_REV_D0) {
|
|
|
|
*dev_name = "MV88F5281-D0";
|
2007-10-24 03:14:42 +08:00
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5281-Rev-Unsupported";
|
|
|
|
}
|
|
|
|
} else if (*dev == MV88F5182_DEV_ID) {
|
|
|
|
if (*rev == MV88F5182_REV_A2) {
|
|
|
|
*dev_name = "MV88F5182-A2";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5182-Rev-Unsupported";
|
|
|
|
}
|
2007-11-11 19:05:11 +08:00
|
|
|
} else if (*dev == MV88F5181_DEV_ID) {
|
|
|
|
if (*rev == MV88F5181_REV_B1) {
|
|
|
|
*dev_name = "MV88F5181-Rev-B1";
|
2008-05-31 14:30:40 +08:00
|
|
|
} else if (*rev == MV88F5181L_REV_A1) {
|
|
|
|
*dev_name = "MV88F5181L-Rev-A1";
|
2007-11-11 19:05:11 +08:00
|
|
|
} else {
|
2008-05-31 14:30:40 +08:00
|
|
|
*dev_name = "MV88F5181(L)-Rev-Unsupported";
|
2007-11-11 19:05:11 +08:00
|
|
|
}
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 12:55:06 +08:00
|
|
|
} else if (*dev == MV88F6183_DEV_ID) {
|
|
|
|
if (*rev == MV88F6183_REV_B0) {
|
|
|
|
*dev_name = "MV88F6183-Rev-B0";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F6183-Rev-Unsupported";
|
|
|
|
}
|
2007-10-24 03:14:42 +08:00
|
|
|
} else {
|
|
|
|
*dev_name = "Device-Unknown";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-28 02:51:41 +08:00
|
|
|
void __init orion5x_init(void)
|
2007-10-24 03:14:42 +08:00
|
|
|
{
|
|
|
|
char *dev_name;
|
|
|
|
u32 dev, rev;
|
|
|
|
|
2008-03-28 02:51:41 +08:00
|
|
|
orion5x_id(&dev, &rev, &dev_name);
|
2008-08-29 11:55:51 +08:00
|
|
|
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
|
|
|
|
|
2007-10-24 03:14:42 +08:00
|
|
|
/*
|
|
|
|
* Setup Orion address map
|
|
|
|
*/
|
2013-03-22 00:59:18 +08:00
|
|
|
orion5x_setup_wins();
|
2008-08-09 21:17:27 +08:00
|
|
|
|
2011-12-15 15:15:07 +08:00
|
|
|
/* Setup root of clk tree */
|
|
|
|
clk_init();
|
|
|
|
|
2008-08-09 21:17:27 +08:00
|
|
|
/*
|
|
|
|
* Don't issue "Wait for Interrupt" instruction if we are
|
|
|
|
* running on D0 5281 silicon.
|
|
|
|
*/
|
|
|
|
if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
|
|
|
|
printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
|
2013-03-22 05:49:38 +08:00
|
|
|
cpu_idle_poll_ctrl(true);
|
2008-08-09 21:17:27 +08:00
|
|
|
}
|
2009-02-25 06:59:22 +08:00
|
|
|
|
2009-06-12 04:27:20 +08:00
|
|
|
/*
|
|
|
|
* The 5082/5181l/5182/6082/6082l/6183 have crypto
|
|
|
|
* while 5180n/5181/5281 don't have crypto.
|
|
|
|
*/
|
|
|
|
if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
|
|
|
|
dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
|
|
|
|
orion5x_crypto_init();
|
|
|
|
|
2009-02-25 06:59:22 +08:00
|
|
|
/*
|
|
|
|
* Register watchdog driver
|
|
|
|
*/
|
|
|
|
orion5x_wdt_init();
|
2007-10-24 03:14:42 +08:00
|
|
|
}
|
2008-03-01 04:12:57 +08:00
|
|
|
|
2013-07-09 07:01:40 +08:00
|
|
|
void orion5x_restart(enum reboot_mode mode, const char *cmd)
|
2011-11-05 18:13:41 +08:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Enable and issue soft reset
|
|
|
|
*/
|
|
|
|
orion5x_setbits(RSTOUTn_MASK, (1 << 2));
|
|
|
|
orion5x_setbits(CPU_SOFT_RESET, 1);
|
|
|
|
mdelay(200);
|
|
|
|
orion5x_clrbits(CPU_SOFT_RESET, 1);
|
|
|
|
}
|
|
|
|
|
2008-03-01 04:12:57 +08:00
|
|
|
/*
|
|
|
|
* Many orion-based systems have buggy bootloader implementations.
|
|
|
|
* This is a common fixup for bogus memory tags.
|
|
|
|
*/
|
ARM: platform fixups: remove mdesc argument to fixup function
Get rid of the mdesc pointer in the fixup function call. No one uses
the mdesc pointer, it shouldn't be modified anyway, and we can't wrap
it, so let's remove it.
Platform files found by:
$ regexp=$(git grep -h '\.fixup.*=' arch/arm |
sed 's!.*= *\([^,]*\),* *!\1!' | sort -u |
tr '\n' '|' | sed 's,|$,,;s,|,\\|,g')
$ git grep $regexp arch/arm
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20 18:37:50 +08:00
|
|
|
void __init tag_fixup_mem32(struct tag *t, char **from,
|
|
|
|
struct meminfo *meminfo)
|
2008-03-01 04:12:57 +08:00
|
|
|
{
|
|
|
|
for (; t->hdr.size; t = tag_next(t))
|
|
|
|
if (t->hdr.tag == ATAG_MEM &&
|
|
|
|
(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
|
|
|
|
t->u.mem.start & ~PAGE_MASK)) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Clearing invalid memory bank %dKB@0x%08x\n",
|
|
|
|
t->u.mem.size / 1024, t->u.mem.start);
|
|
|
|
t->hdr.tag = 0;
|
|
|
|
}
|
|
|
|
}
|