2012-05-11 22:25:46 +08:00
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/*
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* Platform data for the chipidea USB dual role controller
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*/
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#ifndef __LINUX_USB_CHIPIDEA_H
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#define __LINUX_USB_CHIPIDEA_H
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2012-07-07 22:56:46 +08:00
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#include <linux/usb/otg.h>
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2013-06-24 19:46:36 +08:00
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struct ci_hdrc;
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struct ci_hdrc_platform_data {
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2012-05-11 22:25:46 +08:00
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const char *name;
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/* offset of the capability registers */
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uintptr_t capoffset;
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2012-05-11 22:25:55 +08:00
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unsigned power_budget;
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2014-10-31 01:41:19 +08:00
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struct phy *phy;
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/* old usb_phy interface */
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2014-10-31 01:41:16 +08:00
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struct usb_phy *usb_phy;
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2013-06-13 22:59:56 +08:00
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enum usb_phy_interface phy_mode;
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2012-05-11 22:25:46 +08:00
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unsigned long flags;
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2013-06-24 19:46:36 +08:00
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#define CI_HDRC_REGS_SHARED BIT(0)
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2015-02-11 12:44:45 +08:00
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#define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2)
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2013-06-24 19:46:36 +08:00
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#define CI_HDRC_DISABLE_STREAMING BIT(3)
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2013-08-14 17:44:08 +08:00
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/*
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* Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
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* but otg is not supported (no register otgsc).
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*/
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#define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4)
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2014-01-10 13:51:27 +08:00
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#define CI_HDRC_IMX28_WRITE_FIX BIT(5)
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2014-02-19 13:41:43 +08:00
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#define CI_HDRC_FORCE_FULLSPEED BIT(6)
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2015-02-11 12:45:01 +08:00
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#define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7)
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usb: chipidea: add ttctrl.ttha control interface
The register of ttctrl.ttha describes like below:
- Internal TT Hub Address Representation
- RW
- Default = 0000000b
This field is used to match against the Hub Address field in QH & siTD
to determine if the packet is routed to the internal TT for directly
attached FS/LS devices. If the Hub Address in the QH or siTD does not
match this address then the packet will be broadcast on the High Speed
ports destined for a downstream High Speed hub with the address in the QH/siTD.
In silicon RTL, this entry only affects QH and siTD, and the hub.addr at
both QH and siTD are 0 in ehci core for chipidea (with hcd->has_tt = 1).
So, for QH, if the "usage_tt" flag at RTL is 0, set CI_HDRC_SET_NON_ZERO_TTHA
will not affect QH (with non-hs device); for siTD, set this flag
will change remaining space requirement for the last transaction from 1023
bytes to 188 bytes, it can increase the number of transactions within one
frame, ehci periodic schedule code will not queue the packet if the frame space
is full, so it is safe to set this flag for siTD.
With this flag, it can fix the problem Alan Stern reported below:
http://www.spinics.net/lists/linux-usb/msg123125.html
And may fix Michael Tessier's problem too.
http://www.spinics.net/lists/linux-usb/msg118679.html
CC: stern@rowland.harvard.edu
CC: michael.tessier@axiontech.ca
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2015-06-18 11:51:53 +08:00
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#define CI_HDRC_SET_NON_ZERO_TTHA BIT(8)
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2013-06-13 22:59:57 +08:00
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enum usb_dr_mode dr_mode;
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2013-06-24 19:46:36 +08:00
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#define CI_HDRC_CONTROLLER_RESET_EVENT 0
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#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
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void (*notify_event) (struct ci_hdrc *ci, unsigned event);
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2013-08-14 17:44:03 +08:00
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struct regulator *reg_vbus;
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2014-08-19 09:51:56 +08:00
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bool tpl_support;
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usb: chipidea: introduce ITC tuning interface
ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.
In some use cases like Android ADB, it only has one usb request for each
direction, and maximum payload data is only 4KB, so the speed is 4MB/s
at most, it needs controller to trigger interrupt as fast as possible
to increase the speed. The USB performance will be better if the interrupt
can be triggered faster.
Reduce ITC value is benefit for USB performance, but the interrupt number
is increased at the same time, it may increase cpu utilization too.
Most of use case cares about performance, but some may care about
cpu utilization, so, we leave a platform interface for user.
We set ITC as 1 (1 micro-frame) as default value which is aligned
with ehci core default value.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
2014-09-22 16:45:39 +08:00
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/* interrupt threshold setting */
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u32 itc_setting;
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2012-05-11 22:25:46 +08:00
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};
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/* Default offset of capability registers */
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#define DEF_CAPOFFSET 0x100
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2013-06-24 19:46:36 +08:00
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/* Add ci hdrc device */
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struct platform_device *ci_hdrc_add_device(struct device *dev,
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2012-07-07 22:56:41 +08:00
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struct resource *res, int nres,
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2013-06-24 19:46:36 +08:00
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struct ci_hdrc_platform_data *platdata);
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/* Remove ci hdrc device */
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void ci_hdrc_remove_device(struct platform_device *pdev);
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2012-07-07 22:56:41 +08:00
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2012-05-11 22:25:46 +08:00
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#endif
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