2012-03-03 07:07:21 +08:00
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/*
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* Copyright 2012 Linaro Ltd
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2013-05-30 01:15:39 +08:00
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#include <dt-bindings/interrupt-controller/irq.h>
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2013-09-18 16:53:10 +08:00
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#include <dt-bindings/mfd/dbx500-prcmu.h>
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2014-10-14 17:12:59 +08:00
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#include <dt-bindings/arm/ux500_pm_domains.h>
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2013-05-27 21:30:53 +08:00
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#include "skeleton.dtsi"
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2012-03-03 07:07:21 +08:00
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/ {
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2013-03-01 21:38:07 +08:00
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soc {
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2012-03-03 07:07:21 +08:00
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#address-cells = <1>;
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#size-cells = <1>;
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2012-03-16 00:46:17 +08:00
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compatible = "stericsson,db8500";
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2012-03-08 01:22:30 +08:00
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interrupt-parent = <&intc>;
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2012-03-03 07:07:21 +08:00
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ranges;
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2012-03-16 00:46:17 +08:00
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2015-03-23 23:49:57 +08:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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2015-04-16 15:08:15 +08:00
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ptm@801ae000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x801ae000 0x1000>;
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clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
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clock-names = "apb_pclk", "atclk";
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cpu = <&CPU0>;
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port {
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ptm0_out_port: endpoint {
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remote-endpoint = <&funnel_in_port0>;
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};
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};
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};
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ptm@801af000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x801af000 0x1000>;
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clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
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clock-names = "apb_pclk", "atclk";
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cpu = <&CPU1>;
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port {
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ptm1_out_port: endpoint {
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remote-endpoint = <&funnel_in_port1>;
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};
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};
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};
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funnel@801a6000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x801a6000 0x1000>;
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clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel output ports */
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port@0 {
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reg = <0>;
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funnel_out_port: endpoint {
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remote-endpoint =
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<&replicator_in_port0>;
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};
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};
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/* funnel input ports */
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port@1 {
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reg = <0>;
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funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&ptm0_out_port>;
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};
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};
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port@2 {
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reg = <1>;
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funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&ptm1_out_port>;
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};
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};
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};
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};
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replicator {
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compatible = "arm,coresight-replicator";
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clocks = <&prcmu_clk PRCMU_APEATCLK>;
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clock-names = "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etb_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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replicator_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&funnel_out_port>;
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};
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};
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};
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};
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tpiu@80190000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x80190000 0x1000>;
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clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
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clock-names = "apb_pclk", "atclk";
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port {
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tpiu_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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etb@801a4000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x801a4000 0x1000>;
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clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
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clock-names = "apb_pclk", "atclk";
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port {
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etb_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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2012-03-08 01:22:30 +08:00
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intc: interrupt-controller@a0411000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xa0411000 0x1000>,
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<0xa0410100 0x100>;
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};
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2015-05-14 17:22:34 +08:00
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scu@a04100000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xa0410000 0x100>;
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};
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2012-03-08 17:02:02 +08:00
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0xa0412000 0x1000>;
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2013-05-30 01:15:39 +08:00
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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2012-03-08 17:02:02 +08:00
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cache-unified;
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cache-level = <2>;
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};
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2012-03-16 00:46:17 +08:00
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pmu {
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compatible = "arm,cortex-a9-pmu";
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2013-05-30 01:15:39 +08:00
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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2012-03-16 00:46:17 +08:00
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};
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2014-10-14 17:12:58 +08:00
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pm_domains: pm_domains0 {
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compatible = "stericsson,ux500-pm-domains";
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#power-domain-cells = <1>;
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};
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2013-09-18 16:54:07 +08:00
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2013-09-18 16:53:10 +08:00
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clocks {
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compatible = "stericsson,u8500-clks";
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prcmu_clk: prcmu-clock {
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#clock-cells = <1>;
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};
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2013-06-06 17:51:04 +08:00
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prcc_pclk: prcc-periph-clock {
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#clock-cells = <2>;
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};
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2013-06-06 17:52:50 +08:00
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prcc_kclk: prcc-kernel-clock {
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#clock-cells = <2>;
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};
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2013-06-06 17:54:27 +08:00
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rtc_clk: rtc32k-clock {
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#clock-cells = <0>;
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};
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2013-06-06 17:54:48 +08:00
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smp_twd_clk: smp-twd-clock {
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#clock-cells = <0>;
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};
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2013-09-18 16:53:10 +08:00
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};
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2013-09-18 16:54:07 +08:00
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mtu@a03c6000 {
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/* Nomadik System Timer */
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compatible = "st,nomadik-mtu";
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reg = <0xa03c6000 0x1000>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
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clock-names = "timclk", "apb_pclk";
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};
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2012-03-16 17:53:24 +08:00
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timer@a0410600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xa0410600 0x20>;
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2013-05-30 01:15:39 +08:00
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interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
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2013-06-05 19:26:52 +08:00
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clocks = <&smp_twd_clk>;
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2012-03-16 17:53:24 +08:00
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};
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2015-05-14 17:22:34 +08:00
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watchdog@a0410620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xa0410620 0x20>;
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interrupts = <1 14 0x304>;
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clocks = <&smp_twd_clk>;
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};
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2012-03-16 00:46:17 +08:00
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rtc@80154000 {
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2012-05-26 14:01:31 +08:00
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compatible = "arm,rtc-pl031", "arm,primecell";
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2012-03-16 00:46:17 +08:00
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reg = <0x80154000 0x1000>;
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2013-05-30 01:15:39 +08:00
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interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
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2013-06-05 19:27:24 +08:00
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clocks = <&rtc_clk>;
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clock-names = "apb_pclk";
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2012-03-16 00:46:17 +08:00
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};
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gpio0: gpio@8012e000 {
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compatible = "stericsson,db8500-gpio",
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2012-04-13 22:05:03 +08:00
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"st,nomadik-gpio";
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2012-03-16 00:46:17 +08:00
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reg = <0x8012e000 0x80>;
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2013-05-30 01:15:39 +08:00
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interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-29 14:17:36 +08:00
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interrupt-controller;
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#interrupt-cells = <2>;
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2012-06-14 18:16:03 +08:00
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st,supports-sleepmode;
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2012-03-16 00:46:17 +08:00
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gpio-controller;
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2012-04-13 22:05:05 +08:00
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#gpio-cells = <2>;
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gpio-bank = <0>;
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2013-06-03 20:07:51 +08:00
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clocks = <&prcc_pclk 1 9>;
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2012-03-16 00:46:17 +08:00
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};
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gpio1: gpio@8012e080 {
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compatible = "stericsson,db8500-gpio",
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2012-04-13 22:05:03 +08:00
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"st,nomadik-gpio";
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2012-03-16 00:46:17 +08:00
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reg = <0x8012e080 0x80>;
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2013-05-30 01:15:39 +08:00
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-29 14:17:36 +08:00
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interrupt-controller;
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#interrupt-cells = <2>;
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2012-06-14 18:16:03 +08:00
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st,supports-sleepmode;
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2012-03-16 00:46:17 +08:00
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gpio-controller;
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2012-04-13 22:05:05 +08:00
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#gpio-cells = <2>;
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gpio-bank = <1>;
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2013-06-03 20:07:51 +08:00
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clocks = <&prcc_pclk 1 9>;
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2012-03-16 00:46:17 +08:00
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};
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gpio2: gpio@8000e000 {
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compatible = "stericsson,db8500-gpio",
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2012-04-13 22:05:03 +08:00
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"st,nomadik-gpio";
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2012-03-16 00:46:17 +08:00
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reg = <0x8000e000 0x80>;
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2013-05-30 01:15:39 +08:00
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interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-29 14:17:36 +08:00
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interrupt-controller;
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#interrupt-cells = <2>;
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2012-06-14 18:16:03 +08:00
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st,supports-sleepmode;
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2012-03-16 00:46:17 +08:00
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gpio-controller;
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2012-04-13 22:05:05 +08:00
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|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <2>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_pclk 3 8>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3: gpio@8000e080 {
|
|
|
|
|
compatible = "stericsson,db8500-gpio",
|
2012-04-13 22:05:03 +08:00
|
|
|
"st,nomadik-gpio";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x8000e080 0x80>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 14:17:36 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-06-14 18:16:03 +08:00
|
|
|
st,supports-sleepmode;
|
2012-03-16 00:46:17 +08:00
|
|
|
gpio-controller;
|
2012-04-13 22:05:05 +08:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <3>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_pclk 3 8>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio4: gpio@8000e100 {
|
|
|
|
|
compatible = "stericsson,db8500-gpio",
|
2012-04-13 22:05:03 +08:00
|
|
|
"st,nomadik-gpio";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x8000e100 0x80>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 14:17:36 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-06-14 18:16:03 +08:00
|
|
|
st,supports-sleepmode;
|
2012-03-16 00:46:17 +08:00
|
|
|
gpio-controller;
|
2012-04-13 22:05:05 +08:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <4>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_pclk 3 8>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio5: gpio@8000e180 {
|
|
|
|
|
compatible = "stericsson,db8500-gpio",
|
2012-04-13 22:05:03 +08:00
|
|
|
"st,nomadik-gpio";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x8000e180 0x80>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 14:17:36 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-06-14 18:16:03 +08:00
|
|
|
st,supports-sleepmode;
|
2012-03-16 00:46:17 +08:00
|
|
|
gpio-controller;
|
2012-04-13 22:05:05 +08:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <5>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_pclk 3 8>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio6: gpio@8011e000 {
|
|
|
|
|
compatible = "stericsson,db8500-gpio",
|
2012-04-13 22:05:03 +08:00
|
|
|
"st,nomadik-gpio";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x8011e000 0x80>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 14:17:36 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-06-14 18:16:03 +08:00
|
|
|
st,supports-sleepmode;
|
2012-03-16 00:46:17 +08:00
|
|
|
gpio-controller;
|
2012-04-13 22:05:05 +08:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <6>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
2013-10-18 15:49:21 +08:00
|
|
|
clocks = <&prcc_pclk 2 11>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio7: gpio@8011e080 {
|
|
|
|
|
compatible = "stericsson,db8500-gpio",
|
2012-04-13 22:05:03 +08:00
|
|
|
"st,nomadik-gpio";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x8011e080 0x80>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 14:17:36 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-06-14 18:16:03 +08:00
|
|
|
st,supports-sleepmode;
|
2012-03-16 00:46:17 +08:00
|
|
|
gpio-controller;
|
2012-04-13 22:05:05 +08:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <7>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
2013-10-18 15:49:21 +08:00
|
|
|
clocks = <&prcc_pclk 2 11>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio8: gpio@a03fe000 {
|
|
|
|
|
compatible = "stericsson,db8500-gpio",
|
2012-04-13 22:05:03 +08:00
|
|
|
"st,nomadik-gpio";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0xa03fe000 0x80>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 14:17:36 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-06-14 18:16:03 +08:00
|
|
|
st,supports-sleepmode;
|
2012-03-16 00:46:17 +08:00
|
|
|
gpio-controller;
|
2012-04-13 22:05:05 +08:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-bank = <8>;
|
2013-06-03 20:07:51 +08:00
|
|
|
|
2013-10-18 15:45:07 +08:00
|
|
|
clocks = <&prcc_pclk 5 1>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
2013-01-11 23:45:28 +08:00
|
|
|
pinctrl {
|
2013-05-22 22:22:55 +08:00
|
|
|
compatible = "stericsson,db8500-pinctrl";
|
2013-01-11 23:45:28 +08:00
|
|
|
prcm = <&prcmu>;
|
2012-05-26 13:25:36 +08:00
|
|
|
};
|
|
|
|
|
|
2013-05-03 22:31:51 +08:00
|
|
|
usb_per5@a03e0000 {
|
2013-08-21 00:40:27 +08:00
|
|
|
compatible = "stericsson,db8500-musb";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0xa03e0000 0x10000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:51 +08:00
|
|
|
interrupt-names = "mc";
|
|
|
|
|
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
|
|
|
|
|
dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 38 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 37 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 37 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 36 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 36 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 19 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 19 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 18 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 18 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 17 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 17 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 16 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 16 0 0x0>, /* Logical - MemToDev */
|
|
|
|
|
<&dma 39 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 39 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
|
|
|
|
|
dma-names = "iep_1_9", "oep_1_9",
|
|
|
|
|
"iep_2_10", "oep_2_10",
|
|
|
|
|
"iep_3_11", "oep_3_11",
|
|
|
|
|
"iep_4_12", "oep_4_12",
|
|
|
|
|
"iep_5_13", "oep_5_13",
|
|
|
|
|
"iep_6_14", "oep_6_14",
|
|
|
|
|
"iep_7_15", "oep_7_15",
|
|
|
|
|
"iep_8", "oep_8";
|
2013-06-03 20:08:26 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_pclk 5 0>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
2013-05-03 22:31:48 +08:00
|
|
|
dma: dma-controller@801C0000 {
|
|
|
|
|
compatible = "stericsson,db8500-dma40", "stericsson,dma40";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x801C0000 0x1000 0x40010000 0x800>;
|
2013-05-03 22:31:47 +08:00
|
|
|
reg-names = "base", "lcpa";
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:48 +08:00
|
|
|
|
|
|
|
|
#dma-cells = <3>;
|
2013-05-03 22:31:52 +08:00
|
|
|
memcpy-channels = <56 57 58 59 60>;
|
2013-06-03 20:13:54 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcmu_clk PRCMU_DMACLK>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
2013-01-11 23:45:28 +08:00
|
|
|
prcmu: prcmu@80157000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "stericsson,db8500-prcmu";
|
ARM: arm-soc non-critical fixes for 3.10
Here is a collection of fixes (and some intermixed cleanups) that were
considered less important and thus not included in the later parts of
the 3.9-rc cycle.
It's a bit all over the map, contents wise. A series of ux500 fixes
and cleanups, a bunch of various fixes for OMAP and tegra, and some for
Freescale i.MX and even Qualcomm MSM.
Note that there's also a patch on this branch to globally turn off
-Wmaybe-uninitialized when building with -Os. It's been posted several
times by Arnd and no dissent was raised, but nobody seemed interested
to pick it up. So here it is, as the topmost patch.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRggtQAAoJEIwa5zzehBx3TmYP/i4Kt3JDYEbYyAqNsH3nb0mN
3kLwViUxDdS/aZCXEaNYLwZBUgl1Zyz3oRd39zFCo4dRM2uG1AW+lC73AP3/eW6n
2oHxI43xzwjDNPxRkiipB4NXPyIoIdbRXM6/QIxXzM9zD3MJXj7BpBBpDgGAsLov
BQ2r28idxZE6jB4puPjVZCuyG5UMjA0Ko2Fp2em7QXarQBBscDvhAtjqNZ3JPtlN
thASsou1B8805J7jf5G8Wz6fNeVJg2wlWMgE9ywJpKFbut4cGM4riS/QvB0fTe6d
tmkCae0bw3UD+D+N1gYcZpeGve8oPSHbeyhrSPAfI/wAVBh0J397MgJW5/f0vW8p
DffLjQI+S450Kw0Bab41Tn0JnMnXtYUo56yjemdxa/NQJF34ycBFQ3HOm6nFxo7U
6tce2O775uvG0+rJfDbX6M+Mu7QoIi0p8sOdg0/W+pFK08xvaezsOc1NjqTvuYoC
s/2LYiIJqVG6tFVU0i/46duQhdp0I/Oj7wXtFXH0ZvZPBz0cDaSU3irB3QA9pNt5
PI6JEBg0FUPUork24gShSUf7un4Itrjlq20HTkC9/z1skx87PbB3Wa7A8jnHeFme
tpuPRvmfBWhIhp06AIA8znhDik9xuJ4B7ypsFNM0VyoV/qx+TSIHbViVQuwcOf9b
nAidtuhMjE+P2sAu+VGU
=bzsu
-----END PGP SIGNATURE-----
Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC non-critical fixes from Olof Johansson:
"Here is a collection of fixes (and some intermixed cleanups) that were
considered less important and thus not included in the later parts of
the 3.9-rc cycle.
It's a bit all over the map, contents wise. A series of ux500 fixes
and cleanups, a bunch of various fixes for OMAP and tegra, and some
for Freescale i.MX and even Qualcomm MSM.
Note that there's also a patch on this branch to globally turn off
-Wmaybe-uninitialized when building with -Os. It's been posted
several times by Arnd and no dissent was raised, but nobody seemed
interested to pick it up. So here it is, as the topmost patch."
* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
Turn off -Wmaybe-uninitialized when building with -Os
ARM: orion5x: include linux/cpu.h
ARM: tegra: call cpu_do_idle from C code
ARM: u300: fix ages old copy/paste bug
ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled
ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
ARM: tegra: fix build error when THUMB2_KERNEL enabled
ARM: msm: Fix uncompess.h tx underrun check
ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms
ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: mach-imx: mach-imx6q: Fix sparse warnings
ARM: mach-imx: src: Include "common.h
ARM: mach-imx: gpc: Include "common.h"
ARM: mach-imx: avic: Staticize *avic_base
ARM: mach-imx: tzic: Staticize *tzic_base
ARM: mach-imx: clk: Include "clk.h"
ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
...
2013-05-02 23:56:55 +08:00
|
|
|
reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
|
2013-03-26 18:26:15 +08:00
|
|
|
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
2012-04-24 17:00:15 +08:00
|
|
|
#size-cells = <1>;
|
2012-08-03 22:42:25 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-04-24 17:00:15 +08:00
|
|
|
ranges;
|
|
|
|
|
|
2012-05-28 16:50:49 +08:00
|
|
|
prcmu-timer-4@80157450 {
|
2012-04-24 17:00:15 +08:00
|
|
|
compatible = "stericsson,db8500-prcmu-timer-4";
|
|
|
|
|
reg = <0x80157450 0xC>;
|
|
|
|
|
};
|
2012-03-16 00:46:17 +08:00
|
|
|
|
2013-09-18 23:07:44 +08:00
|
|
|
cpufreq {
|
|
|
|
|
compatible = "stericsson,cpufreq-ux500";
|
|
|
|
|
clocks = <&prcmu_clk PRCMU_ARMSS>;
|
|
|
|
|
clock-names = "armss";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-15 18:56:43 +08:00
|
|
|
thermal@801573c0 {
|
|
|
|
|
compatible = "stericsson,db8500-thermal";
|
|
|
|
|
reg = <0x801573c0 0x40>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<22 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-15 18:56:43 +08:00
|
|
|
interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
|
|
|
|
|
status = "disabled";
|
2013-06-06 19:21:15 +08:00
|
|
|
};
|
2012-11-15 18:56:43 +08:00
|
|
|
|
2012-05-04 20:32:34 +08:00
|
|
|
db8500-prcmu-regulators {
|
|
|
|
|
compatible = "stericsson,db8500-prcmu-regulator";
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VAPE
|
|
|
|
|
db8500_vape_reg: db8500_vape {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vape";
|
2012-05-04 20:32:34 +08:00
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VARM
|
|
|
|
|
db8500_varm_reg: db8500_varm {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_varm";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VMODEM
|
|
|
|
|
db8500_vmodem_reg: db8500_vmodem {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vmodem";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VPLL
|
|
|
|
|
db8500_vpll_reg: db8500_vpll {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vpll";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VSMPS1
|
|
|
|
|
db8500_vsmps1_reg: db8500_vsmps1 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vsmps1";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VSMPS2
|
|
|
|
|
db8500_vsmps2_reg: db8500_vsmps2 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vsmps2";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VSMPS3
|
|
|
|
|
db8500_vsmps3_reg: db8500_vsmps3 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vsmps3";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_VRF1
|
|
|
|
|
db8500_vrf1_reg: db8500_vrf1 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_vrf1";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SVAMMDSP
|
|
|
|
|
db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_sva_mmdsp";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
|
|
|
|
|
db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_sva_mmdsp_ret";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SVAPIPE
|
|
|
|
|
db8500_sva_pipe_reg: db8500_sva_pipe {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_sva_pipe";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SIAMMDSP
|
|
|
|
|
db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_sia_mmdsp";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
|
|
|
|
|
db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SIAPIPE
|
|
|
|
|
db8500_sia_pipe_reg: db8500_sia_pipe {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_sia_pipe";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_SGA
|
|
|
|
|
db8500_sga_reg: db8500_sga {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_sga";
|
2012-05-04 20:32:34 +08:00
|
|
|
vin-supply = <&db8500_vape_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_B2R2_MCDE
|
|
|
|
|
db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_b2r2_mcde";
|
2012-05-04 20:32:34 +08:00
|
|
|
vin-supply = <&db8500_vape_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_ESRAM12
|
|
|
|
|
db8500_esram12_reg: db8500_esram12 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_esram12";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_ESRAM12RET
|
|
|
|
|
db8500_esram12_ret_reg: db8500_esram12_ret {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_esram12_ret";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_ESRAM34
|
|
|
|
|
db8500_esram34_reg: db8500_esram34 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_esram34";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// DB8500_REGULATOR_SWITCH_ESRAM34RET
|
|
|
|
|
db8500_esram34_ret_reg: db8500_esram34_ret {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "db8500_esram34_ret";
|
2012-05-04 20:32:34 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-12 16:39:01 +08:00
|
|
|
ab8500 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "stericsson,ab8500";
|
2012-08-04 03:37:35 +08:00
|
|
|
interrupt-parent = <&intc>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-29 10:49:33 +08:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2012-05-29 14:29:53 +08:00
|
|
|
|
2013-06-18 16:51:57 +08:00
|
|
|
ab8500_gpio: ab8500-gpio {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-26 14:03:48 +08:00
|
|
|
ab8500-rtc {
|
|
|
|
|
compatible = "stericsson,ab8500-rtc";
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <17 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
18 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-26 14:03:48 +08:00
|
|
|
interrupt-names = "60S", "ALARM";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-28 16:59:26 +08:00
|
|
|
ab8500-gpadc {
|
|
|
|
|
compatible = "stericsson,ab8500-gpadc";
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <32 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
39 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-28 16:59:26 +08:00
|
|
|
interrupt-names = "HW_CONV_END", "SW_CONV_END";
|
|
|
|
|
vddadc-supply = <&ab8500_ldo_tvout_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-19 10:45:41 +08:00
|
|
|
ab8500_battery: ab8500_battery {
|
|
|
|
|
stericsson,battery-type = "LIPO";
|
|
|
|
|
thermistor-on-batctrl;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ab8500_fg {
|
|
|
|
|
compatible = "stericsson,ab8500-fg";
|
|
|
|
|
battery = <&ab8500_battery>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-19 11:16:58 +08:00
|
|
|
ab8500_btemp {
|
|
|
|
|
compatible = "stericsson,ab8500-btemp";
|
|
|
|
|
battery = <&ab8500_battery>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-19 11:17:47 +08:00
|
|
|
ab8500_charger {
|
|
|
|
|
compatible = "stericsson,ab8500-charger";
|
|
|
|
|
battery = <&ab8500_battery>;
|
|
|
|
|
vddadc-supply = <&ab8500_ldo_tvout_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-31 23:40:33 +08:00
|
|
|
ab8500_chargalg {
|
|
|
|
|
compatible = "stericsson,ab8500-chargalg";
|
|
|
|
|
battery = <&ab8500_battery>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-19 10:45:41 +08:00
|
|
|
ab8500_usb {
|
2012-05-03 21:40:24 +08:00
|
|
|
compatible = "stericsson,ab8500-usb";
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
96 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
14 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
15 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
79 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
74 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
75 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-03 21:40:24 +08:00
|
|
|
interrupt-names = "ID_WAKEUP_R",
|
|
|
|
|
"ID_WAKEUP_F",
|
|
|
|
|
"VBUS_DET_F",
|
|
|
|
|
"VBUS_DET_R",
|
|
|
|
|
"USB_LINK_STATUS",
|
|
|
|
|
"USB_ADP_PROBE_PLUG",
|
|
|
|
|
"USB_ADP_PROBE_UNPLUG";
|
2013-04-09 17:16:56 +08:00
|
|
|
vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
|
2012-05-03 21:40:24 +08:00
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
|
|
|
|
musb_1v8-supply = <&db8500_vsmps2_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-02 15:45:40 +08:00
|
|
|
ab8500-ponkey {
|
2012-08-09 20:00:12 +08:00
|
|
|
compatible = "stericsson,ab8500-poweron-key";
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
7 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-02 15:45:40 +08:00
|
|
|
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-03 19:53:55 +08:00
|
|
|
ab8500-sysctrl {
|
|
|
|
|
compatible = "stericsson,ab8500-sysctrl";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-03 20:03:59 +08:00
|
|
|
ab8500-pwm {
|
|
|
|
|
compatible = "stericsson,ab8500-pwm";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-01 23:11:19 +08:00
|
|
|
ab8500-debugfs {
|
|
|
|
|
compatible = "stericsson,ab8500-debug";
|
|
|
|
|
};
|
2012-05-29 14:29:53 +08:00
|
|
|
|
2012-07-25 19:50:13 +08:00
|
|
|
codec: ab8500-codec {
|
|
|
|
|
compatible = "stericsson,ab8500-codec";
|
|
|
|
|
|
2013-05-30 21:27:43 +08:00
|
|
|
V-AUD-supply = <&ab8500_ldo_audio_reg>;
|
|
|
|
|
V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
|
|
|
|
|
V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
|
|
|
|
|
V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
|
|
|
|
|
|
2012-07-25 19:50:13 +08:00
|
|
|
stericsson,earpeice-cmv = <950>; /* Units in mV. */
|
|
|
|
|
};
|
|
|
|
|
|
2013-06-08 00:11:19 +08:00
|
|
|
ext_regulators: ab8500-ext-regulators {
|
|
|
|
|
compatible = "stericsson,ab8500-ext-regulator";
|
|
|
|
|
|
|
|
|
|
ab8500_ext1_reg: ab8500_ext1 {
|
|
|
|
|
regulator-compatible = "ab8500_ext1";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ab8500_ext2_reg: ab8500_ext2 {
|
|
|
|
|
regulator-compatible = "ab8500_ext2";
|
|
|
|
|
regulator-min-microvolt = <1360000>;
|
|
|
|
|
regulator-max-microvolt = <1360000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ab8500_ext3_reg: ab8500_ext3 {
|
|
|
|
|
regulator-compatible = "ab8500_ext3";
|
|
|
|
|
regulator-min-microvolt = <3400000>;
|
|
|
|
|
regulator-max-microvolt = <3400000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-29 14:29:53 +08:00
|
|
|
ab8500-regulators {
|
|
|
|
|
compatible = "stericsson,ab8500-regulator";
|
2013-06-08 00:11:20 +08:00
|
|
|
vin-supply = <&ab8500_ext3_reg>;
|
2012-05-29 14:29:53 +08:00
|
|
|
|
|
|
|
|
// supplies to the display/camera
|
|
|
|
|
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_aux1";
|
2012-05-29 14:29:53 +08:00
|
|
|
regulator-min-microvolt = <2500000>;
|
|
|
|
|
regulator-max-microvolt = <2900000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
/* BUG: If turned off MMC will be affected. */
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supplies to the on-board eMMC
|
|
|
|
|
ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_aux2";
|
2012-05-29 14:29:53 +08:00
|
|
|
regulator-min-microvolt = <1100000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for VAUX3; SDcard slots
|
|
|
|
|
ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_aux3";
|
2012-05-29 14:29:53 +08:00
|
|
|
regulator-min-microvolt = <1100000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for v-intcore12; VINTCORE12 LDO
|
2013-04-09 17:16:56 +08:00
|
|
|
ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
|
|
|
|
|
regulator-compatible = "ab8500_ldo_intcore";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for tvout; gpadc; TVOUT LDO
|
|
|
|
|
ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_tvout";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for ab8500-usb; USB LDO
|
|
|
|
|
ab8500_ldo_usb_reg: ab8500_ldo_usb {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_usb";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for ab8500-vaudio; VAUDIO LDO
|
|
|
|
|
ab8500_ldo_audio_reg: ab8500_ldo_audio {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_audio";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
2013-05-30 21:27:41 +08:00
|
|
|
// supply for v-anamic1 VAMIC1 LDO
|
2012-05-29 14:29:53 +08:00
|
|
|
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_anamic1";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
|
2013-05-30 21:27:42 +08:00
|
|
|
ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
|
|
|
|
|
regulator-compatible = "ab8500_ldo_anamic2";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for v-dmic; VDMIC LDO
|
|
|
|
|
ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_dmic";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// supply for U8500 CSI/DSI; VANA LDO
|
|
|
|
|
ab8500_ldo_ana_reg: ab8500_ldo_ana {
|
2012-06-20 20:23:05 +08:00
|
|
|
regulator-compatible = "ab8500_ldo_ana";
|
2012-05-29 14:29:53 +08:00
|
|
|
};
|
|
|
|
|
};
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@80004000 {
|
2012-06-18 16:55:44 +08:00
|
|
|
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x80004000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-24 18:07:02 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2012-06-18 16:55:44 +08:00
|
|
|
v-i2c-supply = <&db8500_vape_reg>;
|
|
|
|
|
|
|
|
|
|
clock-frequency = <400000>;
|
2013-06-03 20:15:22 +08:00
|
|
|
clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
|
|
|
|
|
clock-names = "i2cclk", "apb_pclk";
|
2014-10-14 17:13:01 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@80122000 {
|
2012-06-18 16:55:44 +08:00
|
|
|
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x80122000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-24 18:07:02 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2012-06-18 16:55:44 +08:00
|
|
|
v-i2c-supply = <&db8500_vape_reg>;
|
|
|
|
|
|
|
|
|
|
clock-frequency = <400000>;
|
2013-06-03 20:15:22 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
|
|
|
|
|
clock-names = "i2cclk", "apb_pclk";
|
2014-10-14 17:13:01 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@80128000 {
|
2012-06-18 16:55:44 +08:00
|
|
|
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x80128000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-24 18:07:02 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2012-06-18 16:55:44 +08:00
|
|
|
v-i2c-supply = <&db8500_vape_reg>;
|
|
|
|
|
|
|
|
|
|
clock-frequency = <400000>;
|
2013-06-03 20:15:22 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
|
|
|
|
|
clock-names = "i2cclk", "apb_pclk";
|
2014-10-14 17:13:01 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@80110000 {
|
2012-06-18 16:55:44 +08:00
|
|
|
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x80110000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-24 18:07:02 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2012-06-18 16:55:44 +08:00
|
|
|
v-i2c-supply = <&db8500_vape_reg>;
|
|
|
|
|
|
|
|
|
|
clock-frequency = <400000>;
|
2013-06-03 20:15:22 +08:00
|
|
|
|
|
|
|
|
clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
|
|
|
|
|
clock-names = "i2cclk", "apb_pclk";
|
2014-10-14 17:13:01 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@8012a000 {
|
2012-06-18 16:55:44 +08:00
|
|
|
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
|
2012-03-16 00:46:17 +08:00
|
|
|
reg = <0x8012a000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-24 18:07:02 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2012-06-18 16:55:44 +08:00
|
|
|
v-i2c-supply = <&db8500_vape_reg>;
|
|
|
|
|
|
|
|
|
|
clock-frequency = <400000>;
|
2013-06-03 20:15:22 +08:00
|
|
|
|
2013-10-18 16:39:58 +08:00
|
|
|
clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
|
2013-06-03 20:15:22 +08:00
|
|
|
clock-names = "i2cclk", "apb_pclk";
|
2014-10-14 17:13:01 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ssp@80002000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
2012-09-07 19:09:34 +08:00
|
|
|
reg = <0x80002000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
2012-03-16 00:46:17 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-10-18 16:25:52 +08:00
|
|
|
clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
|
2014-02-24 20:30:15 +08:00
|
|
|
clock-names = "SSPCLK", "apb_pclk";
|
2013-10-18 16:25:52 +08:00
|
|
|
dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 8 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
2014-10-14 17:13:00 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-10-18 16:25:52 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ssp@80003000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x80003000 0x1000>;
|
|
|
|
|
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
|
2014-02-24 20:30:15 +08:00
|
|
|
clock-names = "SSPCLK", "apb_pclk";
|
2013-10-18 16:25:52 +08:00
|
|
|
dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 9 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
2014-10-14 17:13:00 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-10-18 16:25:52 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@8011a000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x8011a000 0x1000>;
|
|
|
|
|
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
/* Same clock wired to kernel and pclk */
|
|
|
|
|
clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
|
2014-02-24 20:30:15 +08:00
|
|
|
clock-names = "SSPCLK", "apb_pclk";
|
2013-10-18 16:25:52 +08:00
|
|
|
dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 0 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
2014-10-14 17:13:00 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-10-18 16:25:52 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@80112000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x80112000 0x1000>;
|
|
|
|
|
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
/* Same clock wired to kernel and pclk */
|
|
|
|
|
clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
|
2014-02-24 20:30:15 +08:00
|
|
|
clock-names = "SSPCLK", "apb_pclk";
|
2013-10-18 16:25:52 +08:00
|
|
|
dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 35 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
2014-10-14 17:13:00 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-10-18 16:25:52 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@80111000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x80111000 0x1000>;
|
|
|
|
|
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
/* Same clock wired to kernel and pclk */
|
|
|
|
|
clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
|
2014-02-24 20:30:15 +08:00
|
|
|
clock-names = "SSPCLK", "apb_pclk";
|
2013-10-18 16:25:52 +08:00
|
|
|
dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 33 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
2014-10-14 17:13:00 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-10-18 16:25:52 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@80129000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x80129000 0x1000>;
|
|
|
|
|
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
/* Same clock wired to kernel and pclk */
|
|
|
|
|
clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
|
2014-02-24 20:30:15 +08:00
|
|
|
clock-names = "SSPCLK", "apb_pclk";
|
2013-10-18 16:25:52 +08:00
|
|
|
dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 40 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
2014-10-14 17:13:00 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2012-03-16 00:46:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart@80120000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x80120000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:49 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 13 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-03 20:17:17 +08:00
|
|
|
clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
|
|
|
|
|
clock-names = "uart", "apb_pclk";
|
|
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-05-03 22:31:49 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
uart@80121000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x80121000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:49 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 12 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-03 20:17:17 +08:00
|
|
|
clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
|
|
|
|
|
clock-names = "uart", "apb_pclk";
|
|
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-05-03 22:31:49 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
uart@80007000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x80007000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:49 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 11 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-03 20:17:17 +08:00
|
|
|
clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
|
|
|
|
|
clock-names = "uart", "apb_pclk";
|
|
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-26 19:55:56 +08:00
|
|
|
sdi0_per1@80126000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
reg = <0x80126000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:50 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 29 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-06 19:28:50 +08:00
|
|
|
clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
|
|
|
|
|
clock-names = "sdi", "apb_pclk";
|
2014-10-14 17:12:59 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-10-24 18:10:05 +08:00
|
|
|
|
2012-09-26 19:55:56 +08:00
|
|
|
sdi1_per2@80118000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
reg = <0x80118000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:50 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 32 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-06 19:28:50 +08:00
|
|
|
clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
|
|
|
|
|
clock-names = "sdi", "apb_pclk";
|
2014-10-14 17:12:59 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-10-24 18:10:05 +08:00
|
|
|
|
2012-09-26 19:55:56 +08:00
|
|
|
sdi2_per3@80005000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
reg = <0x80005000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:50 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 28 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-06 19:28:50 +08:00
|
|
|
clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
|
|
|
|
|
clock-names = "sdi", "apb_pclk";
|
2014-10-14 17:12:59 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-10-24 18:10:05 +08:00
|
|
|
|
2012-09-26 19:55:56 +08:00
|
|
|
sdi3_per2@80119000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
reg = <0x80119000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2014-06-11 16:45:50 +08:00
|
|
|
dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 41 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-06 19:28:50 +08:00
|
|
|
clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
|
|
|
|
|
clock-names = "sdi", "apb_pclk";
|
2014-10-14 17:12:59 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-10-24 18:10:05 +08:00
|
|
|
|
2012-09-26 19:55:56 +08:00
|
|
|
sdi4_per2@80114000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
reg = <0x80114000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-03 22:31:50 +08:00
|
|
|
|
|
|
|
|
dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 42 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-06 19:28:50 +08:00
|
|
|
clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
|
|
|
|
|
clock-names = "sdi", "apb_pclk";
|
2014-10-14 17:12:59 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-10-24 18:10:05 +08:00
|
|
|
|
2012-09-26 19:55:56 +08:00
|
|
|
sdi5_per3@80008000 {
|
2012-03-16 00:46:17 +08:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
2012-10-24 18:10:05 +08:00
|
|
|
reg = <0x80008000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2014-06-11 16:45:50 +08:00
|
|
|
dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
|
|
|
|
|
<&dma 43 0 0x0>; /* Logical - MemToDev */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-06 19:28:50 +08:00
|
|
|
clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
|
|
|
|
|
clock-names = "sdi", "apb_pclk";
|
2014-10-14 17:12:59 +08:00
|
|
|
power-domains = <&pm_domains DOMAIN_VAPE>;
|
2013-06-06 19:28:50 +08:00
|
|
|
|
2012-03-16 00:46:17 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-04-24 17:53:18 +08:00
|
|
|
|
2012-07-31 19:37:16 +08:00
|
|
|
msp0: msp@80123000 {
|
|
|
|
|
compatible = "stericsson,ux500-msp-i2s";
|
|
|
|
|
reg = <0x80123000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-31 19:37:16 +08:00
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
2013-06-03 20:18:00 +08:00
|
|
|
|
2013-11-06 18:16:16 +08:00
|
|
|
dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
|
|
|
|
|
<&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-03 20:18:00 +08:00
|
|
|
clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
|
|
|
|
|
clock-names = "msp", "apb_pclk";
|
|
|
|
|
|
2012-07-31 19:37:16 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
msp1: msp@80124000 {
|
|
|
|
|
compatible = "stericsson,ux500-msp-i2s";
|
|
|
|
|
reg = <0x80124000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-31 19:37:16 +08:00
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
2013-06-03 20:18:00 +08:00
|
|
|
|
2014-06-11 16:45:50 +08:00
|
|
|
/* This DMA channel only exist on DB8500 v1 */
|
2013-11-06 18:16:16 +08:00
|
|
|
dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
|
|
|
|
|
dma-names = "tx";
|
|
|
|
|
|
2013-06-03 20:18:00 +08:00
|
|
|
clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
|
|
|
|
|
clock-names = "msp", "apb_pclk";
|
|
|
|
|
|
2012-07-31 19:37:16 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// HDMI sound
|
|
|
|
|
msp2: msp@80117000 {
|
|
|
|
|
compatible = "stericsson,ux500-msp-i2s";
|
|
|
|
|
reg = <0x80117000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-31 19:37:16 +08:00
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
2013-06-03 20:18:00 +08:00
|
|
|
|
2013-11-06 18:16:16 +08:00
|
|
|
dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
|
|
|
|
|
<&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
|
|
|
|
|
HighPrio - Fixed */
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
|
2013-06-03 20:18:00 +08:00
|
|
|
clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
|
|
|
|
|
clock-names = "msp", "apb_pclk";
|
|
|
|
|
|
2012-07-31 19:37:16 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
msp3: msp@80125000 {
|
|
|
|
|
compatible = "stericsson,ux500-msp-i2s";
|
|
|
|
|
reg = <0x80125000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-31 19:37:16 +08:00
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
2013-06-03 20:18:00 +08:00
|
|
|
|
2014-06-11 16:45:50 +08:00
|
|
|
/* This DMA channel only exist on DB8500 v2 */
|
2013-11-06 18:16:16 +08:00
|
|
|
dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
|
|
|
|
|
dma-names = "rx";
|
|
|
|
|
|
2013-06-03 20:18:00 +08:00
|
|
|
clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
|
|
|
|
|
clock-names = "msp", "apb_pclk";
|
|
|
|
|
|
2012-07-31 19:37:16 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-24 17:53:18 +08:00
|
|
|
external-bus@50000000 {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
reg = <0x50000000 0x4000000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x50000000 0x4000000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-11-15 18:56:43 +08:00
|
|
|
|
|
|
|
|
cpufreq-cooling {
|
|
|
|
|
compatible = "stericsson,db8500-cpufreq-cooling";
|
|
|
|
|
status = "disabled";
|
2013-09-18 23:05:04 +08:00
|
|
|
};
|
2012-11-15 18:56:43 +08:00
|
|
|
|
2013-11-14 22:21:00 +08:00
|
|
|
mcde@a0350000 {
|
|
|
|
|
compatible = "stericsson,mcde";
|
|
|
|
|
reg = <0xa0350000 0x1000>, /* MCDE */
|
|
|
|
|
<0xa0351000 0x1000>, /* DSI link 1 */
|
|
|
|
|
<0xa0352000 0x1000>, /* DSI link 2 */
|
|
|
|
|
<0xa0353000 0x1000>; /* DSI link 3 */
|
|
|
|
|
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
|
|
|
|
|
<&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
|
|
|
|
|
<&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
|
|
|
|
|
<&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
|
|
|
|
|
<&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
|
|
|
|
|
<&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
|
|
|
|
|
<&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
|
|
|
|
|
<&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
|
|
|
|
|
};
|
|
|
|
|
|
2013-05-16 19:27:21 +08:00
|
|
|
cryp@a03cb000 {
|
|
|
|
|
compatible = "stericsson,ux500-cryp";
|
|
|
|
|
reg = <0xa03cb000 0x1000>;
|
2013-05-30 01:15:39 +08:00
|
|
|
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-16 19:27:21 +08:00
|
|
|
|
|
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
2013-09-18 23:05:52 +08:00
|
|
|
clocks = <&prcc_pclk 6 1>;
|
2013-05-16 19:27:21 +08:00
|
|
|
};
|
2013-05-16 19:27:22 +08:00
|
|
|
|
|
|
|
|
hash@a03c2000 {
|
|
|
|
|
compatible = "stericsson,ux500-hash";
|
|
|
|
|
reg = <0xa03c2000 0x1000>;
|
|
|
|
|
|
|
|
|
|
v-ape-supply = <&db8500_vape_reg>;
|
2013-09-18 23:07:27 +08:00
|
|
|
clocks = <&prcc_pclk 6 2>;
|
2013-05-16 19:27:22 +08:00
|
|
|
};
|
2012-03-03 07:07:21 +08:00
|
|
|
};
|
|
|
|
|
};
|