2019-12-11 18:56:56 +08:00
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// SPDX-License-Identifier: GPL-2.0
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// Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
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// Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
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//
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// Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
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// interface according to the operating speed between 10GBASE-R,
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// 2500BASE-X and SGMII (but unlike the 88x3310, without the control
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// word).
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//
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// This driver only supports those aspects of the PHY that I'm able to
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// observe and test with the SFP+ module, which is an incomplete subset
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// of what this PHY is able to support. For example, I only assume it
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// supports a single lane Serdes connection, but it may be that the PHY
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// is able to support more than that.
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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enum {
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MDIO_AN_C22 = 0xffe0,
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};
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static int bcm84881_wait_init(struct phy_device *phydev)
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{
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2020-03-23 23:05:54 +08:00
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int val;
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2019-12-11 18:56:56 +08:00
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2020-03-23 23:05:54 +08:00
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return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
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val, !(val & MDIO_CTRL1_RESET),
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100000, 2000000, false);
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2019-12-11 18:56:56 +08:00
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}
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static int bcm84881_config_init(struct phy_device *phydev)
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{
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_2500BASEX:
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2020-01-04 04:43:23 +08:00
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case PHY_INTERFACE_MODE_10GBASER:
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2019-12-11 18:56:56 +08:00
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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static int bcm84881_probe(struct phy_device *phydev)
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{
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/* This driver requires PMAPMD and AN blocks */
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const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
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if (!phydev->is_c45 ||
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(phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
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return -ENODEV;
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return 0;
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}
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static int bcm84881_get_features(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_c45_pma_read_abilities(phydev);
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if (ret)
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return ret;
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/* Although the PHY sets bit 1.11.8, it does not support 10M modes */
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linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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phydev->supported);
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linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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phydev->supported);
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return 0;
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}
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static int bcm84881_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u32 adv;
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int ret;
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/* Wait for the PHY to finish initialising, otherwise our
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* advertisement may be overwritten.
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*/
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ret = bcm84881_wait_init(phydev);
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if (ret)
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return ret;
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/* We don't support manual MDI control */
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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/* disabled autoneg doesn't seem to work with this PHY */
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if (phydev->autoneg == AUTONEG_DISABLE)
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return -EINVAL;
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
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MDIO_AN_C22 + MII_CTRL1000,
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ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int bcm84881_aneg_done(struct phy_device *phydev)
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{
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int bmsr, val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
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if (bmsr < 0)
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return val;
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return !!(val & MDIO_AN_STAT1_COMPLETE) &&
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!!(bmsr & BMSR_ANEGCOMPLETE);
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}
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static int bcm84881_read_status(struct phy_device *phydev)
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{
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unsigned int mode;
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int bmsr, val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
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if (val < 0)
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return val;
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if (val & MDIO_AN_CTRL1_RESTART) {
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phydev->link = 0;
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return 0;
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}
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
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if (bmsr < 0)
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return val;
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phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
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!!(bmsr & BMSR_ANEGCOMPLETE);
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phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
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!!(bmsr & BMSR_LSTATUS);
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if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
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phydev->link = false;
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linkmode_zero(phydev->lp_advertising);
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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phydev->mdix = 0;
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2020-04-23 15:57:42 +08:00
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if (!phydev->link)
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return 0;
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2019-12-11 18:56:56 +08:00
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if (phydev->autoneg_complete) {
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val = genphy_c45_read_lpa(phydev);
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if (val < 0)
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return val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_C22 + MII_STAT1000);
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if (val < 0)
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return val;
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mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
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if (phydev->autoneg == AUTONEG_ENABLE)
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phy_resolve_aneg_linkmode(phydev);
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}
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if (phydev->autoneg == AUTONEG_DISABLE) {
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/* disabled autoneg doesn't seem to work, so force the link
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* down.
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*/
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phydev->link = 0;
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return 0;
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}
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/* Set the host link mode - we set the phy interface mode and
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* the speed according to this register so that downshift works.
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* We leave the duplex setting as per the resolution from the
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* above.
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*/
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val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
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mode = (val & 0x1e) >> 1;
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if (mode == 1 || mode == 2)
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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else if (mode == 3)
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2020-01-04 04:43:23 +08:00
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phydev->interface = PHY_INTERFACE_MODE_10GBASER;
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2019-12-11 18:56:56 +08:00
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else if (mode == 4)
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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switch (mode & 7) {
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case 1:
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phydev->speed = SPEED_100;
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break;
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case 2:
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phydev->speed = SPEED_1000;
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break;
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case 3:
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phydev->speed = SPEED_10000;
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break;
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case 4:
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phydev->speed = SPEED_2500;
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break;
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case 5:
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phydev->speed = SPEED_5000;
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break;
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}
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return genphy_c45_read_mdix(phydev);
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}
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static struct phy_driver bcm84881_drivers[] = {
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{
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.phy_id = 0xae025150,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM84881",
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.config_init = bcm84881_config_init,
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.probe = bcm84881_probe,
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.get_features = bcm84881_get_features,
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.config_aneg = bcm84881_config_aneg,
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.aneg_done = bcm84881_aneg_done,
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.read_status = bcm84881_read_status,
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},
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};
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module_phy_driver(bcm84881_drivers);
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/* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
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static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
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{ 0xae025150, 0xfffffff0 },
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{ },
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};
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MODULE_AUTHOR("Russell King");
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MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
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MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
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MODULE_LICENSE("GPL");
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