2021-05-26 02:02:40 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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2023-07-15 01:47:27 +08:00
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#include <linux/of.h>
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2021-05-26 02:02:40 +08:00
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <dt-bindings/mfd/qcom-pm8008.h>
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#define I2C_INTR_STATUS_BASE 0x0550
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#define INT_RT_STS_OFFSET 0x10
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#define INT_SET_TYPE_OFFSET 0x11
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#define INT_POL_HIGH_OFFSET 0x12
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#define INT_POL_LOW_OFFSET 0x13
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#define INT_LATCHED_CLR_OFFSET 0x14
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#define INT_EN_SET_OFFSET 0x15
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#define INT_EN_CLR_OFFSET 0x16
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#define INT_LATCHED_STS_OFFSET 0x18
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enum {
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PM8008_MISC,
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PM8008_TEMP_ALARM,
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PM8008_GPIO1,
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PM8008_GPIO2,
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PM8008_NUM_PERIPHS,
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};
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#define PM8008_PERIPH_0_BASE 0x900
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#define PM8008_PERIPH_1_BASE 0x2400
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#define PM8008_PERIPH_2_BASE 0xC000
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#define PM8008_PERIPH_3_BASE 0xC100
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#define PM8008_TEMP_ALARM_ADDR PM8008_PERIPH_1_BASE
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#define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE
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#define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE
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enum {
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SET_TYPE_INDEX,
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POLARITY_HI_INDEX,
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POLARITY_LO_INDEX,
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};
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static unsigned int pm8008_config_regs[] = {
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INT_SET_TYPE_OFFSET,
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INT_POL_HIGH_OFFSET,
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INT_POL_LOW_OFFSET,
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};
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static struct regmap_irq pm8008_irqs[] = {
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_UVLO, PM8008_MISC, BIT(0)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_OVLO, PM8008_MISC, BIT(1)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST2, PM8008_MISC, BIT(2)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST3, PM8008_MISC, BIT(3)),
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REGMAP_IRQ_REG(PM8008_IRQ_MISC_LDO_OCP, PM8008_MISC, BIT(4)),
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REGMAP_IRQ_REG(PM8008_IRQ_TEMP_ALARM, PM8008_TEMP_ALARM, BIT(0)),
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REGMAP_IRQ_REG(PM8008_IRQ_GPIO1, PM8008_GPIO1, BIT(0)),
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REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)),
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};
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2023-02-17 06:22:13 +08:00
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static const unsigned int pm8008_periph_base[] = {
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PM8008_PERIPH_0_BASE,
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PM8008_PERIPH_1_BASE,
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PM8008_PERIPH_2_BASE,
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PM8008_PERIPH_3_BASE,
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};
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static unsigned int pm8008_get_irq_reg(struct regmap_irq_chip_data *data,
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unsigned int base, int index)
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{
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/* Simple linear addressing for the main status register */
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if (base == I2C_INTR_STATUS_BASE)
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return base + index;
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return pm8008_periph_base[index] + base;
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}
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2023-02-17 06:22:12 +08:00
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static int pm8008_set_type_config(unsigned int **buf, unsigned int type,
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const struct regmap_irq *irq_data, int idx,
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void *irq_drv_data)
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{
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switch (type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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buf[POLARITY_HI_INDEX][idx] &= ~irq_data->mask;
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buf[POLARITY_LO_INDEX][idx] |= irq_data->mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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buf[POLARITY_HI_INDEX][idx] |= irq_data->mask;
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buf[POLARITY_LO_INDEX][idx] &= ~irq_data->mask;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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buf[POLARITY_HI_INDEX][idx] |= irq_data->mask;
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buf[POLARITY_LO_INDEX][idx] |= irq_data->mask;
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break;
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default:
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return -EINVAL;
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}
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2023-02-17 06:22:12 +08:00
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if (type & IRQ_TYPE_EDGE_BOTH)
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buf[SET_TYPE_INDEX][idx] |= irq_data->mask;
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else
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buf[SET_TYPE_INDEX][idx] &= ~irq_data->mask;
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2021-05-26 02:02:40 +08:00
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return 0;
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}
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static struct regmap_irq_chip pm8008_irq_chip = {
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.name = "pm8008_irq",
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.main_status = I2C_INTR_STATUS_BASE,
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.num_main_regs = 1,
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.irqs = pm8008_irqs,
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.num_irqs = ARRAY_SIZE(pm8008_irqs),
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.num_regs = PM8008_NUM_PERIPHS,
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.status_base = INT_LATCHED_STS_OFFSET,
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.mask_base = INT_EN_CLR_OFFSET,
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.unmask_base = INT_EN_SET_OFFSET,
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.mask_unmask_non_inverted = true,
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.ack_base = INT_LATCHED_CLR_OFFSET,
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.config_base = pm8008_config_regs,
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.num_config_bases = ARRAY_SIZE(pm8008_config_regs),
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.num_config_regs = PM8008_NUM_PERIPHS,
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.set_type_config = pm8008_set_type_config,
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.get_irq_reg = pm8008_get_irq_reg,
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};
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static struct regmap_config qcom_mfd_regmap_cfg = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0xFFFF,
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};
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2022-06-21 16:14:02 +08:00
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static int pm8008_probe_irq_peripherals(struct device *dev,
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struct regmap *regmap,
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int client_irq)
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{
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int rc, i;
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struct regmap_irq_type *type;
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struct regmap_irq_chip_data *irq_data;
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for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) {
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type = &pm8008_irqs[i].type;
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type->type_reg_offset = pm8008_irqs[i].reg_offset;
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if (type->type_reg_offset == PM8008_MISC)
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type->types_supported = IRQ_TYPE_EDGE_RISING;
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else
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type->types_supported = (IRQ_TYPE_EDGE_BOTH |
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
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}
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2022-06-21 16:14:02 +08:00
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rc = devm_regmap_add_irq_chip(dev, regmap, client_irq,
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IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
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if (rc) {
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dev_err(dev, "Failed to add IRQ chip: %d\n", rc);
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return rc;
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}
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return 0;
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}
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static int pm8008_probe(struct i2c_client *client)
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{
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int rc;
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struct device *dev;
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struct regmap *regmap;
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2022-06-21 16:14:02 +08:00
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dev = &client->dev;
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regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
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2022-11-25 15:36:26 +08:00
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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2022-06-21 16:14:02 +08:00
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i2c_set_clientdata(client, regmap);
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2022-06-21 16:14:02 +08:00
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if (of_property_read_bool(dev->of_node, "interrupt-controller")) {
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rc = pm8008_probe_irq_peripherals(dev, regmap, client->irq);
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if (rc)
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dev_err(dev, "Failed to probe irq periphs: %d\n", rc);
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}
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2022-06-21 16:14:02 +08:00
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return devm_of_platform_populate(dev);
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}
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static const struct of_device_id pm8008_match[] = {
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{ .compatible = "qcom,pm8008", },
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{ },
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};
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2023-05-26 17:16:45 +08:00
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MODULE_DEVICE_TABLE(of, pm8008_match);
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static struct i2c_driver pm8008_mfd_driver = {
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.driver = {
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.name = "pm8008",
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.of_match_table = pm8008_match,
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},
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.probe = pm8008_probe,
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};
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module_i2c_driver(pm8008_mfd_driver);
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MODULE_LICENSE("GPL v2");
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