2013-08-13 17:56:54 +08:00
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "evergreend.h"
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u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev);
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/**
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* evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
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*
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* @rdev: radeon_device pointer
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* @fence: radeon fence object
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*
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* Add a DMA fence packet to the ring to write
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* the fence seq number and DMA trap packet to generate
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* an interrupt if needed (evergreen-SI).
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*/
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void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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/* write the fence */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
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radeon_ring_write(ring, addr & 0xfffffffc);
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
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radeon_ring_write(ring, fence->seq);
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/* generate an interrupt */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
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/* flush HDP */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
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radeon_ring_write(ring, 1);
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}
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/**
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* evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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*
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* Schedule an IB in the DMA ring (evergreen).
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*/
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void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
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struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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if (rdev->wb.enabled) {
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u32 next_rptr = ring->wptr + 4;
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while ((next_rptr & 7) != 5)
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next_rptr++;
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next_rptr += 3;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
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radeon_ring_write(ring, next_rptr);
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}
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/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
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* Pad as necessary with NOPs.
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*/
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while ((ring->wptr & 7) != 5)
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
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radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
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radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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}
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/**
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* evergreen_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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*
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* Copy GPU paging using the DMA engine (evergreen-cayman).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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int evergreen_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence)
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{
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struct radeon_semaphore *sem = NULL;
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int ring_index = rdev->asic->copy.dma_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_dw, cur_size_in_dw;
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int i, num_loops;
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int r = 0;
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r = radeon_semaphore_create(rdev, &sem);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return r;
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}
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size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
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num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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return r;
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}
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2013-11-12 19:58:05 +08:00
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radeon_semaphore_sync_to(sem, *fence);
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radeon_semaphore_sync_rings(rdev, sem, ring->idx);
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2013-08-13 17:56:54 +08:00
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for (i = 0; i < num_loops; i++) {
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cur_size_in_dw = size_in_dw;
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if (cur_size_in_dw > 0xFFFFF)
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cur_size_in_dw = 0xFFFFF;
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size_in_dw -= cur_size_in_dw;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
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radeon_ring_write(ring, dst_offset & 0xfffffffc);
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radeon_ring_write(ring, src_offset & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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src_offset += cur_size_in_dw * 4;
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dst_offset += cur_size_in_dw * 4;
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}
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r = radeon_fence_emit(rdev, fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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radeon_ring_unlock_commit(rdev, ring);
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radeon_semaphore_free(rdev, &sem, *fence);
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return r;
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}
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/**
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* evergreen_dma_is_lockup - Check if the DMA engine is locked up
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Check if the async DMA engine is locked up.
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* Returns true if the engine appears to be locked up, false if not.
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*/
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bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
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if (!(reset_mask & RADEON_RESET_DMA)) {
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radeon_ring_lockup_update(ring);
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return false;
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}
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/* force ring activities */
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radeon_ring_force_activity(rdev, ring);
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return radeon_ring_test_lockup(rdev, ring);
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}
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