2018-09-12 17:52:47 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2016-05-05 16:51:43 +08:00
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/thermal.h>
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#include "tsens.h"
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#define CONFIG_ADDR 0x3640
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#define CONFIG_ADDR_8660 0x3620
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/* CONFIG_ADDR bitmasks */
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#define CONFIG 0x9b
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#define CONFIG_MASK 0xf
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#define CONFIG_8660 1
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#define CONFIG_SHIFT_8660 28
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#define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660)
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#define CNTL_ADDR 0x3620
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/* CNTL_ADDR bitmasks */
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#define EN BIT(0)
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#define SW_RST BIT(1)
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2021-04-21 02:33:41 +08:00
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2021-04-21 02:33:39 +08:00
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#define MEASURE_PERIOD BIT(18)
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2016-05-05 16:51:43 +08:00
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#define SLP_CLK_ENA BIT(26)
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#define SLP_CLK_ENA_8660 BIT(24)
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#define SENSOR0_SHIFT 3
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#define THRESHOLD_ADDR 0x3624
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#define INT_STATUS_ADDR 0x363c
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2021-04-21 02:33:36 +08:00
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#define S0_STATUS_OFF 0x3628
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#define S1_STATUS_OFF 0x362c
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#define S2_STATUS_OFF 0x3630
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#define S3_STATUS_OFF 0x3634
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#define S4_STATUS_OFF 0x3638
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#define S5_STATUS_OFF 0x3664 /* Sensors 5-10 found on apq8064/msm8960 */
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#define S6_STATUS_OFF 0x3668
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#define S7_STATUS_OFF 0x366c
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#define S8_STATUS_OFF 0x3670
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#define S9_STATUS_OFF 0x3674
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#define S10_STATUS_OFF 0x3678
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2021-04-21 02:33:40 +08:00
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/* Original slope - 350 to compensate mC to C inaccuracy */
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static u32 tsens_msm8960_slope[] = {
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826, 826, 804, 826,
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761, 782, 782, 849,
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782, 849, 782
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};
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2019-03-20 21:17:44 +08:00
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static int suspend_8960(struct tsens_priv *priv)
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2016-05-05 16:51:43 +08:00
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{
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int ret;
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unsigned int mask;
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2019-03-20 21:17:44 +08:00
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struct regmap *map = priv->tm_map;
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2016-05-05 16:51:43 +08:00
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2019-03-20 21:17:44 +08:00
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ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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2019-03-20 21:17:44 +08:00
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ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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2019-03-20 21:17:44 +08:00
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if (priv->num_sensors > 1)
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2016-05-05 16:51:43 +08:00
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mask = SLP_CLK_ENA | EN;
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else
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mask = SLP_CLK_ENA_8660 | EN;
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ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
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if (ret)
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return ret;
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return 0;
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}
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2019-03-20 21:17:44 +08:00
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static int resume_8960(struct tsens_priv *priv)
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2016-05-05 16:51:43 +08:00
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{
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int ret;
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2019-03-20 21:17:44 +08:00
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struct regmap *map = priv->tm_map;
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2016-05-05 16:51:43 +08:00
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ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
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if (ret)
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return ret;
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/*
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* Separate CONFIG restore is not needed only for 8660 as
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* config is part of CTRL Addr and its restored as such
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*/
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2019-03-20 21:17:44 +08:00
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if (priv->num_sensors > 1) {
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2016-05-05 16:51:43 +08:00
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ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
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if (ret)
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return ret;
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}
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2019-03-20 21:17:44 +08:00
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ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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2019-03-20 21:17:44 +08:00
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ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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return 0;
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}
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2019-03-20 21:17:44 +08:00
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static int enable_8960(struct tsens_priv *priv, int id)
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2016-05-05 16:51:43 +08:00
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{
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int ret;
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2021-04-21 02:33:39 +08:00
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u32 reg, mask = BIT(id);
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2016-05-05 16:51:43 +08:00
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2019-03-20 21:17:44 +08:00
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ret = regmap_read(priv->tm_map, CNTL_ADDR, ®);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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2021-04-21 02:33:39 +08:00
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/* HARDWARE BUG:
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* On platforms with more than 6 sensors, all remaining sensors
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* must be enabled together, otherwise undefined results are expected.
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* (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver,
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* all the sensors are enabled in one step hence this bug is not
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* triggered.
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*/
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if (id > 5)
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mask = GENMASK(10, 6);
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mask <<= SENSOR0_SHIFT;
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/* Sensors already enabled. Skip. */
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if ((reg & mask) == mask)
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return 0;
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2019-03-20 21:17:44 +08:00
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ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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2021-04-21 02:33:39 +08:00
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reg |= MEASURE_PERIOD;
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2019-03-20 21:17:44 +08:00
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if (priv->num_sensors > 1)
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2016-05-05 16:51:43 +08:00
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reg |= mask | SLP_CLK_ENA | EN;
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else
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reg |= mask | SLP_CLK_ENA_8660 | EN;
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2019-03-20 21:17:44 +08:00
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ret = regmap_write(priv->tm_map, CNTL_ADDR, reg);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return ret;
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return 0;
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}
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2019-03-20 21:17:44 +08:00
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static void disable_8960(struct tsens_priv *priv)
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2016-05-05 16:51:43 +08:00
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{
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int ret;
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u32 reg_cntl;
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u32 mask;
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2019-03-20 21:17:44 +08:00
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mask = GENMASK(priv->num_sensors - 1, 0);
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2016-05-05 16:51:43 +08:00
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mask <<= SENSOR0_SHIFT;
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mask |= EN;
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2019-03-20 21:17:44 +08:00
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ret = regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl);
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2016-05-05 16:51:43 +08:00
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if (ret)
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return;
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reg_cntl &= ~mask;
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2019-03-20 21:17:44 +08:00
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if (priv->num_sensors > 1)
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2016-05-05 16:51:43 +08:00
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reg_cntl &= ~SLP_CLK_ENA;
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else
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reg_cntl &= ~SLP_CLK_ENA_8660;
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2019-03-20 21:17:44 +08:00
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regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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2016-05-05 16:51:43 +08:00
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}
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2019-03-20 21:17:44 +08:00
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static int calibrate_8960(struct tsens_priv *priv)
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2016-05-05 16:51:43 +08:00
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{
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int i;
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char *data;
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2021-04-21 02:33:40 +08:00
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u32 p1[11];
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2016-05-05 16:51:43 +08:00
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2019-03-20 21:17:44 +08:00
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data = qfprom_read(priv->dev, "calib");
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2016-05-05 16:51:43 +08:00
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if (IS_ERR(data))
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2019-03-20 21:17:44 +08:00
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data = qfprom_read(priv->dev, "calib_backup");
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2016-05-05 16:51:43 +08:00
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if (IS_ERR(data))
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return PTR_ERR(data);
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2021-04-21 02:33:40 +08:00
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for (i = 0; i < priv->num_sensors; i++) {
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p1[i] = data[i];
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priv->sensor[i].slope = tsens_msm8960_slope[i];
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}
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compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB);
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2016-05-05 16:51:43 +08:00
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2019-08-23 17:38:35 +08:00
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kfree(data);
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2016-05-05 16:51:43 +08:00
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return 0;
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}
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2021-04-21 02:33:36 +08:00
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static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {
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/* ----- SROT ------ */
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/* No VERSION information */
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/* CNTL */
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[TSENS_EN] = REG_FIELD(CNTL_ADDR, 0, 0),
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[TSENS_SW_RST] = REG_FIELD(CNTL_ADDR, 1, 1),
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/* 8960 has 5 sensors, 8660 has 11, we only handle 5 */
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[SENSOR_EN] = REG_FIELD(CNTL_ADDR, 3, 7),
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/* ----- TM ------ */
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/* INTERRUPT ENABLE */
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/* NO INTERRUPT ENABLE */
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/* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */
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[LOW_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 0, 7),
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[UP_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 8, 15),
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/* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield
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* Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp
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* MIN_THRESH_0 -> CRIT_THRESH_1
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* MAX_THRESH_0 -> CRIT_THRESH_0
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*/
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[CRIT_THRESH_1] = REG_FIELD(THRESHOLD_ADDR, 16, 23),
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[CRIT_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 24, 31),
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/* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */
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/* 1 == clear, 0 == normal operation */
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[LOW_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 9, 9),
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[UP_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 10, 10),
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/* NO CRITICAL INTERRUPT SUPPORT on 8960 */
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/* Sn_STATUS */
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[LAST_TEMP_0] = REG_FIELD(S0_STATUS_OFF, 0, 7),
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[LAST_TEMP_1] = REG_FIELD(S1_STATUS_OFF, 0, 7),
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[LAST_TEMP_2] = REG_FIELD(S2_STATUS_OFF, 0, 7),
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[LAST_TEMP_3] = REG_FIELD(S3_STATUS_OFF, 0, 7),
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[LAST_TEMP_4] = REG_FIELD(S4_STATUS_OFF, 0, 7),
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[LAST_TEMP_5] = REG_FIELD(S5_STATUS_OFF, 0, 7),
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[LAST_TEMP_6] = REG_FIELD(S6_STATUS_OFF, 0, 7),
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[LAST_TEMP_7] = REG_FIELD(S7_STATUS_OFF, 0, 7),
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[LAST_TEMP_8] = REG_FIELD(S8_STATUS_OFF, 0, 7),
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[LAST_TEMP_9] = REG_FIELD(S9_STATUS_OFF, 0, 7),
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[LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0, 7),
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/* No VALID field on 8960 */
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/* TSENS_INT_STATUS bits: 1 == threshold violated */
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[MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0),
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[LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1),
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[UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2),
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/* No CRITICAL field on 8960 */
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[MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3),
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/* TRDY: 1=ready, 0=in progress */
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[TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7),
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};
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2016-07-02 09:02:09 +08:00
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static const struct tsens_ops ops_8960 = {
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2021-04-21 02:33:38 +08:00
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.init = init_common,
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2016-05-05 16:51:43 +08:00
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.calibrate = calibrate_8960,
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2021-04-21 02:33:40 +08:00
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.get_temp = get_temp_common,
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2016-05-05 16:51:43 +08:00
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.enable = enable_8960,
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.disable = disable_8960,
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.suspend = suspend_8960,
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.resume = resume_8960,
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};
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2021-04-21 02:33:37 +08:00
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static struct tsens_features tsens_8960_feat = {
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.ver_major = VER_0,
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.crit_int = 0,
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2022-08-19 06:02:42 +08:00
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.combo_int = 0,
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2021-04-21 02:33:37 +08:00
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.adc = 1,
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.srot_split = 0,
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.max_sensors = 11,
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2022-08-19 06:02:43 +08:00
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.trip_min_temp = -40000,
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.trip_max_temp = 120000,
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2021-04-21 02:33:37 +08:00
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};
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2020-03-12 20:36:58 +08:00
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struct tsens_plat_data data_8960 = {
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2016-05-05 16:51:43 +08:00
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.num_sensors = 11,
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.ops = &ops_8960,
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2021-04-21 02:33:37 +08:00
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.feat = &tsens_8960_feat,
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2021-04-21 02:33:36 +08:00
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.fields = tsens_8960_regfields,
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2016-05-05 16:51:43 +08:00
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};
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