2018-08-22 06:02:20 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2015-11-30 09:44:30 +08:00
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/*
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* Renesas R-Car Gen3 for USB2.0 PHY driver
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*
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2017-10-12 14:34:45 +08:00
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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2015-11-30 09:44:30 +08:00
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*
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* This is based on the phy-rcar-gen2 driver:
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* Copyright (C) 2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded, Inc.
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*/
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2017-09-21 11:11:24 +08:00
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#include <linux/extcon-provider.h>
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2015-11-30 09:44:32 +08:00
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#include <linux/interrupt.h>
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2015-11-30 09:44:30 +08:00
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#include <linux/io.h>
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#include <linux/module.h>
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2019-06-10 14:23:55 +08:00
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#include <linux/mutex.h>
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2015-11-30 09:44:30 +08:00
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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2017-03-14 07:37:40 +08:00
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#include <linux/pm_runtime.h>
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2016-03-03 18:09:05 +08:00
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#include <linux/regulator/consumer.h>
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2019-10-07 15:55:10 +08:00
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#include <linux/string.h>
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2017-10-12 14:34:45 +08:00
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#include <linux/usb/of.h>
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2016-06-27 14:36:53 +08:00
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#include <linux/workqueue.h>
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2015-11-30 09:44:30 +08:00
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/******* USB2.0 Host registers (original offset is +0x200) *******/
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#define USB2_INT_ENABLE 0x000
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#define USB2_USBCTR 0x00c
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#define USB2_SPD_RSM_TIMSET 0x10c
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#define USB2_OC_TIMSET 0x110
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2015-11-30 09:44:31 +08:00
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#define USB2_COMMCTRL 0x600
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2015-11-30 09:44:32 +08:00
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#define USB2_OBINTSTA 0x604
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#define USB2_OBINTEN 0x608
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2015-11-30 09:44:31 +08:00
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#define USB2_VBCTRL 0x60c
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#define USB2_LINECTRL1 0x610
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#define USB2_ADPCTRL 0x630
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2015-11-30 09:44:30 +08:00
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/* INT_ENABLE */
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2015-11-30 09:44:32 +08:00
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#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
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2019-04-11 18:27:36 +08:00
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#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) /* For EHCI */
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#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) /* For OHCI */
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2015-11-30 09:44:30 +08:00
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/* USBCTR */
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#define USB2_USBCTR_DIRPD BIT(2)
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#define USB2_USBCTR_PLL_RST BIT(1)
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/* SPD_RSM_TIMSET */
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#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
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/* OC_TIMSET */
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#define USB2_OC_TIMSET_INIT 0x000209ab
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2015-11-30 09:44:31 +08:00
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/* COMMCTRL */
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#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
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2015-11-30 09:44:32 +08:00
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/* OBINTSTA and OBINTEN */
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#define USB2_OBINT_SESSVLDCHG BIT(12)
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#define USB2_OBINT_IDDIGCHG BIT(11)
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#define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG | \
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USB2_OBINT_IDDIGCHG)
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2015-11-30 09:44:31 +08:00
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/* VBCTRL */
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2019-08-06 16:51:19 +08:00
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#define USB2_VBCTRL_OCCLREN BIT(16)
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2015-11-30 09:44:31 +08:00
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#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
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2021-07-28 02:55:24 +08:00
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#define USB2_VBCTRL_VBOUT BIT(0)
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2015-11-30 09:44:31 +08:00
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/* LINECTRL1 */
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#define USB2_LINECTRL1_DPRPD_EN BIT(19)
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#define USB2_LINECTRL1_DP_RPD BIT(18)
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#define USB2_LINECTRL1_DMRPD_EN BIT(17)
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#define USB2_LINECTRL1_DM_RPD BIT(16)
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2016-11-09 10:30:25 +08:00
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#define USB2_LINECTRL1_OPMODE_NODRV BIT(6)
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2015-11-30 09:44:31 +08:00
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/* ADPCTRL */
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#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
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#define USB2_ADPCTRL_IDDIG BIT(19)
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#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
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#define USB2_ADPCTRL_DRVVBUS BIT(4)
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2021-07-28 02:55:24 +08:00
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/* RZ/G2L specific */
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#define USB2_OBINT_IDCHG_EN BIT(0)
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#define USB2_LINECTRL1_USB2_IDMON BIT(0)
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2019-04-11 18:27:36 +08:00
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#define NUM_OF_PHYS 4
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enum rcar_gen3_phy_index {
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PHY_INDEX_BOTH_HC,
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PHY_INDEX_OHCI,
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PHY_INDEX_EHCI,
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PHY_INDEX_HSUSB
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};
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static const u32 rcar_gen3_int_enable[NUM_OF_PHYS] = {
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USB2_INT_ENABLE_USBH_INTB_EN | USB2_INT_ENABLE_USBH_INTA_EN,
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USB2_INT_ENABLE_USBH_INTA_EN,
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USB2_INT_ENABLE_USBH_INTB_EN,
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0
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};
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struct rcar_gen3_phy {
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struct phy *phy;
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struct rcar_gen3_chan *ch;
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u32 int_enable_bits;
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bool initialized;
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bool otg_initialized;
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bool powered;
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};
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2015-11-30 09:44:30 +08:00
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struct rcar_gen3_chan {
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2016-03-03 18:09:04 +08:00
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void __iomem *base;
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2019-04-11 18:27:35 +08:00
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struct device *dev; /* platform_device's device */
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2016-04-29 16:52:25 +08:00
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struct extcon_dev *extcon;
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2019-04-11 18:27:36 +08:00
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struct rcar_gen3_phy rphys[NUM_OF_PHYS];
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2016-03-03 18:09:05 +08:00
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struct regulator *vbus;
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2016-06-27 14:36:53 +08:00
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struct work_struct work;
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2019-06-10 14:23:55 +08:00
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struct mutex lock; /* protects rphys[...].powered */
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2018-09-21 19:53:22 +08:00
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enum usb_dr_mode dr_mode;
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2020-07-17 19:44:56 +08:00
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int irq;
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2021-07-28 02:55:24 +08:00
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u32 obint_enable_bits;
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2016-06-27 14:36:53 +08:00
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bool extcon_host;
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2018-09-21 19:53:24 +08:00
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bool is_otg_channel;
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2018-09-21 19:53:19 +08:00
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bool uses_otg_pins;
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2021-07-28 02:55:24 +08:00
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bool soc_no_adp_ctrl;
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};
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struct rcar_gen3_phy_drv_data {
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const struct phy_ops *phy_usb2_ops;
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bool no_adp_ctrl;
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2015-11-30 09:44:30 +08:00
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};
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2018-09-21 19:53:24 +08:00
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/*
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* Combination about is_otg_channel and uses_otg_pins:
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*
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* Parameters || Behaviors
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* is_otg_channel | uses_otg_pins || irqs | role sysfs
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* ---------------------+---------------++--------------+------------
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* true | true || enabled | enabled
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* true | false || disabled | enabled
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* false | any || disabled | disabled
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*/
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2016-06-27 14:36:53 +08:00
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static void rcar_gen3_phy_usb2_work(struct work_struct *work)
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{
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struct rcar_gen3_chan *ch = container_of(work, struct rcar_gen3_chan,
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work);
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if (ch->extcon_host) {
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2016-12-30 12:11:28 +08:00
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extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, true);
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extcon_set_state_sync(ch->extcon, EXTCON_USB, false);
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2016-06-27 14:36:53 +08:00
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} else {
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2016-12-30 12:11:28 +08:00
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extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, false);
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extcon_set_state_sync(ch->extcon, EXTCON_USB, true);
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2016-06-27 14:36:53 +08:00
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}
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}
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2015-11-30 09:44:31 +08:00
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static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
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{
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2016-03-03 18:09:04 +08:00
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void __iomem *usb2_base = ch->base;
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2015-11-30 09:44:31 +08:00
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u32 val = readl(usb2_base + USB2_COMMCTRL);
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2019-04-11 18:27:35 +08:00
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dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, host);
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2015-11-30 09:44:31 +08:00
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if (host)
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val &= ~USB2_COMMCTRL_OTG_PERI;
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else
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val |= USB2_COMMCTRL_OTG_PERI;
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writel(val, usb2_base + USB2_COMMCTRL);
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}
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static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
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{
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2016-03-03 18:09:04 +08:00
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void __iomem *usb2_base = ch->base;
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2015-11-30 09:44:31 +08:00
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u32 val = readl(usb2_base + USB2_LINECTRL1);
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2019-04-11 18:27:35 +08:00
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dev_vdbg(ch->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
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2015-11-30 09:44:31 +08:00
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val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
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if (dp)
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val |= USB2_LINECTRL1_DP_RPD;
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if (dm)
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val |= USB2_LINECTRL1_DM_RPD;
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writel(val, usb2_base + USB2_LINECTRL1);
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}
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static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
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{
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2016-03-03 18:09:04 +08:00
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void __iomem *usb2_base = ch->base;
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2021-07-28 02:55:24 +08:00
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u32 vbus_ctrl_reg = USB2_ADPCTRL;
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u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
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u32 val;
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2015-11-30 09:44:31 +08:00
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2019-04-11 18:27:35 +08:00
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dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
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2021-07-28 02:55:24 +08:00
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if (ch->soc_no_adp_ctrl) {
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vbus_ctrl_reg = USB2_VBCTRL;
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vbus_ctrl_val = USB2_VBCTRL_VBOUT;
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}
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val = readl(usb2_base + vbus_ctrl_reg);
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2015-11-30 09:44:31 +08:00
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if (vbus)
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2021-07-28 02:55:24 +08:00
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val |= vbus_ctrl_val;
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2015-11-30 09:44:31 +08:00
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else
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2021-07-28 02:55:24 +08:00
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val &= ~vbus_ctrl_val;
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writel(val, usb2_base + vbus_ctrl_reg);
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2015-11-30 09:44:31 +08:00
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}
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2018-09-21 19:53:21 +08:00
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static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
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{
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void __iomem *usb2_base = ch->base;
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u32 val = readl(usb2_base + USB2_OBINTEN);
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2018-09-21 19:53:23 +08:00
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if (ch->uses_otg_pins && enable)
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2021-07-28 02:55:24 +08:00
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val |= ch->obint_enable_bits;
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2018-09-21 19:53:21 +08:00
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else
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2021-07-28 02:55:24 +08:00
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val &= ~ch->obint_enable_bits;
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2018-09-21 19:53:21 +08:00
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writel(val, usb2_base + USB2_OBINTEN);
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}
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2015-11-30 09:44:31 +08:00
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static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
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{
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rcar_gen3_set_linectrl(ch, 1, 1);
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rcar_gen3_set_host_mode(ch, 1);
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rcar_gen3_enable_vbus_ctrl(ch, 1);
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2016-04-29 16:52:25 +08:00
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2016-06-27 14:36:53 +08:00
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ch->extcon_host = true;
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schedule_work(&ch->work);
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2015-11-30 09:44:31 +08:00
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}
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static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
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{
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rcar_gen3_set_linectrl(ch, 0, 1);
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rcar_gen3_set_host_mode(ch, 0);
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rcar_gen3_enable_vbus_ctrl(ch, 0);
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2016-04-29 16:52:25 +08:00
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2016-06-27 14:36:53 +08:00
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ch->extcon_host = false;
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schedule_work(&ch->work);
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2015-11-30 09:44:31 +08:00
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}
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2016-11-09 10:30:25 +08:00
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static void rcar_gen3_init_for_b_host(struct rcar_gen3_chan *ch)
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{
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void __iomem *usb2_base = ch->base;
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u32 val;
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val = readl(usb2_base + USB2_LINECTRL1);
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writel(val | USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
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rcar_gen3_set_linectrl(ch, 1, 1);
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rcar_gen3_set_host_mode(ch, 1);
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rcar_gen3_enable_vbus_ctrl(ch, 0);
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val = readl(usb2_base + USB2_LINECTRL1);
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writel(val & ~USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
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}
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static void rcar_gen3_init_for_a_peri(struct rcar_gen3_chan *ch)
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{
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rcar_gen3_set_linectrl(ch, 0, 1);
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rcar_gen3_set_host_mode(ch, 0);
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rcar_gen3_enable_vbus_ctrl(ch, 1);
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}
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static void rcar_gen3_init_from_a_peri_to_a_host(struct rcar_gen3_chan *ch)
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{
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2018-09-21 19:53:21 +08:00
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rcar_gen3_control_otg_irq(ch, 0);
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2016-11-09 10:30:25 +08:00
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2018-09-21 19:53:18 +08:00
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rcar_gen3_enable_vbus_ctrl(ch, 1);
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2016-11-09 10:30:25 +08:00
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rcar_gen3_init_for_host(ch);
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2018-09-21 19:53:21 +08:00
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rcar_gen3_control_otg_irq(ch, 1);
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2016-11-09 10:30:25 +08:00
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}
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2015-11-30 09:44:31 +08:00
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static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
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{
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2018-09-21 19:53:23 +08:00
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if (!ch->uses_otg_pins)
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return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
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2021-07-28 02:55:24 +08:00
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if (ch->soc_no_adp_ctrl)
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return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
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2016-03-03 18:09:04 +08:00
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return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
|
2015-11-30 09:44:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
2016-05-31 20:47:17 +08:00
|
|
|
if (!rcar_gen3_check_id(ch))
|
2015-11-30 09:44:31 +08:00
|
|
|
rcar_gen3_init_for_host(ch);
|
|
|
|
else
|
|
|
|
rcar_gen3_init_for_peri(ch);
|
|
|
|
}
|
|
|
|
|
2016-11-09 10:30:25 +08:00
|
|
|
static bool rcar_gen3_is_host(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
|
|
|
return !(readl(ch->base + USB2_COMMCTRL) & USB2_COMMCTRL_OTG_PERI);
|
|
|
|
}
|
|
|
|
|
2017-10-12 14:34:46 +08:00
|
|
|
static enum phy_mode rcar_gen3_get_phy_mode(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
|
|
|
if (rcar_gen3_is_host(ch))
|
|
|
|
return PHY_MODE_USB_HOST;
|
|
|
|
|
|
|
|
return PHY_MODE_USB_DEVICE;
|
|
|
|
}
|
|
|
|
|
2019-04-11 18:27:36 +08:00
|
|
|
static bool rcar_gen3_is_any_rphy_initialized(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_OF_PHYS; i++) {
|
|
|
|
if (ch->rphys[i].initialized)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool rcar_gen3_needs_init_otg(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_OF_PHYS; i++) {
|
|
|
|
if (ch->rphys[i].otg_initialized)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool rcar_gen3_are_all_rphys_power_off(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_OF_PHYS; i++) {
|
|
|
|
if (ch->rphys[i].powered)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-11-09 10:30:25 +08:00
|
|
|
static ssize_t role_store(struct device *dev, struct device_attribute *attr,
|
|
|
|
const char *buf, size_t count)
|
|
|
|
{
|
|
|
|
struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
|
2017-10-12 14:34:46 +08:00
|
|
|
bool is_b_device;
|
|
|
|
enum phy_mode cur_mode, new_mode;
|
2016-11-09 10:30:25 +08:00
|
|
|
|
2019-04-11 18:27:36 +08:00
|
|
|
if (!ch->is_otg_channel || !rcar_gen3_is_any_rphy_initialized(ch))
|
2016-11-09 10:30:25 +08:00
|
|
|
return -EIO;
|
|
|
|
|
2019-10-07 15:55:10 +08:00
|
|
|
if (sysfs_streq(buf, "host"))
|
2017-10-12 14:34:46 +08:00
|
|
|
new_mode = PHY_MODE_USB_HOST;
|
2019-10-07 15:55:10 +08:00
|
|
|
else if (sysfs_streq(buf, "peripheral"))
|
2017-10-12 14:34:46 +08:00
|
|
|
new_mode = PHY_MODE_USB_DEVICE;
|
2016-11-09 10:30:25 +08:00
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-10-12 14:34:46 +08:00
|
|
|
/* is_b_device: true is B-Device. false is A-Device. */
|
|
|
|
is_b_device = rcar_gen3_check_id(ch);
|
|
|
|
cur_mode = rcar_gen3_get_phy_mode(ch);
|
|
|
|
|
2016-11-09 10:30:25 +08:00
|
|
|
/* If current and new mode is the same, this returns the error */
|
2017-10-12 14:34:46 +08:00
|
|
|
if (cur_mode == new_mode)
|
2016-11-09 10:30:25 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2017-10-12 14:34:46 +08:00
|
|
|
if (new_mode == PHY_MODE_USB_HOST) { /* And is_host must be false */
|
2016-11-09 10:30:25 +08:00
|
|
|
if (!is_b_device) /* A-Peripheral */
|
|
|
|
rcar_gen3_init_from_a_peri_to_a_host(ch);
|
|
|
|
else /* B-Peripheral */
|
|
|
|
rcar_gen3_init_for_b_host(ch);
|
|
|
|
} else { /* And is_host must be true */
|
|
|
|
if (!is_b_device) /* A-Host */
|
|
|
|
rcar_gen3_init_for_a_peri(ch);
|
|
|
|
else /* B-Host */
|
|
|
|
rcar_gen3_init_for_peri(ch);
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t role_show(struct device *dev, struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
|
|
|
|
|
2019-04-11 18:27:36 +08:00
|
|
|
if (!ch->is_otg_channel || !rcar_gen3_is_any_rphy_initialized(ch))
|
2016-11-09 10:30:25 +08:00
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
return sprintf(buf, "%s\n", rcar_gen3_is_host(ch) ? "host" :
|
|
|
|
"peripheral");
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(role);
|
|
|
|
|
2015-11-30 09:44:31 +08:00
|
|
|
static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
|
|
|
|
{
|
2016-03-03 18:09:04 +08:00
|
|
|
void __iomem *usb2_base = ch->base;
|
2015-11-30 09:44:31 +08:00
|
|
|
u32 val;
|
|
|
|
|
2018-11-30 15:00:57 +08:00
|
|
|
/* Should not use functions of read-modify-write a register */
|
|
|
|
val = readl(usb2_base + USB2_LINECTRL1);
|
|
|
|
val = (val & ~USB2_LINECTRL1_DP_RPD) | USB2_LINECTRL1_DPRPD_EN |
|
|
|
|
USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
|
|
|
|
writel(val, usb2_base + USB2_LINECTRL1);
|
|
|
|
|
2021-07-28 02:55:24 +08:00
|
|
|
if (!ch->soc_no_adp_ctrl) {
|
|
|
|
val = readl(usb2_base + USB2_VBCTRL);
|
|
|
|
val &= ~USB2_VBCTRL_OCCLREN;
|
|
|
|
writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
|
|
|
|
val = readl(usb2_base + USB2_ADPCTRL);
|
|
|
|
writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
|
|
|
|
}
|
2018-11-30 15:00:57 +08:00
|
|
|
msleep(20);
|
|
|
|
|
|
|
|
writel(0xffffffff, usb2_base + USB2_OBINTSTA);
|
2021-07-28 02:55:24 +08:00
|
|
|
writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
|
2015-11-30 09:44:31 +08:00
|
|
|
|
|
|
|
rcar_gen3_device_recognition(ch);
|
|
|
|
}
|
|
|
|
|
2020-07-17 19:44:56 +08:00
|
|
|
static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
|
|
|
|
{
|
|
|
|
struct rcar_gen3_chan *ch = _ch;
|
|
|
|
void __iomem *usb2_base = ch->base;
|
|
|
|
u32 status = readl(usb2_base + USB2_OBINTSTA);
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
2021-07-28 02:55:24 +08:00
|
|
|
if (status & ch->obint_enable_bits) {
|
2020-07-17 19:44:56 +08:00
|
|
|
dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
|
2021-07-28 02:55:24 +08:00
|
|
|
writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
|
2020-07-17 19:44:56 +08:00
|
|
|
rcar_gen3_device_recognition(ch);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-11-30 09:44:30 +08:00
|
|
|
static int rcar_gen3_phy_usb2_init(struct phy *p)
|
|
|
|
{
|
2019-04-11 18:27:36 +08:00
|
|
|
struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
|
|
|
|
struct rcar_gen3_chan *channel = rphy->ch;
|
2016-03-03 18:09:04 +08:00
|
|
|
void __iomem *usb2_base = channel->base;
|
2019-04-11 18:27:36 +08:00
|
|
|
u32 val;
|
2020-07-17 19:44:56 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!rcar_gen3_is_any_rphy_initialized(channel) && channel->irq >= 0) {
|
|
|
|
INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work);
|
|
|
|
ret = request_irq(channel->irq, rcar_gen3_phy_usb2_irq,
|
|
|
|
IRQF_SHARED, dev_name(channel->dev), channel);
|
2020-07-17 19:44:57 +08:00
|
|
|
if (ret < 0) {
|
2020-07-17 19:44:56 +08:00
|
|
|
dev_err(channel->dev, "No irq handler (%d)\n", channel->irq);
|
2020-07-17 19:44:57 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2020-07-17 19:44:56 +08:00
|
|
|
}
|
2015-11-30 09:44:30 +08:00
|
|
|
|
|
|
|
/* Initialize USB2 part */
|
2019-04-11 18:27:36 +08:00
|
|
|
val = readl(usb2_base + USB2_INT_ENABLE);
|
|
|
|
val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits;
|
|
|
|
writel(val, usb2_base + USB2_INT_ENABLE);
|
2015-11-30 09:44:30 +08:00
|
|
|
writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
|
|
|
|
writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
|
|
|
|
|
2016-01-07 17:16:44 +08:00
|
|
|
/* Initialize otg part */
|
2019-04-11 18:27:36 +08:00
|
|
|
if (channel->is_otg_channel) {
|
|
|
|
if (rcar_gen3_needs_init_otg(channel))
|
|
|
|
rcar_gen3_init_otg(channel);
|
|
|
|
rphy->otg_initialized = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
rphy->initialized = true;
|
2015-11-30 09:44:30 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rcar_gen3_phy_usb2_exit(struct phy *p)
|
|
|
|
{
|
2019-04-11 18:27:36 +08:00
|
|
|
struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
|
|
|
|
struct rcar_gen3_chan *channel = rphy->ch;
|
|
|
|
void __iomem *usb2_base = channel->base;
|
|
|
|
u32 val;
|
2015-11-30 09:44:30 +08:00
|
|
|
|
2019-04-11 18:27:36 +08:00
|
|
|
rphy->initialized = false;
|
|
|
|
|
|
|
|
if (channel->is_otg_channel)
|
|
|
|
rphy->otg_initialized = false;
|
|
|
|
|
|
|
|
val = readl(usb2_base + USB2_INT_ENABLE);
|
|
|
|
val &= ~rphy->int_enable_bits;
|
|
|
|
if (!rcar_gen3_is_any_rphy_initialized(channel))
|
|
|
|
val &= ~USB2_INT_ENABLE_UCOM_INTEN;
|
|
|
|
writel(val, usb2_base + USB2_INT_ENABLE);
|
2015-11-30 09:44:30 +08:00
|
|
|
|
2020-07-17 19:44:56 +08:00
|
|
|
if (channel->irq >= 0 && !rcar_gen3_is_any_rphy_initialized(channel))
|
|
|
|
free_irq(channel->irq, channel);
|
|
|
|
|
2015-11-30 09:44:30 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rcar_gen3_phy_usb2_power_on(struct phy *p)
|
|
|
|
{
|
2019-04-11 18:27:36 +08:00
|
|
|
struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
|
|
|
|
struct rcar_gen3_chan *channel = rphy->ch;
|
2016-03-03 18:09:04 +08:00
|
|
|
void __iomem *usb2_base = channel->base;
|
2015-11-30 09:44:30 +08:00
|
|
|
u32 val;
|
2019-06-10 14:23:55 +08:00
|
|
|
int ret = 0;
|
2016-03-03 18:09:05 +08:00
|
|
|
|
2019-06-10 14:23:55 +08:00
|
|
|
mutex_lock(&channel->lock);
|
2019-04-11 18:27:36 +08:00
|
|
|
if (!rcar_gen3_are_all_rphys_power_off(channel))
|
2019-06-10 14:23:55 +08:00
|
|
|
goto out;
|
2019-04-11 18:27:36 +08:00
|
|
|
|
2016-03-03 18:09:05 +08:00
|
|
|
if (channel->vbus) {
|
|
|
|
ret = regulator_enable(channel->vbus);
|
|
|
|
if (ret)
|
2019-06-10 14:23:55 +08:00
|
|
|
goto out;
|
2016-03-03 18:09:05 +08:00
|
|
|
}
|
2015-11-30 09:44:30 +08:00
|
|
|
|
|
|
|
val = readl(usb2_base + USB2_USBCTR);
|
|
|
|
val |= USB2_USBCTR_PLL_RST;
|
|
|
|
writel(val, usb2_base + USB2_USBCTR);
|
|
|
|
val &= ~USB2_USBCTR_PLL_RST;
|
|
|
|
writel(val, usb2_base + USB2_USBCTR);
|
|
|
|
|
2019-06-10 14:23:55 +08:00
|
|
|
out:
|
|
|
|
/* The powered flag should be set for any other phys anyway */
|
2019-04-11 18:27:36 +08:00
|
|
|
rphy->powered = true;
|
2019-06-10 14:23:55 +08:00
|
|
|
mutex_unlock(&channel->lock);
|
2019-04-11 18:27:36 +08:00
|
|
|
|
2015-11-30 09:44:30 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-03 18:09:05 +08:00
|
|
|
static int rcar_gen3_phy_usb2_power_off(struct phy *p)
|
|
|
|
{
|
2019-04-11 18:27:36 +08:00
|
|
|
struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
|
|
|
|
struct rcar_gen3_chan *channel = rphy->ch;
|
2016-03-03 18:09:05 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
2019-06-10 14:23:55 +08:00
|
|
|
mutex_lock(&channel->lock);
|
2019-04-11 18:27:36 +08:00
|
|
|
rphy->powered = false;
|
|
|
|
|
|
|
|
if (!rcar_gen3_are_all_rphys_power_off(channel))
|
2019-06-10 14:23:55 +08:00
|
|
|
goto out;
|
2019-04-11 18:27:36 +08:00
|
|
|
|
2016-03-03 18:09:05 +08:00
|
|
|
if (channel->vbus)
|
|
|
|
ret = regulator_disable(channel->vbus);
|
|
|
|
|
2019-06-10 14:23:55 +08:00
|
|
|
out:
|
|
|
|
mutex_unlock(&channel->lock);
|
|
|
|
|
2016-03-03 18:09:05 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-01-08 18:35:56 +08:00
|
|
|
static const struct phy_ops rcar_gen3_phy_usb2_ops = {
|
2015-11-30 09:44:30 +08:00
|
|
|
.init = rcar_gen3_phy_usb2_init,
|
|
|
|
.exit = rcar_gen3_phy_usb2_exit,
|
|
|
|
.power_on = rcar_gen3_phy_usb2_power_on,
|
2016-03-03 18:09:05 +08:00
|
|
|
.power_off = rcar_gen3_phy_usb2_power_off,
|
2015-11-30 09:44:30 +08:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
2019-04-10 22:48:41 +08:00
|
|
|
static const struct phy_ops rz_g1c_phy_usb2_ops = {
|
|
|
|
.init = rcar_gen3_phy_usb2_init,
|
|
|
|
.exit = rcar_gen3_phy_usb2_exit,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
2021-07-28 02:55:24 +08:00
|
|
|
static const struct rcar_gen3_phy_drv_data rcar_gen3_phy_usb2_data = {
|
|
|
|
.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
|
|
|
|
.no_adp_ctrl = false,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct rcar_gen3_phy_drv_data rz_g1c_phy_usb2_data = {
|
|
|
|
.phy_usb2_ops = &rz_g1c_phy_usb2_ops,
|
|
|
|
.no_adp_ctrl = false,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
|
|
|
|
.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
|
|
|
|
.no_adp_ctrl = true,
|
|
|
|
};
|
|
|
|
|
2015-11-30 09:44:30 +08:00
|
|
|
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
|
2019-04-10 22:48:41 +08:00
|
|
|
{
|
|
|
|
.compatible = "renesas,usb2-phy-r8a77470",
|
2021-07-28 02:55:24 +08:00
|
|
|
.data = &rz_g1c_phy_usb2_data,
|
2019-04-10 22:48:41 +08:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "renesas,usb2-phy-r8a7795",
|
2021-07-28 02:55:24 +08:00
|
|
|
.data = &rcar_gen3_phy_usb2_data,
|
2019-04-10 22:48:41 +08:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "renesas,usb2-phy-r8a7796",
|
2021-07-28 02:55:24 +08:00
|
|
|
.data = &rcar_gen3_phy_usb2_data,
|
2019-04-10 22:48:41 +08:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "renesas,usb2-phy-r8a77965",
|
2021-07-28 02:55:24 +08:00
|
|
|
.data = &rcar_gen3_phy_usb2_data,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "renesas,rzg2l-usb2-phy",
|
|
|
|
.data = &rz_g2l_phy_usb2_data,
|
2019-04-10 22:48:41 +08:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "renesas,rcar-gen3-usb2-phy",
|
2021-07-28 02:55:24 +08:00
|
|
|
.data = &rcar_gen3_phy_usb2_data,
|
2019-04-10 22:48:41 +08:00
|
|
|
},
|
|
|
|
{ /* sentinel */ },
|
2015-11-30 09:44:30 +08:00
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
|
|
|
|
|
2016-04-29 16:52:25 +08:00
|
|
|
static const unsigned int rcar_gen3_phy_cable[] = {
|
|
|
|
EXTCON_USB,
|
|
|
|
EXTCON_USB_HOST,
|
|
|
|
EXTCON_NONE,
|
|
|
|
};
|
|
|
|
|
2019-04-11 18:27:36 +08:00
|
|
|
static struct phy *rcar_gen3_phy_usb2_xlate(struct device *dev,
|
|
|
|
struct of_phandle_args *args)
|
|
|
|
{
|
|
|
|
struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (args->args_count == 0) /* For old version dts */
|
|
|
|
return ch->rphys[PHY_INDEX_BOTH_HC].phy;
|
|
|
|
else if (args->args_count > 1) /* Prevent invalid args count */
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
if (args->args[0] >= NUM_OF_PHYS)
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
return ch->rphys[args->args[0]].phy;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
|
|
|
|
{
|
|
|
|
enum usb_dr_mode candidate = USB_DR_MODE_UNKNOWN;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If one of device nodes has other dr_mode except UNKNOWN,
|
|
|
|
* this function returns UNKNOWN. To achieve backward compatibility,
|
|
|
|
* this loop starts the index as 0.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < NUM_OF_PHYS; i++) {
|
|
|
|
enum usb_dr_mode mode = of_usb_get_dr_mode_by_phy(np, i);
|
|
|
|
|
|
|
|
if (mode != USB_DR_MODE_UNKNOWN) {
|
|
|
|
if (candidate == USB_DR_MODE_UNKNOWN)
|
|
|
|
candidate = mode;
|
|
|
|
else if (candidate != mode)
|
|
|
|
return USB_DR_MODE_UNKNOWN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return candidate;
|
|
|
|
}
|
|
|
|
|
2015-11-30 09:44:30 +08:00
|
|
|
static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
|
|
|
|
{
|
2021-07-28 02:55:24 +08:00
|
|
|
const struct rcar_gen3_phy_drv_data *phy_data;
|
2015-11-30 09:44:30 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct rcar_gen3_chan *channel;
|
|
|
|
struct phy_provider *provider;
|
2020-07-17 19:44:56 +08:00
|
|
|
int ret = 0, i;
|
2015-11-30 09:44:30 +08:00
|
|
|
|
|
|
|
if (!dev->of_node) {
|
|
|
|
dev_err(dev, "This driver needs device tree\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
|
|
|
|
if (!channel)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2020-11-06 14:08:45 +08:00
|
|
|
channel->base = devm_platform_ioremap_resource(pdev, 0);
|
2016-03-03 18:09:04 +08:00
|
|
|
if (IS_ERR(channel->base))
|
|
|
|
return PTR_ERR(channel->base);
|
2015-11-30 09:44:30 +08:00
|
|
|
|
2021-07-28 02:55:24 +08:00
|
|
|
channel->obint_enable_bits = USB2_OBINT_BITS;
|
2020-07-17 19:44:56 +08:00
|
|
|
/* get irq number here and request_irq for OTG in phy_init */
|
|
|
|
channel->irq = platform_get_irq_optional(pdev, 0);
|
2019-04-11 18:27:36 +08:00
|
|
|
channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
|
2018-09-21 19:53:22 +08:00
|
|
|
if (channel->dr_mode != USB_DR_MODE_UNKNOWN) {
|
2017-10-12 14:34:45 +08:00
|
|
|
int ret;
|
|
|
|
|
2018-09-21 19:53:24 +08:00
|
|
|
channel->is_otg_channel = true;
|
2018-09-21 19:53:20 +08:00
|
|
|
channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
|
|
|
|
"renesas,no-otg-pins");
|
2016-04-29 16:52:25 +08:00
|
|
|
channel->extcon = devm_extcon_dev_allocate(dev,
|
|
|
|
rcar_gen3_phy_cable);
|
|
|
|
if (IS_ERR(channel->extcon))
|
|
|
|
return PTR_ERR(channel->extcon);
|
|
|
|
|
|
|
|
ret = devm_extcon_dev_register(dev, channel->extcon);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "Failed to register extcon\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2015-11-30 09:44:30 +08:00
|
|
|
}
|
|
|
|
|
2017-03-14 07:37:40 +08:00
|
|
|
/*
|
|
|
|
* devm_phy_create() will call pm_runtime_enable(&phy->dev);
|
|
|
|
* And then, phy-core will manage runtime pm for this device.
|
|
|
|
*/
|
|
|
|
pm_runtime_enable(dev);
|
2021-07-28 02:55:24 +08:00
|
|
|
|
|
|
|
phy_data = of_device_get_match_data(dev);
|
|
|
|
if (!phy_data) {
|
2020-11-26 10:44:12 +08:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
2019-04-10 22:48:41 +08:00
|
|
|
|
2021-07-28 02:55:24 +08:00
|
|
|
channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl;
|
|
|
|
if (phy_data->no_adp_ctrl)
|
|
|
|
channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
|
|
|
|
|
2019-06-10 14:23:55 +08:00
|
|
|
mutex_init(&channel->lock);
|
2019-04-11 18:27:36 +08:00
|
|
|
for (i = 0; i < NUM_OF_PHYS; i++) {
|
|
|
|
channel->rphys[i].phy = devm_phy_create(dev, NULL,
|
2021-07-28 02:55:24 +08:00
|
|
|
phy_data->phy_usb2_ops);
|
2019-04-11 18:27:36 +08:00
|
|
|
if (IS_ERR(channel->rphys[i].phy)) {
|
|
|
|
dev_err(dev, "Failed to create USB2 PHY\n");
|
|
|
|
ret = PTR_ERR(channel->rphys[i].phy);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
channel->rphys[i].ch = channel;
|
|
|
|
channel->rphys[i].int_enable_bits = rcar_gen3_int_enable[i];
|
|
|
|
phy_set_drvdata(channel->rphys[i].phy, &channel->rphys[i]);
|
2015-11-30 09:44:30 +08:00
|
|
|
}
|
|
|
|
|
2016-03-03 18:09:05 +08:00
|
|
|
channel->vbus = devm_regulator_get_optional(dev, "vbus");
|
|
|
|
if (IS_ERR(channel->vbus)) {
|
2017-03-14 07:37:40 +08:00
|
|
|
if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) {
|
|
|
|
ret = PTR_ERR(channel->vbus);
|
|
|
|
goto error;
|
|
|
|
}
|
2016-03-03 18:09:05 +08:00
|
|
|
channel->vbus = NULL;
|
|
|
|
}
|
|
|
|
|
2016-11-09 10:30:25 +08:00
|
|
|
platform_set_drvdata(pdev, channel);
|
2019-04-11 18:27:35 +08:00
|
|
|
channel->dev = dev;
|
2015-11-30 09:44:30 +08:00
|
|
|
|
2019-04-11 18:27:36 +08:00
|
|
|
provider = devm_of_phy_provider_register(dev, rcar_gen3_phy_usb2_xlate);
|
2016-11-09 10:30:25 +08:00
|
|
|
if (IS_ERR(provider)) {
|
2015-11-30 09:44:30 +08:00
|
|
|
dev_err(dev, "Failed to register PHY provider\n");
|
2017-03-14 07:37:40 +08:00
|
|
|
ret = PTR_ERR(provider);
|
|
|
|
goto error;
|
2018-09-21 19:53:24 +08:00
|
|
|
} else if (channel->is_otg_channel) {
|
2016-11-09 10:30:25 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = device_create_file(dev, &dev_attr_role);
|
|
|
|
if (ret < 0)
|
2017-03-14 07:37:40 +08:00
|
|
|
goto error;
|
2016-11-09 10:30:25 +08:00
|
|
|
}
|
2015-11-30 09:44:30 +08:00
|
|
|
|
2017-03-14 07:37:40 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
|
|
|
|
return ret;
|
2015-11-30 09:44:30 +08:00
|
|
|
}
|
|
|
|
|
2023-03-07 19:58:45 +08:00
|
|
|
static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
|
2016-11-09 10:30:25 +08:00
|
|
|
{
|
|
|
|
struct rcar_gen3_chan *channel = platform_get_drvdata(pdev);
|
|
|
|
|
2018-09-21 19:53:24 +08:00
|
|
|
if (channel->is_otg_channel)
|
2016-11-09 10:30:25 +08:00
|
|
|
device_remove_file(&pdev->dev, &dev_attr_role);
|
|
|
|
|
2017-03-14 07:37:40 +08:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2016-11-09 10:30:25 +08:00
|
|
|
};
|
|
|
|
|
2015-11-30 09:44:30 +08:00
|
|
|
static struct platform_driver rcar_gen3_phy_usb2_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "phy_rcar_gen3_usb2",
|
|
|
|
.of_match_table = rcar_gen3_phy_usb2_match_table,
|
|
|
|
},
|
|
|
|
.probe = rcar_gen3_phy_usb2_probe,
|
2023-03-07 19:58:45 +08:00
|
|
|
.remove_new = rcar_gen3_phy_usb2_remove,
|
2015-11-30 09:44:30 +08:00
|
|
|
};
|
|
|
|
module_platform_driver(rcar_gen3_phy_usb2_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
|
|
|
|
MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
|