277 lines
7.4 KiB
C
277 lines
7.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* GPADC driver for sunxi platforms (D1, T113-S3 and R329)
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* Copyright (c) 2023 Maksim Kiselev <bigunclemax@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/reset.h>
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#include <linux/iio/iio.h>
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#define SUN20I_GPADC_DRIVER_NAME "sun20i-gpadc"
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/* Register map definition */
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#define SUN20I_GPADC_SR 0x00
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#define SUN20I_GPADC_CTRL 0x04
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#define SUN20I_GPADC_CS_EN 0x08
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#define SUN20I_GPADC_FIFO_INTC 0x0c
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#define SUN20I_GPADC_FIFO_INTS 0x10
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#define SUN20I_GPADC_FIFO_DATA 0X14
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#define SUN20I_GPADC_CB_DATA 0X18
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#define SUN20I_GPADC_DATAL_INTC 0x20
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#define SUN20I_GPADC_DATAH_INTC 0x24
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#define SUN20I_GPADC_DATA_INTC 0x28
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#define SUN20I_GPADC_DATAL_INTS 0x30
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#define SUN20I_GPADC_DATAH_INTS 0x34
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#define SUN20I_GPADC_DATA_INTS 0x38
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#define SUN20I_GPADC_CH_CMP_DATA(x) (0x40 + (x) * 4)
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#define SUN20I_GPADC_CH_DATA(x) (0x80 + (x) * 4)
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#define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK BIT(23)
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#define SUN20I_GPADC_CTRL_WORK_MODE_MASK GENMASK(19, 18)
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#define SUN20I_GPADC_CTRL_ADC_EN_MASK BIT(16)
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#define SUN20I_GPADC_CS_EN_ADC_CH(x) BIT(x)
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#define SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(x) BIT(x)
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#define SUN20I_GPADC_WORK_MODE_SINGLE 0
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struct sun20i_gpadc_iio {
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void __iomem *regs;
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struct completion completion;
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int last_channel;
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/*
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* Lock to protect the device state during a potential concurrent
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* read access from userspace. Reading a raw value requires a sequence
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* of register writes, then a wait for a completion callback,
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* and finally a register read, during which userspace could issue
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* another read request. This lock protects a read access from
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* ocurring before another one has finished.
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*/
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struct mutex lock;
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};
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static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info,
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struct iio_chan_spec const *chan, int *val)
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{
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u32 ctrl;
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int ret = IIO_VAL_INT;
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mutex_lock(&info->lock);
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reinit_completion(&info->completion);
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if (info->last_channel != chan->channel) {
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info->last_channel = chan->channel;
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/* enable the analog input channel */
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writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel),
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info->regs + SUN20I_GPADC_CS_EN);
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/* enable the data irq for input channel */
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writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel),
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info->regs + SUN20I_GPADC_DATA_INTC);
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}
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/* enable the ADC function */
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ctrl = readl(info->regs + SUN20I_GPADC_CTRL);
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ctrl |= FIELD_PREP(SUN20I_GPADC_CTRL_ADC_EN_MASK, 1);
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writel(ctrl, info->regs + SUN20I_GPADC_CTRL);
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/*
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* According to the datasheet maximum acquire time(TACQ) can be
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* (65535+1)/24Mhz and conversion time(CONV_TIME) is always constant
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* and equal to 14/24Mhz, so (TACQ+CONV_TIME) <= 2.73125ms.
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* A 10ms delay should be enough to make sure an interrupt occurs in
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* normal conditions. If it doesn't occur, then there is a timeout.
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*/
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if (!wait_for_completion_timeout(&info->completion, msecs_to_jiffies(10))) {
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ret = -ETIMEDOUT;
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goto err_unlock;
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}
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/* read the ADC data */
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*val = readl(info->regs + SUN20I_GPADC_CH_DATA(chan->channel));
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err_unlock:
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mutex_unlock(&info->lock);
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return ret;
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}
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static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val,
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int *val2, long mask)
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{
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struct sun20i_gpadc_iio *info = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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return sun20i_gpadc_adc_read(info, chan, val);
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case IIO_CHAN_INFO_SCALE:
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/* value in mv = 1800mV / 4096 raw */
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*val = 1800;
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*val2 = 12;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data)
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{
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struct sun20i_gpadc_iio *info = data;
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/* clear data interrupt status register */
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writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS);
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complete(&info->completion);
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return IRQ_HANDLED;
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}
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static const struct iio_info sun20i_gpadc_iio_info = {
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.read_raw = sun20i_gpadc_read_raw,
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};
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static void sun20i_gpadc_reset_assert(void *data)
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{
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struct reset_control *rst = data;
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reset_control_assert(rst);
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}
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static int sun20i_gpadc_alloc_channels(struct iio_dev *indio_dev,
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struct device *dev)
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{
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unsigned int channel;
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int num_channels, i, ret;
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struct iio_chan_spec *channels;
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struct fwnode_handle *node;
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num_channels = device_get_child_node_count(dev);
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if (num_channels == 0)
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return dev_err_probe(dev, -ENODEV, "no channel children\n");
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channels = devm_kcalloc(dev, num_channels, sizeof(*channels),
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GFP_KERNEL);
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if (!channels)
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return -ENOMEM;
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i = 0;
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device_for_each_child_node(dev, node) {
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ret = fwnode_property_read_u32(node, "reg", &channel);
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if (ret) {
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fwnode_handle_put(node);
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return dev_err_probe(dev, ret, "invalid channel number\n");
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}
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channels[i].type = IIO_VOLTAGE;
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channels[i].indexed = 1;
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channels[i].channel = channel;
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channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
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i++;
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}
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indio_dev->channels = channels;
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indio_dev->num_channels = num_channels;
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return 0;
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}
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static int sun20i_gpadc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct iio_dev *indio_dev;
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struct sun20i_gpadc_iio *info;
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struct reset_control *rst;
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struct clk *clk;
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int irq;
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int ret;
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indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
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if (!indio_dev)
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return -ENOMEM;
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info = iio_priv(indio_dev);
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info->last_channel = -1;
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mutex_init(&info->lock);
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init_completion(&info->completion);
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ret = sun20i_gpadc_alloc_channels(indio_dev, dev);
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if (ret)
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return ret;
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indio_dev->info = &sun20i_gpadc_iio_info;
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indio_dev->name = SUN20I_GPADC_DRIVER_NAME;
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info->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(info->regs))
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return PTR_ERR(info->regs);
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clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n");
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rst = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(rst))
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return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
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ret = reset_control_deassert(rst);
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if (ret)
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return dev_err_probe(dev, ret, "failed to deassert reset\n");
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ret = devm_add_action_or_reset(dev, sun20i_gpadc_reset_assert, rst);
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if (ret)
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return ret;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(dev, irq, sun20i_gpadc_irq_handler, 0,
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dev_name(dev), info);
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if (ret)
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return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq);
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writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) |
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FIELD_PREP(SUN20I_GPADC_CTRL_WORK_MODE_MASK, SUN20I_GPADC_WORK_MODE_SINGLE),
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info->regs + SUN20I_GPADC_CTRL);
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ret = devm_iio_device_register(dev, indio_dev);
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if (ret)
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return dev_err_probe(dev, ret, "could not register the device\n");
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return 0;
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}
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static const struct of_device_id sun20i_gpadc_of_id[] = {
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{ .compatible = "allwinner,sun20i-d1-gpadc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id);
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static struct platform_driver sun20i_gpadc_driver = {
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.driver = {
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.name = SUN20I_GPADC_DRIVER_NAME,
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.of_match_table = sun20i_gpadc_of_id,
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},
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.probe = sun20i_gpadc_probe,
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};
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module_platform_driver(sun20i_gpadc_driver);
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MODULE_DESCRIPTION("ADC driver for sunxi platforms");
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MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>");
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MODULE_LICENSE("GPL");
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