2018-12-13 23:42:54 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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2021-04-23 11:33:33 +08:00
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* Copyright 2018-2021 NXP
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2018-12-13 23:42:54 +08:00
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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2019-02-26 13:17:36 +08:00
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <linux/arm-smccc.h>
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2021-04-23 11:33:33 +08:00
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#include <linux/bsearch.h>
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2018-12-13 23:42:54 +08:00
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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2023-07-18 22:31:43 +08:00
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#include <linux/of.h>
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2020-07-29 16:00:10 +08:00
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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2020-07-29 16:00:13 +08:00
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#include <linux/pm_runtime.h>
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2018-12-13 23:42:54 +08:00
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#include <linux/slab.h>
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#include "clk-scu.h"
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2019-02-26 13:17:36 +08:00
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#define IMX_SIP_CPUFREQ 0xC2000001
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#define IMX_SIP_SET_CPUFREQ 0x00
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2018-12-13 23:42:54 +08:00
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static struct imx_sc_ipc *ccm_ipc_handle;
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2020-11-04 19:19:31 +08:00
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static struct device_node *pd_np;
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2020-10-30 23:37:33 +08:00
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static struct platform_driver imx_clk_scu_driver;
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2021-04-23 11:33:33 +08:00
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static const struct imx_clk_scu_rsrc_table *rsrc_table;
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2020-07-29 16:00:10 +08:00
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struct imx_scu_clk_node {
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const char *name;
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u32 rsrc;
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u8 clk_type;
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const char * const *parents;
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int num_parents;
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struct clk_hw *hw;
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struct list_head node;
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};
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struct list_head imx_scu_clks[IMX_SC_R_LAST];
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2018-12-13 23:42:54 +08:00
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/*
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* struct clk_scu - Description of one SCU clock
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* @hw: the common clk_hw
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* @rsrc_id: resource ID of this SCU clock
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* @clk_type: type of this clock resource
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*/
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struct clk_scu {
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struct clk_hw hw;
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u16 rsrc_id;
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u8 clk_type;
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2020-07-29 16:00:14 +08:00
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/* for state save&restore */
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2021-06-04 17:09:42 +08:00
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struct clk_hw *parent;
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u8 parent_index;
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2020-07-29 16:00:14 +08:00
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bool is_enabled;
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u32 rate;
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2018-12-13 23:42:54 +08:00
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};
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2021-04-23 11:33:32 +08:00
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/*
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* struct clk_gpr_scu - Description of one SCU GPR clock
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* @hw: the common clk_hw
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* @rsrc_id: resource ID of this SCU clock
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* @gpr_id: GPR ID index to control the divider
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*/
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struct clk_gpr_scu {
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struct clk_hw hw;
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u16 rsrc_id;
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u8 gpr_id;
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u8 flags;
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bool gate_invert;
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};
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#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
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2018-12-13 23:42:54 +08:00
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/*
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* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
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* @hdr: SCU protocol header
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* @rate: rate to set
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* @resource: clock resource to set rate
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* @clk: clk type of this resource
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*
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* This structure describes the SCU protocol of clock rate set
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*/
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struct imx_sc_msg_req_set_clock_rate {
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struct imx_sc_rpc_msg hdr;
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__le32 rate;
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__le16 resource;
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u8 clk;
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2020-02-21 00:29:32 +08:00
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} __packed __aligned(4);
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2018-12-13 23:42:54 +08:00
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struct req_get_clock_rate {
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__le16 resource;
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u8 clk;
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2020-02-21 00:29:32 +08:00
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} __packed __aligned(4);
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2018-12-13 23:42:54 +08:00
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struct resp_get_clock_rate {
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__le32 rate;
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};
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/*
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* struct imx_sc_msg_get_clock_rate - clock get rate protocol
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* @hdr: SCU protocol header
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* @req: get rate request protocol
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* @resp: get rate response protocol
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*
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* This structure describes the SCU protocol of clock rate get
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*/
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struct imx_sc_msg_get_clock_rate {
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struct imx_sc_rpc_msg hdr;
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union {
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struct req_get_clock_rate req;
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struct resp_get_clock_rate resp;
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} data;
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};
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2019-01-30 21:39:15 +08:00
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/*
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* struct imx_sc_msg_get_clock_parent - clock get parent protocol
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* @hdr: SCU protocol header
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* @req: get parent request protocol
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* @resp: get parent response protocol
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*
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* This structure describes the SCU protocol of clock get parent
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*/
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struct imx_sc_msg_get_clock_parent {
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struct imx_sc_rpc_msg hdr;
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union {
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struct req_get_clock_parent {
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__le16 resource;
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u8 clk;
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2020-02-21 00:29:33 +08:00
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} __packed __aligned(4) req;
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2019-01-30 21:39:15 +08:00
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struct resp_get_clock_parent {
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u8 parent;
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} resp;
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} data;
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};
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/*
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* struct imx_sc_msg_set_clock_parent - clock set parent protocol
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* @hdr: SCU protocol header
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* @req: set parent request protocol
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*
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* This structure describes the SCU protocol of clock set parent
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*/
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struct imx_sc_msg_set_clock_parent {
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struct imx_sc_rpc_msg hdr;
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__le16 resource;
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u8 clk;
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u8 parent;
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} __packed;
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2018-12-13 23:42:54 +08:00
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/*
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* struct imx_sc_msg_req_clock_enable - clock gate protocol
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* @hdr: SCU protocol header
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* @resource: clock resource to gate
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* @clk: clk type of this resource
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* @enable: whether gate off the clock
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* @autog: HW auto gate enable
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*
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* This structure describes the SCU protocol of clock gate
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*/
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struct imx_sc_msg_req_clock_enable {
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struct imx_sc_rpc_msg hdr;
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__le16 resource;
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u8 clk;
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u8 enable;
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u8 autog;
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2020-02-21 00:29:32 +08:00
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} __packed __aligned(4);
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2018-12-13 23:42:54 +08:00
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static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_scu, hw);
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}
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2021-04-23 11:33:33 +08:00
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static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
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{
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return *(u32 *)rsrc - *(u32 *)rsrc_p;
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}
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static bool imx_scu_clk_is_valid(u32 rsrc_id)
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{
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void *p;
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if (!rsrc_table)
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return true;
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p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
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sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
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return p != NULL;
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}
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int imx_clk_scu_init(struct device_node *np,
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const struct imx_clk_scu_rsrc_table *data)
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2018-12-13 23:42:54 +08:00
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{
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2020-07-29 16:00:10 +08:00
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u32 clk_cells;
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int ret, i;
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ret = imx_scu_get_handle(&ccm_ipc_handle);
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if (ret)
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return ret;
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of_property_read_u32(np, "#clock-cells", &clk_cells);
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if (clk_cells == 2) {
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for (i = 0; i < IMX_SC_R_LAST; i++)
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INIT_LIST_HEAD(&imx_scu_clks[i]);
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2020-11-19 19:43:02 +08:00
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/* pd_np will be used to attach power domains later */
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2020-07-29 16:00:10 +08:00
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pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
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2020-11-19 19:43:02 +08:00
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if (!pd_np)
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return -EINVAL;
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2021-04-23 11:33:33 +08:00
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rsrc_table = data;
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2020-07-29 16:00:10 +08:00
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}
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2020-10-30 23:37:33 +08:00
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return platform_driver_register(&imx_clk_scu_driver);
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2018-12-13 23:42:54 +08:00
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}
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/*
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* clk_scu_recalc_rate - Get clock rate for a SCU clock
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* @hw: clock to get rate for
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* @parent_rate: parent rate provided by common clock framework, not used
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*
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* Gets the current clock rate of a SCU clock. Returns the current
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* clock rate, or zero in failure.
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*/
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static unsigned long clk_scu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct imx_sc_msg_get_clock_rate msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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int ret;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;
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hdr->size = 2;
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msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
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msg.data.req.clk = clk->clk_type;
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ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
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if (ret) {
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pr_err("%s: failed to get clock rate %d\n",
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clk_hw_get_name(hw), ret);
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return 0;
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}
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return le32_to_cpu(msg.data.resp.rate);
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}
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clk: imx: scu: Switch to determine_rate
The iMX SCU clocks implements a mux with a set_parent hook, but doesn't
provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. The round_rate()
implementation being shared with other clocks, it's not removed.
And if it was an oversight, the clock behaviour can be adjusted later
on.
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-58-971d5077e7d2@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-05-05 19:26:00 +08:00
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/*
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* clk_scu_determine_rate - Returns the closest rate for a SCU clock
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* @hw: clock to round rate for
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* @req: clock rate request
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*
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* Returns 0 on success, a negative error on failure
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*/
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static int clk_scu_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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/*
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* Assume we support all the requested rate and let the SCU firmware
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* to handle the left work
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*/
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return 0;
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}
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2018-12-13 23:42:54 +08:00
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/*
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* clk_scu_round_rate - Round clock rate for a SCU clock
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* @hw: clock to round rate for
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* @rate: rate to round
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* @parent_rate: parent rate provided by common clock framework, not used
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*
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* Returns the current clock rate, or zero in failure.
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*/
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static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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/*
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* Assume we support all the requested rate and let the SCU firmware
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* to handle the left work
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*/
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return rate;
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}
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2019-02-26 13:17:36 +08:00
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static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct arm_smccc_res res;
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unsigned long cluster_id;
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2021-06-04 17:09:39 +08:00
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if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)
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2019-02-26 13:17:36 +08:00
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cluster_id = 0;
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2021-06-04 17:09:40 +08:00
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else if (clk->rsrc_id == IMX_SC_R_A72)
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cluster_id = 1;
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2019-02-26 13:17:36 +08:00
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else
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return -EINVAL;
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/* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
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arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
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cluster_id, rate, 0, 0, 0, 0, &res);
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return 0;
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}
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2018-12-13 23:42:54 +08:00
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/*
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* clk_scu_set_rate - Set rate for a SCU clock
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* @hw: clock to change rate for
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* @rate: target rate for the clock
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* @parent_rate: rate of the clock parent, not used for SCU clocks
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*
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* Sets a clock frequency for a SCU clock. Returns the SCU
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* protocol status.
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|
|
*/
|
|
|
|
static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = to_clk_scu(hw);
|
|
|
|
struct imx_sc_msg_req_set_clock_rate msg;
|
|
|
|
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
|
|
|
|
|
|
|
hdr->ver = IMX_SC_RPC_VERSION;
|
|
|
|
hdr->svc = IMX_SC_RPC_SVC_PM;
|
|
|
|
hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
|
|
|
|
hdr->size = 3;
|
|
|
|
|
|
|
|
msg.rate = cpu_to_le32(rate);
|
|
|
|
msg.resource = cpu_to_le16(clk->rsrc_id);
|
|
|
|
msg.clk = clk->clk_type;
|
|
|
|
|
|
|
|
return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
|
|
|
|
}
|
|
|
|
|
2019-01-30 21:39:15 +08:00
|
|
|
static u8 clk_scu_get_parent(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = to_clk_scu(hw);
|
|
|
|
struct imx_sc_msg_get_clock_parent msg;
|
|
|
|
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
hdr->ver = IMX_SC_RPC_VERSION;
|
|
|
|
hdr->svc = IMX_SC_RPC_SVC_PM;
|
|
|
|
hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;
|
|
|
|
hdr->size = 2;
|
|
|
|
|
|
|
|
msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
|
|
|
|
msg.data.req.clk = clk->clk_type;
|
|
|
|
|
|
|
|
ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: failed to get clock parent %d\n",
|
|
|
|
clk_hw_get_name(hw), ret);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-06-04 17:09:42 +08:00
|
|
|
clk->parent_index = msg.data.resp.parent;
|
|
|
|
|
2019-01-30 21:39:15 +08:00
|
|
|
return msg.data.resp.parent;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = to_clk_scu(hw);
|
|
|
|
struct imx_sc_msg_set_clock_parent msg;
|
|
|
|
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
2021-06-04 17:09:42 +08:00
|
|
|
int ret;
|
2019-01-30 21:39:15 +08:00
|
|
|
|
|
|
|
hdr->ver = IMX_SC_RPC_VERSION;
|
|
|
|
hdr->svc = IMX_SC_RPC_SVC_PM;
|
|
|
|
hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;
|
|
|
|
hdr->size = 2;
|
|
|
|
|
|
|
|
msg.resource = cpu_to_le16(clk->rsrc_id);
|
|
|
|
msg.clk = clk->clk_type;
|
|
|
|
msg.parent = index;
|
|
|
|
|
2021-06-04 17:09:42 +08:00
|
|
|
ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: failed to set clock parent %d\n",
|
|
|
|
clk_hw_get_name(hw), ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
clk->parent_index = index;
|
|
|
|
|
|
|
|
return 0;
|
2019-01-30 21:39:15 +08:00
|
|
|
}
|
|
|
|
|
2018-12-13 23:42:54 +08:00
|
|
|
static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
|
|
|
|
u8 clk, bool enable, bool autog)
|
|
|
|
{
|
|
|
|
struct imx_sc_msg_req_clock_enable msg;
|
|
|
|
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
|
|
|
|
|
|
|
hdr->ver = IMX_SC_RPC_VERSION;
|
|
|
|
hdr->svc = IMX_SC_RPC_SVC_PM;
|
|
|
|
hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;
|
|
|
|
hdr->size = 3;
|
|
|
|
|
|
|
|
msg.resource = cpu_to_le16(resource);
|
|
|
|
msg.clk = clk;
|
|
|
|
msg.enable = enable;
|
|
|
|
msg.autog = autog;
|
|
|
|
|
|
|
|
return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* clk_scu_prepare - Enable a SCU clock
|
|
|
|
* @hw: clock to enable
|
|
|
|
*
|
|
|
|
* Enable the clock at the DSC slice level
|
|
|
|
*/
|
|
|
|
static int clk_scu_prepare(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = to_clk_scu(hw);
|
|
|
|
|
|
|
|
return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->clk_type, true, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* clk_scu_unprepare - Disable a SCU clock
|
|
|
|
* @hw: clock to enable
|
|
|
|
*
|
|
|
|
* Disable the clock at the DSC slice level
|
|
|
|
*/
|
|
|
|
static void clk_scu_unprepare(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = to_clk_scu(hw);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->clk_type, false, false);
|
|
|
|
if (ret)
|
|
|
|
pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
|
|
|
|
ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct clk_ops clk_scu_ops = {
|
|
|
|
.recalc_rate = clk_scu_recalc_rate,
|
clk: imx: scu: Switch to determine_rate
The iMX SCU clocks implements a mux with a set_parent hook, but doesn't
provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. The round_rate()
implementation being shared with other clocks, it's not removed.
And if it was an oversight, the clock behaviour can be adjusted later
on.
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-58-971d5077e7d2@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-05-05 19:26:00 +08:00
|
|
|
.determine_rate = clk_scu_determine_rate,
|
2018-12-13 23:42:54 +08:00
|
|
|
.set_rate = clk_scu_set_rate,
|
2019-01-30 21:39:15 +08:00
|
|
|
.get_parent = clk_scu_get_parent,
|
|
|
|
.set_parent = clk_scu_set_parent,
|
2018-12-13 23:42:54 +08:00
|
|
|
.prepare = clk_scu_prepare,
|
|
|
|
.unprepare = clk_scu_unprepare,
|
|
|
|
};
|
|
|
|
|
2019-02-26 13:17:36 +08:00
|
|
|
static const struct clk_ops clk_scu_cpu_ops = {
|
|
|
|
.recalc_rate = clk_scu_recalc_rate,
|
|
|
|
.round_rate = clk_scu_round_rate,
|
|
|
|
.set_rate = clk_scu_atf_set_cpu_rate,
|
|
|
|
.prepare = clk_scu_prepare,
|
|
|
|
.unprepare = clk_scu_unprepare,
|
|
|
|
};
|
|
|
|
|
2021-06-04 17:09:35 +08:00
|
|
|
static const struct clk_ops clk_scu_pi_ops = {
|
|
|
|
.recalc_rate = clk_scu_recalc_rate,
|
|
|
|
.round_rate = clk_scu_round_rate,
|
|
|
|
.set_rate = clk_scu_set_rate,
|
|
|
|
};
|
|
|
|
|
2020-07-29 16:00:12 +08:00
|
|
|
struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
|
|
|
|
const char * const *parents, int num_parents,
|
|
|
|
u32 rsrc_id, u8 clk_type)
|
2018-12-13 23:42:54 +08:00
|
|
|
{
|
|
|
|
struct clk_init_data init;
|
|
|
|
struct clk_scu *clk;
|
|
|
|
struct clk_hw *hw;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
|
|
|
if (!clk)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
clk->rsrc_id = rsrc_id;
|
|
|
|
clk->clk_type = clk_type;
|
|
|
|
|
|
|
|
init.name = name;
|
|
|
|
init.ops = &clk_scu_ops;
|
2021-06-04 17:09:40 +08:00
|
|
|
if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72)
|
2019-02-26 13:17:36 +08:00
|
|
|
init.ops = &clk_scu_cpu_ops;
|
2021-06-04 17:09:35 +08:00
|
|
|
else if (rsrc_id == IMX_SC_R_PI_0_PLL)
|
|
|
|
init.ops = &clk_scu_pi_ops;
|
2019-02-26 13:17:36 +08:00
|
|
|
else
|
|
|
|
init.ops = &clk_scu_ops;
|
2019-01-30 21:39:15 +08:00
|
|
|
init.parent_names = parents;
|
|
|
|
init.num_parents = num_parents;
|
|
|
|
|
2018-12-13 23:42:54 +08:00
|
|
|
/*
|
|
|
|
* Note on MX8, the clocks are tightly coupled with power domain
|
|
|
|
* that once the power domain is off, the clock status may be
|
|
|
|
* lost. So we make it NOCACHE to let user to retrieve the real
|
|
|
|
* clock status from HW instead of using the possible invalid
|
|
|
|
* cached rate.
|
|
|
|
*/
|
|
|
|
init.flags = CLK_GET_RATE_NOCACHE;
|
|
|
|
clk->hw.init = &init;
|
|
|
|
|
|
|
|
hw = &clk->hw;
|
2020-07-29 16:00:12 +08:00
|
|
|
ret = clk_hw_register(dev, hw);
|
2018-12-13 23:42:54 +08:00
|
|
|
if (ret) {
|
|
|
|
kfree(clk);
|
|
|
|
hw = ERR_PTR(ret);
|
2021-03-23 11:10:34 +08:00
|
|
|
return hw;
|
2018-12-13 23:42:54 +08:00
|
|
|
}
|
|
|
|
|
2020-07-29 16:00:14 +08:00
|
|
|
if (dev)
|
|
|
|
dev_set_drvdata(dev, clk);
|
|
|
|
|
2018-12-13 23:42:54 +08:00
|
|
|
return hw;
|
|
|
|
}
|
2020-07-29 16:00:10 +08:00
|
|
|
|
|
|
|
struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
unsigned int rsrc = clkspec->args[0];
|
|
|
|
unsigned int idx = clkspec->args[1];
|
|
|
|
struct list_head *scu_clks = data;
|
|
|
|
struct imx_scu_clk_node *clk;
|
|
|
|
|
|
|
|
list_for_each_entry(clk, &scu_clks[rsrc], node) {
|
|
|
|
if (clk->clk_type == idx)
|
|
|
|
return clk->hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_clk_scu_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct imx_scu_clk_node *clk = dev_get_platdata(dev);
|
|
|
|
struct clk_hw *hw;
|
2020-07-29 16:00:13 +08:00
|
|
|
int ret;
|
|
|
|
|
2021-06-04 17:09:43 +08:00
|
|
|
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
|
|
|
|
(clk->rsrc == IMX_SC_R_A72))) {
|
|
|
|
pm_runtime_set_suspended(dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, 50);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
|
2022-04-25 09:11:17 +08:00
|
|
|
ret = pm_runtime_resume_and_get(dev);
|
2021-06-04 17:09:43 +08:00
|
|
|
if (ret) {
|
|
|
|
pm_genpd_remove_device(dev);
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
2020-07-29 16:00:13 +08:00
|
|
|
}
|
2020-07-29 16:00:10 +08:00
|
|
|
|
2020-07-29 16:00:13 +08:00
|
|
|
hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
|
2020-07-29 16:00:10 +08:00
|
|
|
clk->rsrc, clk->clk_type);
|
2020-07-29 16:00:13 +08:00
|
|
|
if (IS_ERR(hw)) {
|
|
|
|
pm_runtime_disable(dev);
|
2020-07-29 16:00:10 +08:00
|
|
|
return PTR_ERR(hw);
|
2020-07-29 16:00:13 +08:00
|
|
|
}
|
2020-07-29 16:00:10 +08:00
|
|
|
|
|
|
|
clk->hw = hw;
|
|
|
|
list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);
|
|
|
|
|
2021-06-04 17:09:43 +08:00
|
|
|
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
|
|
|
|
(clk->rsrc == IMX_SC_R_A72))) {
|
|
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
}
|
2020-07-29 16:00:13 +08:00
|
|
|
|
2020-07-29 16:00:10 +08:00
|
|
|
dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,
|
|
|
|
clk->clk_type);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-07-29 16:00:14 +08:00
|
|
|
static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = dev_get_drvdata(dev);
|
2021-06-04 17:09:36 +08:00
|
|
|
u32 rsrc_id = clk->rsrc_id;
|
|
|
|
|
|
|
|
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
|
|
|
|
(rsrc_id == IMX_SC_R_A72))
|
|
|
|
return 0;
|
2020-07-29 16:00:14 +08:00
|
|
|
|
2021-06-04 17:09:42 +08:00
|
|
|
clk->parent = clk_hw_get_parent(&clk->hw);
|
|
|
|
|
2021-06-04 17:09:41 +08:00
|
|
|
/* DC SS needs to handle bypass clock using non-cached clock rate */
|
|
|
|
if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
|
|
|
|
clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
|
|
|
|
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
|
|
|
|
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
|
|
|
|
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
|
|
|
|
else
|
|
|
|
clk->rate = clk_hw_get_rate(&clk->hw);
|
2020-07-29 16:00:14 +08:00
|
|
|
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
|
|
|
|
|
2021-06-04 17:09:42 +08:00
|
|
|
if (clk->parent)
|
|
|
|
dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),
|
|
|
|
clk->parent_index);
|
|
|
|
|
2020-07-29 16:00:14 +08:00
|
|
|
if (clk->rate)
|
|
|
|
dev_dbg(dev, "save rate %d\n", clk->rate);
|
|
|
|
|
|
|
|
if (clk->is_enabled)
|
|
|
|
dev_dbg(dev, "save enabled state\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __maybe_unused imx_clk_scu_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct clk_scu *clk = dev_get_drvdata(dev);
|
2021-06-04 17:09:36 +08:00
|
|
|
u32 rsrc_id = clk->rsrc_id;
|
2020-07-29 16:00:14 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
2021-06-04 17:09:36 +08:00
|
|
|
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
|
|
|
|
(rsrc_id == IMX_SC_R_A72))
|
|
|
|
return 0;
|
|
|
|
|
2021-06-04 17:09:42 +08:00
|
|
|
if (clk->parent) {
|
|
|
|
ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
|
|
|
|
dev_dbg(dev, "restore parent %s idx %u %s\n",
|
|
|
|
clk_hw_get_name(clk->parent),
|
|
|
|
clk->parent_index, !ret ? "success" : "failed");
|
|
|
|
}
|
|
|
|
|
2020-07-29 16:00:14 +08:00
|
|
|
if (clk->rate) {
|
|
|
|
ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
|
|
|
|
dev_dbg(dev, "restore rate %d %s\n", clk->rate,
|
|
|
|
!ret ? "success" : "failed");
|
|
|
|
}
|
|
|
|
|
2021-06-04 17:09:38 +08:00
|
|
|
if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {
|
2020-07-29 16:00:14 +08:00
|
|
|
ret = clk_scu_prepare(&clk->hw);
|
|
|
|
dev_dbg(dev, "restore enabled state %s\n",
|
|
|
|
!ret ? "success" : "failed");
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops imx_clk_scu_pm_ops = {
|
|
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_scu_suspend,
|
|
|
|
imx_clk_scu_resume)
|
|
|
|
};
|
|
|
|
|
2020-07-29 16:00:10 +08:00
|
|
|
static struct platform_driver imx_clk_scu_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "imx-scu-clk",
|
|
|
|
.suppress_bind_attrs = true,
|
2020-07-29 16:00:14 +08:00
|
|
|
.pm = &imx_clk_scu_pm_ops,
|
2020-07-29 16:00:10 +08:00
|
|
|
},
|
|
|
|
.probe = imx_clk_scu_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int imx_clk_scu_attach_pd(struct device *dev, u32 rsrc_id)
|
|
|
|
{
|
|
|
|
struct of_phandle_args genpdspec = {
|
|
|
|
.np = pd_np,
|
|
|
|
.args_count = 1,
|
|
|
|
.args[0] = rsrc_id,
|
|
|
|
};
|
|
|
|
|
2020-07-29 16:00:11 +08:00
|
|
|
if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 ||
|
|
|
|
rsrc_id == IMX_SC_R_A72)
|
|
|
|
return 0;
|
|
|
|
|
2020-07-29 16:00:10 +08:00
|
|
|
return of_genpd_add_device(&genpdspec, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
|
|
|
|
const char * const *parents,
|
|
|
|
int num_parents, u32 rsrc_id, u8 clk_type)
|
|
|
|
{
|
|
|
|
struct imx_scu_clk_node clk = {
|
|
|
|
.name = name,
|
|
|
|
.rsrc = rsrc_id,
|
|
|
|
.clk_type = clk_type,
|
|
|
|
.parents = parents,
|
|
|
|
.num_parents = num_parents,
|
|
|
|
};
|
|
|
|
struct platform_device *pdev;
|
|
|
|
int ret;
|
|
|
|
|
2021-04-23 11:33:33 +08:00
|
|
|
if (!imx_scu_clk_is_valid(rsrc_id))
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
2020-07-29 16:00:10 +08:00
|
|
|
pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
|
|
|
|
if (!pdev) {
|
|
|
|
pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
|
|
|
|
name, rsrc_id, clk_type);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = platform_device_add_data(pdev, &clk, sizeof(clk));
|
|
|
|
if (ret) {
|
|
|
|
platform_device_put(pdev);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
2022-04-19 19:34:32 +08:00
|
|
|
ret = driver_set_override(&pdev->dev, &pdev->driver_override,
|
|
|
|
"imx-scu-clk", strlen("imx-scu-clk"));
|
|
|
|
if (ret) {
|
|
|
|
platform_device_put(pdev);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2020-07-29 16:00:10 +08:00
|
|
|
|
|
|
|
ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);
|
|
|
|
if (ret)
|
|
|
|
pr_warn("%s: failed to attached the power domain %d\n",
|
|
|
|
name, ret);
|
|
|
|
|
2022-09-14 11:32:06 +08:00
|
|
|
ret = platform_device_add(pdev);
|
|
|
|
if (ret) {
|
|
|
|
platform_device_put(pdev);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2020-07-29 16:00:10 +08:00
|
|
|
|
|
|
|
/* For API backwards compatiblilty, simply return NULL for success */
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx_clk_scu_unregister(void)
|
|
|
|
{
|
2023-04-19 22:23:01 +08:00
|
|
|
struct imx_scu_clk_node *clk, *n;
|
2020-07-29 16:00:10 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < IMX_SC_R_LAST; i++) {
|
2023-04-19 22:23:01 +08:00
|
|
|
list_for_each_entry_safe(clk, n, &imx_scu_clks[i], node) {
|
2020-07-29 16:00:10 +08:00
|
|
|
clk_hw_unregister(clk->hw);
|
|
|
|
kfree(clk);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2021-04-23 11:33:32 +08:00
|
|
|
|
|
|
|
static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
unsigned long rate = 0;
|
|
|
|
u32 val;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, &val);
|
|
|
|
|
|
|
|
rate = val ? parent_rate / 2 : parent_rate;
|
|
|
|
|
|
|
|
return err ? 0 : rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *prate)
|
|
|
|
{
|
|
|
|
if (rate < *prate)
|
|
|
|
rate = *prate / 2;
|
|
|
|
else
|
|
|
|
rate = *prate;
|
|
|
|
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
uint32_t val;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
val = (rate < parent_rate) ? 1 : 0;
|
|
|
|
err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, val);
|
|
|
|
|
|
|
|
return err ? -EINVAL : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct clk_ops clk_gpr_div_scu_ops = {
|
|
|
|
.recalc_rate = clk_gpr_div_scu_recalc_rate,
|
|
|
|
.round_rate = clk_gpr_div_scu_round_rate,
|
|
|
|
.set_rate = clk_gpr_div_scu_set_rate,
|
|
|
|
};
|
|
|
|
|
|
|
|
static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, &val);
|
|
|
|
|
|
|
|
return (u8)val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
|
|
|
|
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct clk_ops clk_gpr_mux_scu_ops = {
|
clk: imx: scu: Add a determine_rate hook
The iMX SCU mux clock implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidates to
trigger that parent change are either the assigned-clock-parents device
tree property or a call to clk_set_rate(), with determine_rate()
figuring out which parent is the best suited for a given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
Similarly, it doesn't look like the device tree using that clock driver
uses any of the assigned-clock properties on that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The latter case would be equivalent to setting the determine_rate
implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no
determine_rate implementation is provided, clk_round_rate() (through
clk_core_round_rate_nolock()) will call itself on the parent if
CLK_SET_RATE_PARENT is set, and will not change the clock rate
otherwise.
And if it was an oversight, then we are at least explicit about our
behavior now and it can be further refined down the line.
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-28-971d5077e7d2@cerno.tech
| Reported-by: kernel test robot <lkp@intel.com>:
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-05-05 19:25:30 +08:00
|
|
|
.determine_rate = clk_hw_determine_rate_no_reparent,
|
2021-04-23 11:33:32 +08:00
|
|
|
.get_parent = clk_gpr_mux_scu_get_parent,
|
|
|
|
.set_parent = clk_gpr_mux_scu_set_parent,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
|
|
|
|
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, !clk->gate_invert);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, clk->gate_invert);
|
|
|
|
if (ret)
|
|
|
|
pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
|
|
|
|
ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
|
|
|
|
int ret;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
|
|
|
|
clk->gpr_id, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return clk->gate_invert ? !val : val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct clk_ops clk_gpr_gate_scu_ops = {
|
|
|
|
.prepare = clk_gpr_gate_scu_prepare,
|
|
|
|
.unprepare = clk_gpr_gate_scu_unprepare,
|
|
|
|
.is_prepared = clk_gpr_gate_scu_is_prepared,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
|
|
|
|
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
|
|
|
|
bool invert)
|
|
|
|
{
|
|
|
|
struct imx_scu_clk_node *clk_node;
|
|
|
|
struct clk_gpr_scu *clk;
|
|
|
|
struct clk_hw *hw;
|
|
|
|
struct clk_init_data init;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
|
|
|
clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
|
|
|
|
if (!clk_node)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
2022-04-07 15:37:22 +08:00
|
|
|
if (!imx_scu_clk_is_valid(rsrc_id)) {
|
|
|
|
kfree(clk_node);
|
2021-04-23 11:33:33 +08:00
|
|
|
return ERR_PTR(-EINVAL);
|
2022-04-07 15:37:22 +08:00
|
|
|
}
|
2021-04-23 11:33:33 +08:00
|
|
|
|
2021-04-23 11:33:32 +08:00
|
|
|
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
|
|
|
if (!clk) {
|
|
|
|
kfree(clk_node);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
clk->rsrc_id = rsrc_id;
|
|
|
|
clk->gpr_id = gpr_id;
|
|
|
|
clk->flags = flags;
|
|
|
|
clk->gate_invert = invert;
|
|
|
|
|
|
|
|
if (flags & IMX_SCU_GPR_CLK_GATE)
|
|
|
|
init.ops = &clk_gpr_gate_scu_ops;
|
|
|
|
|
|
|
|
if (flags & IMX_SCU_GPR_CLK_DIV)
|
|
|
|
init.ops = &clk_gpr_div_scu_ops;
|
|
|
|
|
|
|
|
if (flags & IMX_SCU_GPR_CLK_MUX)
|
|
|
|
init.ops = &clk_gpr_mux_scu_ops;
|
|
|
|
|
|
|
|
init.flags = 0;
|
|
|
|
init.name = name;
|
|
|
|
init.parent_names = parent_name;
|
|
|
|
init.num_parents = num_parents;
|
|
|
|
|
|
|
|
clk->hw.init = &init;
|
|
|
|
|
|
|
|
hw = &clk->hw;
|
|
|
|
ret = clk_hw_register(NULL, hw);
|
|
|
|
if (ret) {
|
|
|
|
kfree(clk);
|
|
|
|
kfree(clk_node);
|
|
|
|
hw = ERR_PTR(ret);
|
|
|
|
} else {
|
|
|
|
clk_node->hw = hw;
|
|
|
|
clk_node->clk_type = gpr_id;
|
|
|
|
list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return hw;
|
|
|
|
}
|