2018-11-14 21:01:35 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP.
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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struct clk_divider_gate {
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struct clk_divider divider;
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u32 cached_val;
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};
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static inline struct clk_divider_gate *to_clk_divider_gate(struct clk_hw *hw)
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{
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struct clk_divider *div = to_clk_divider(hw);
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return container_of(div, struct clk_divider_gate, divider);
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}
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static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *div = to_clk_divider(hw);
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unsigned int val;
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2019-04-18 19:12:11 +08:00
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val = readl(div->reg) >> div->shift;
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2018-11-14 21:01:35 +08:00
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val &= clk_div_mask(div->width);
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if (!val)
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return 0;
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return divider_recalc_rate(hw, parent_rate, val, div->table,
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div->flags, div->width);
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}
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static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
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struct clk_divider *div = to_clk_divider(hw);
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2019-11-04 18:11:37 +08:00
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unsigned long flags;
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2018-11-14 21:01:35 +08:00
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unsigned int val;
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spin_lock_irqsave(div->lock, flags);
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if (!clk_hw_is_enabled(hw)) {
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val = div_gate->cached_val;
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} else {
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2019-04-18 19:12:11 +08:00
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val = readl(div->reg) >> div->shift;
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2018-11-14 21:01:35 +08:00
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val &= clk_div_mask(div->width);
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}
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spin_unlock_irqrestore(div->lock, flags);
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if (!val)
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return 0;
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return divider_recalc_rate(hw, parent_rate, val, div->table,
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div->flags, div->width);
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}
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2021-07-03 06:51:41 +08:00
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static int clk_divider_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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2018-11-14 21:01:35 +08:00
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{
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2021-07-03 06:51:41 +08:00
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return clk_divider_ops.determine_rate(hw, req);
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2018-11-14 21:01:35 +08:00
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}
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static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
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struct clk_divider *div = to_clk_divider(hw);
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2019-11-04 18:11:37 +08:00
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unsigned long flags;
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2018-11-14 21:01:35 +08:00
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int value;
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u32 val;
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value = divider_get_val(rate, parent_rate, div->table,
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div->width, div->flags);
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if (value < 0)
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return value;
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spin_lock_irqsave(div->lock, flags);
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if (clk_hw_is_enabled(hw)) {
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2019-04-18 19:12:11 +08:00
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val = readl(div->reg);
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2018-11-14 21:01:35 +08:00
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val &= ~(clk_div_mask(div->width) << div->shift);
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val |= (u32)value << div->shift;
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2019-04-18 19:12:11 +08:00
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writel(val, div->reg);
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2018-11-14 21:01:35 +08:00
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} else {
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div_gate->cached_val = value;
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}
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spin_unlock_irqrestore(div->lock, flags);
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return 0;
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}
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static int clk_divider_enable(struct clk_hw *hw)
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{
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struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
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struct clk_divider *div = to_clk_divider(hw);
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2019-11-04 18:11:37 +08:00
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unsigned long flags;
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2018-11-14 21:01:35 +08:00
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u32 val;
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if (!div_gate->cached_val) {
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pr_err("%s: no valid preset rate\n", clk_hw_get_name(hw));
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return -EINVAL;
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}
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spin_lock_irqsave(div->lock, flags);
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/* restore div val */
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2019-04-18 19:12:11 +08:00
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val = readl(div->reg);
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2018-11-14 21:01:35 +08:00
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val |= div_gate->cached_val << div->shift;
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2019-04-18 19:12:11 +08:00
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writel(val, div->reg);
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2018-11-14 21:01:35 +08:00
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spin_unlock_irqrestore(div->lock, flags);
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return 0;
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}
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static void clk_divider_disable(struct clk_hw *hw)
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{
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struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
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struct clk_divider *div = to_clk_divider(hw);
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2019-11-04 18:11:37 +08:00
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unsigned long flags;
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2018-11-14 21:01:35 +08:00
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u32 val;
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spin_lock_irqsave(div->lock, flags);
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/* store the current div val */
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2019-04-18 19:12:11 +08:00
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val = readl(div->reg) >> div->shift;
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2018-11-14 21:01:35 +08:00
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val &= clk_div_mask(div->width);
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div_gate->cached_val = val;
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2019-04-18 19:12:11 +08:00
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writel(0, div->reg);
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2018-11-14 21:01:35 +08:00
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spin_unlock_irqrestore(div->lock, flags);
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}
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static int clk_divider_is_enabled(struct clk_hw *hw)
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{
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struct clk_divider *div = to_clk_divider(hw);
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u32 val;
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2019-04-18 19:12:11 +08:00
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val = readl(div->reg) >> div->shift;
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2018-11-14 21:01:35 +08:00
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val &= clk_div_mask(div->width);
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return val ? 1 : 0;
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}
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static const struct clk_ops clk_divider_gate_ro_ops = {
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.recalc_rate = clk_divider_gate_recalc_rate_ro,
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2021-07-03 06:51:41 +08:00
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.determine_rate = clk_divider_determine_rate,
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2018-11-14 21:01:35 +08:00
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};
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static const struct clk_ops clk_divider_gate_ops = {
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.recalc_rate = clk_divider_gate_recalc_rate,
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2021-07-03 06:51:41 +08:00
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.determine_rate = clk_divider_determine_rate,
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2018-11-14 21:01:35 +08:00
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.set_rate = clk_divider_gate_set_rate,
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.enable = clk_divider_enable,
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.disable = clk_divider_disable,
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.is_enabled = clk_divider_is_enabled,
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};
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/*
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2019-11-04 18:11:33 +08:00
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* NOTE: In order to reuse the most code from the common divider,
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2018-11-14 21:01:35 +08:00
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* we also design our divider following the way that provids an extra
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* clk_divider_flags, however it's fixed to CLK_DIVIDER_ONE_BASED by
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* default as our HW is. Besides that it supports only CLK_DIVIDER_READ_ONLY
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* flag which can be specified by user flexibly.
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*/
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2019-12-11 17:25:49 +08:00
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struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
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2018-11-14 21:01:35 +08:00
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unsigned long flags, void __iomem *reg,
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u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table,
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spinlock_t *lock)
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{
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struct clk_init_data init;
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struct clk_divider_gate *div_gate;
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struct clk_hw *hw;
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u32 val;
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int ret;
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div_gate = kzalloc(sizeof(*div_gate), GFP_KERNEL);
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if (!div_gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
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init.ops = &clk_divider_gate_ro_ops;
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else
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init.ops = &clk_divider_gate_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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div_gate->divider.reg = reg;
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div_gate->divider.shift = shift;
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div_gate->divider.width = width;
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div_gate->divider.lock = lock;
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div_gate->divider.table = table;
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div_gate->divider.hw.init = &init;
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div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
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/* cache gate status */
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val = readl(reg) >> shift;
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2018-11-14 21:01:35 +08:00
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val &= clk_div_mask(width);
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div_gate->cached_val = val;
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hw = &div_gate->divider.hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(div_gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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