clk: qcom: Configure the RCGs to a safe source as needed
For some root clock generators, there could be child branches which are
controlled by an entity other than application processor subsystem. For
such RCGs, as per application processor subsystem clock driver, all of
its downstream clocks are disabled and RCG is in disabled state but in
reality downstream clocks can be left enabled before.
So in this scenario, when RCG is disabled as per clock driver's point of
view and when rate scaling request comes before downstream clock enable
request, then RCG fails to update its configuration because in reality
RCG is on and it expects its new source to already be in enable state but
in reality new source is off. In order to avoid having the RCG to go into
an invalid state, add support to update the CFG, M, N and D registers
during set_rate() without configuration update and defer the actual RCG
configuration update to be done during clk_enable() as at this point of
time, both its new parent and safe source will be already enabled and RCG
can safely switch to new parent.
During clk_disable() request, configure it to safe source as both its
parents, safe source and current parent will be enabled and RCG can
safely execute a switch.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2014-01-16 02:47:25 +08:00
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/*
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2018-03-08 15:18:12 +08:00
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* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
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2014-01-16 02:47:25 +08:00
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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2014-05-17 07:07:11 +08:00
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#include <linux/math64.h>
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2018-08-11 09:53:55 +08:00
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#include <linux/slab.h>
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2014-01-16 02:47:25 +08:00
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#include <asm/div64.h>
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#include "clk-rcg.h"
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2014-09-05 04:21:50 +08:00
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#include "common.h"
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2014-01-16 02:47:25 +08:00
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#define CMD_REG 0x0
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#define CMD_UPDATE BIT(0)
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#define CMD_ROOT_EN BIT(1)
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#define CMD_DIRTY_CFG BIT(4)
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#define CMD_DIRTY_N BIT(5)
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#define CMD_DIRTY_M BIT(6)
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#define CMD_DIRTY_D BIT(7)
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#define CMD_ROOT_OFF BIT(31)
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#define CFG_REG 0x4
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#define CFG_SRC_DIV_SHIFT 0
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#define CFG_SRC_SEL_SHIFT 8
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#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
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#define CFG_MODE_SHIFT 12
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#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
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#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
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2018-03-08 15:18:12 +08:00
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#define CFG_HW_CLK_CTRL_MASK BIT(20)
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2014-01-16 02:47:25 +08:00
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#define M_REG 0x8
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#define N_REG 0xc
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#define D_REG 0x10
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2019-02-11 15:39:27 +08:00
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#define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
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#define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
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#define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
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#define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
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2018-08-11 09:53:55 +08:00
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/* Dynamic Frequency Scaling */
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#define MAX_PERF_LEVEL 8
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#define SE_CMD_DFSR_OFFSET 0x14
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#define SE_CMD_DFS_EN BIT(0)
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#define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
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#define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
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#define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
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2016-11-21 14:37:11 +08:00
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enum freq_policy {
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FLOOR,
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CEIL,
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};
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2014-01-16 02:47:25 +08:00
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static int clk_rcg2_is_enabled(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 cmd;
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int ret;
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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if (ret)
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return ret;
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2014-05-17 07:07:08 +08:00
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return (cmd & CMD_ROOT_OFF) == 0;
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2014-01-16 02:47:25 +08:00
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}
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static u8 clk_rcg2_get_parent(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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2015-06-26 07:53:23 +08:00
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int num_parents = clk_hw_get_num_parents(hw);
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2014-01-16 02:47:25 +08:00
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u32 cfg;
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int i, ret;
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2019-02-11 15:39:27 +08:00
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ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
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2014-01-16 02:47:25 +08:00
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if (ret)
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2015-03-21 00:30:24 +08:00
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goto err;
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2014-01-16 02:47:25 +08:00
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cfg &= CFG_SRC_SEL_MASK;
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cfg >>= CFG_SRC_SEL_SHIFT;
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for (i = 0; i < num_parents; i++)
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2015-03-21 00:30:26 +08:00
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if (cfg == rcg->parent_map[i].cfg)
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2014-01-16 02:47:25 +08:00
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return i;
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2015-03-21 00:30:24 +08:00
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err:
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pr_debug("%s: Clock %s has invalid parent, using default.\n",
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2015-07-31 08:20:57 +08:00
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__func__, clk_hw_get_name(hw));
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2015-03-21 00:30:24 +08:00
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return 0;
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2014-01-16 02:47:25 +08:00
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}
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static int update_config(struct clk_rcg2 *rcg)
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{
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int count, ret;
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u32 cmd;
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struct clk_hw *hw = &rcg->clkr.hw;
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2015-07-31 08:20:57 +08:00
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const char *name = clk_hw_get_name(hw);
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2014-01-16 02:47:25 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
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CMD_UPDATE, CMD_UPDATE);
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if (ret)
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return ret;
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/* Wait for update to take effect */
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for (count = 500; count > 0; count--) {
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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if (ret)
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return ret;
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if (!(cmd & CMD_UPDATE))
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return 0;
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udelay(1);
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}
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WARN(1, "%s: rcg didn't update its configuration.", name);
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return 0;
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}
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static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int ret;
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2015-03-21 00:30:26 +08:00
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u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
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2014-01-16 02:47:25 +08:00
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2019-02-11 15:39:27 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
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2015-03-21 00:30:26 +08:00
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CFG_SRC_SEL_MASK, cfg);
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2014-01-16 02:47:25 +08:00
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if (ret)
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return ret;
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return update_config(rcg);
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}
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/*
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* Calculate m/n:d rate
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*
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* parent_rate m
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* rate = ----------- x ---
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* hid_div n
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*/
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static unsigned long
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calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
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{
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if (hid_div) {
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rate *= 2;
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rate /= hid_div + 1;
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}
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if (mode) {
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u64 tmp = rate;
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tmp *= m;
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do_div(tmp, n);
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rate = tmp;
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}
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return rate;
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}
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static unsigned long
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clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
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2019-02-11 15:39:27 +08:00
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regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
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2014-01-16 02:47:25 +08:00
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if (rcg->mnd_width) {
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mask = BIT(rcg->mnd_width) - 1;
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2019-02-11 15:39:27 +08:00
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regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
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2014-01-16 02:47:25 +08:00
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m &= mask;
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2019-02-11 15:39:27 +08:00
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regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
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2014-01-16 02:47:25 +08:00
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n = ~n;
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n &= mask;
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n += m;
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mode = cfg & CFG_MODE_MASK;
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mode >>= CFG_MODE_SHIFT;
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}
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mask = BIT(rcg->hid_width) - 1;
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hid_div = cfg >> CFG_SRC_DIV_SHIFT;
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hid_div &= mask;
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return calc_rate(parent_rate, m, n, mode, hid_div);
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}
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2016-11-21 14:37:11 +08:00
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static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
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struct clk_rate_request *req,
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enum freq_policy policy)
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2014-01-16 02:47:25 +08:00
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{
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2015-07-08 02:48:08 +08:00
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unsigned long clk_flags, rate = req->rate;
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2015-07-31 08:20:57 +08:00
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struct clk_hw *p;
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2015-04-07 22:14:51 +08:00
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int index;
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2014-01-16 02:47:25 +08:00
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2016-11-21 14:37:11 +08:00
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switch (policy) {
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case FLOOR:
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f = qcom_find_freq_floor(f, rate);
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break;
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case CEIL:
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f = qcom_find_freq(f, rate);
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break;
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default:
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return -EINVAL;
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};
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2014-01-16 02:47:25 +08:00
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if (!f)
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return -EINVAL;
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2015-04-07 22:14:51 +08:00
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index = qcom_find_src_index(hw, rcg->parent_map, f->src);
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if (index < 0)
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return index;
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2015-06-30 07:56:30 +08:00
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clk_flags = clk_hw_get_flags(hw);
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2015-07-31 08:20:57 +08:00
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p = clk_hw_get_parent_by_index(hw, index);
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2014-01-16 02:47:25 +08:00
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if (clk_flags & CLK_SET_RATE_PARENT) {
|
2018-04-14 04:33:36 +08:00
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rate = f->freq;
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2014-01-16 02:47:25 +08:00
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if (f->pre_div) {
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rate /= 2;
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rate *= f->pre_div + 1;
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}
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if (f->n) {
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u64 tmp = rate;
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tmp = tmp * f->n;
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do_div(tmp, f->m);
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rate = tmp;
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}
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} else {
|
2015-07-31 08:20:57 +08:00
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rate = clk_hw_get_rate(p);
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2014-01-16 02:47:25 +08:00
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}
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2015-07-31 08:20:57 +08:00
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req->best_parent_hw = p;
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2015-07-08 02:48:08 +08:00
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req->best_parent_rate = rate;
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req->rate = f->freq;
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2014-01-16 02:47:25 +08:00
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2015-07-08 02:48:08 +08:00
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return 0;
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2014-01-16 02:47:25 +08:00
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}
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2015-07-08 02:48:08 +08:00
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static int clk_rcg2_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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2014-01-16 02:47:25 +08:00
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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2016-11-21 14:37:11 +08:00
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return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
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}
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static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
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2014-01-16 02:47:25 +08:00
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}
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|
clk: qcom: Configure the RCGs to a safe source as needed
For some root clock generators, there could be child branches which are
controlled by an entity other than application processor subsystem. For
such RCGs, as per application processor subsystem clock driver, all of
its downstream clocks are disabled and RCG is in disabled state but in
reality downstream clocks can be left enabled before.
So in this scenario, when RCG is disabled as per clock driver's point of
view and when rate scaling request comes before downstream clock enable
request, then RCG fails to update its configuration because in reality
RCG is on and it expects its new source to already be in enable state but
in reality new source is off. In order to avoid having the RCG to go into
an invalid state, add support to update the CFG, M, N and D registers
during set_rate() without configuration update and defer the actual RCG
configuration update to be done during clk_enable() as at this point of
time, both its new parent and safe source will be already enabled and RCG
can safely switch to new parent.
During clk_disable() request, configure it to safe source as both its
parents, safe source and current parent will be enabled and RCG can
safely execute a switch.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
|
|
|
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
2014-01-16 02:47:25 +08:00
|
|
|
{
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u32 cfg, mask;
|
2015-03-21 00:30:26 +08:00
|
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|
struct clk_hw *hw = &rcg->clkr.hw;
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int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
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|
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|
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|
if (index < 0)
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|
return index;
|
2014-01-16 02:47:25 +08:00
|
|
|
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|
|
|
if (rcg->mnd_width && f->n) {
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mask = BIT(rcg->mnd_width) - 1;
|
2014-05-17 07:07:11 +08:00
|
|
|
ret = regmap_update_bits(rcg->clkr.regmap,
|
2019-02-11 15:39:27 +08:00
|
|
|
RCG_M_OFFSET(rcg), mask, f->m);
|
2014-01-16 02:47:25 +08:00
|
|
|
if (ret)
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|
|
return ret;
|
|
|
|
|
2014-05-17 07:07:11 +08:00
|
|
|
ret = regmap_update_bits(rcg->clkr.regmap,
|
2019-02-11 15:39:27 +08:00
|
|
|
RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
|
2014-01-16 02:47:25 +08:00
|
|
|
if (ret)
|
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|
|
return ret;
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|
|
|
|
2014-05-17 07:07:11 +08:00
|
|
|
ret = regmap_update_bits(rcg->clkr.regmap,
|
2019-02-11 15:39:27 +08:00
|
|
|
RCG_D_OFFSET(rcg), mask, ~f->n);
|
2014-01-16 02:47:25 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
mask = BIT(rcg->hid_width) - 1;
|
2018-03-08 15:18:12 +08:00
|
|
|
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
|
2014-01-16 02:47:25 +08:00
|
|
|
cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
|
2015-03-21 00:30:26 +08:00
|
|
|
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
|
2015-03-04 17:49:35 +08:00
|
|
|
if (rcg->mnd_width && f->n && (f->m != f->n))
|
2014-01-16 02:47:25 +08:00
|
|
|
cfg |= CFG_MODE_DUAL_EDGE;
|
2019-02-11 15:39:27 +08:00
|
|
|
return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
|
clk: qcom: Configure the RCGs to a safe source as needed
For some root clock generators, there could be child branches which are
controlled by an entity other than application processor subsystem. For
such RCGs, as per application processor subsystem clock driver, all of
its downstream clocks are disabled and RCG is in disabled state but in
reality downstream clocks can be left enabled before.
So in this scenario, when RCG is disabled as per clock driver's point of
view and when rate scaling request comes before downstream clock enable
request, then RCG fails to update its configuration because in reality
RCG is on and it expects its new source to already be in enable state but
in reality new source is off. In order to avoid having the RCG to go into
an invalid state, add support to update the CFG, M, N and D registers
during set_rate() without configuration update and defer the actual RCG
configuration update to be done during clk_enable() as at this point of
time, both its new parent and safe source will be already enabled and RCG
can safely switch to new parent.
During clk_disable() request, configure it to safe source as both its
parents, safe source and current parent will be enabled and RCG can
safely execute a switch.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
|
|
|
mask, cfg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = __clk_rcg2_configure(rcg, f);
|
2014-01-16 02:47:25 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return update_config(rcg);
|
|
|
|
}
|
|
|
|
|
2016-11-21 14:37:11 +08:00
|
|
|
static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
enum freq_policy policy)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const struct freq_tbl *f;
|
|
|
|
|
2016-11-21 14:37:11 +08:00
|
|
|
switch (policy) {
|
|
|
|
case FLOOR:
|
|
|
|
f = qcom_find_freq_floor(rcg->freq_tbl, rate);
|
|
|
|
break;
|
|
|
|
case CEIL:
|
|
|
|
f = qcom_find_freq(rcg->freq_tbl, rate);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
};
|
|
|
|
|
2014-05-17 07:07:11 +08:00
|
|
|
if (!f)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, f);
|
|
|
|
}
|
|
|
|
|
2014-01-16 02:47:25 +08:00
|
|
|
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
2016-11-21 14:37:11 +08:00
|
|
|
return __clk_rcg2_set_rate(hw, rate, CEIL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
return __clk_rcg2_set_rate(hw, rate, FLOOR);
|
2014-01-16 02:47:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
2016-11-21 14:37:11 +08:00
|
|
|
return __clk_rcg2_set_rate(hw, rate, CEIL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
return __clk_rcg2_set_rate(hw, rate, FLOOR);
|
2014-01-16 02:47:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_rcg2_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.determine_rate = clk_rcg2_determine_rate,
|
|
|
|
.set_rate = clk_rcg2_set_rate,
|
|
|
|
.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_rcg2_ops);
|
2014-05-17 07:07:11 +08:00
|
|
|
|
2016-11-21 14:37:11 +08:00
|
|
|
const struct clk_ops clk_rcg2_floor_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.determine_rate = clk_rcg2_determine_floor_rate,
|
|
|
|
.set_rate = clk_rcg2_set_floor_rate,
|
|
|
|
.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
|
|
|
|
|
2014-05-17 07:07:11 +08:00
|
|
|
struct frac_entry {
|
|
|
|
int num;
|
|
|
|
int den;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
|
|
|
|
{ 52, 295 }, /* 119 M */
|
|
|
|
{ 11, 57 }, /* 130.25 M */
|
|
|
|
{ 63, 307 }, /* 138.50 M */
|
|
|
|
{ 11, 50 }, /* 148.50 M */
|
|
|
|
{ 47, 206 }, /* 154 M */
|
|
|
|
{ 31, 100 }, /* 205.25 M */
|
|
|
|
{ 107, 269 }, /* 268.50 M */
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
|
|
|
|
{ 31, 211 }, /* 119 M */
|
|
|
|
{ 32, 199 }, /* 130.25 M */
|
|
|
|
{ 63, 307 }, /* 138.50 M */
|
|
|
|
{ 11, 60 }, /* 148.50 M */
|
|
|
|
{ 50, 263 }, /* 154 M */
|
|
|
|
{ 31, 120 }, /* 205.25 M */
|
|
|
|
{ 119, 359 }, /* 268.50 M */
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
struct freq_tbl f = *rcg->freq_tbl;
|
|
|
|
const struct frac_entry *frac;
|
|
|
|
int delta = 100000;
|
|
|
|
s64 src_rate = parent_rate;
|
|
|
|
s64 request;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
u32 hid_div;
|
|
|
|
|
|
|
|
if (src_rate == 810000000)
|
|
|
|
frac = frac_table_810m;
|
|
|
|
else
|
|
|
|
frac = frac_table_675m;
|
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
|
|
|
request = rate;
|
|
|
|
request *= frac->den;
|
|
|
|
request = div_s64(request, frac->num);
|
|
|
|
if ((src_rate < (request - delta)) ||
|
|
|
|
(src_rate > (request + delta)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
&hid_div);
|
|
|
|
f.pre_div = hid_div;
|
|
|
|
f.pre_div >>= CFG_SRC_DIV_SHIFT;
|
|
|
|
f.pre_div &= mask;
|
|
|
|
f.m = frac->num;
|
|
|
|
f.n = frac->den;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
/* Parent index is set statically in frequency table */
|
|
|
|
return clk_edp_pixel_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const struct freq_tbl *f = rcg->freq_tbl;
|
|
|
|
const struct frac_entry *frac;
|
|
|
|
int delta = 100000;
|
|
|
|
s64 request;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
u32 hid_div;
|
2015-04-07 22:14:51 +08:00
|
|
|
int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
|
2014-05-17 07:07:11 +08:00
|
|
|
|
|
|
|
/* Force the correct parent */
|
2015-07-31 08:20:57 +08:00
|
|
|
req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
|
|
|
|
req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
|
2014-05-17 07:07:11 +08:00
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
if (req->best_parent_rate == 810000000)
|
2014-05-17 07:07:11 +08:00
|
|
|
frac = frac_table_810m;
|
|
|
|
else
|
|
|
|
frac = frac_table_675m;
|
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
2015-07-08 02:48:08 +08:00
|
|
|
request = req->rate;
|
2014-05-17 07:07:11 +08:00
|
|
|
request *= frac->den;
|
|
|
|
request = div_s64(request, frac->num);
|
2015-07-08 02:48:08 +08:00
|
|
|
if ((req->best_parent_rate < (request - delta)) ||
|
|
|
|
(req->best_parent_rate > (request + delta)))
|
2014-05-17 07:07:11 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
&hid_div);
|
|
|
|
hid_div >>= CFG_SRC_DIV_SHIFT;
|
|
|
|
hid_div &= mask;
|
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
req->rate = calc_rate(req->best_parent_rate,
|
|
|
|
frac->num, frac->den,
|
|
|
|
!!frac->den, hid_div);
|
|
|
|
return 0;
|
2014-05-17 07:07:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_edp_pixel_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_edp_pixel_set_rate,
|
|
|
|
.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_edp_pixel_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
|
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
static int clk_byte_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const struct freq_tbl *f = rcg->freq_tbl;
|
2015-04-07 22:14:51 +08:00
|
|
|
int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
|
2014-05-17 07:07:11 +08:00
|
|
|
unsigned long parent_rate, div;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
2015-07-31 08:20:57 +08:00
|
|
|
struct clk_hw *p;
|
2014-05-17 07:07:11 +08:00
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
if (req->rate == 0)
|
2014-05-17 07:07:11 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2015-07-31 08:20:57 +08:00
|
|
|
req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
|
|
|
|
req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
|
2014-05-17 07:07:11 +08:00
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
|
2014-05-17 07:07:11 +08:00
|
|
|
div = min_t(u32, div, mask);
|
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
req->rate = calc_rate(parent_rate, 0, 0, 0, div);
|
|
|
|
|
|
|
|
return 0;
|
2014-05-17 07:07:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
struct freq_tbl f = *rcg->freq_tbl;
|
|
|
|
unsigned long div;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
|
|
|
|
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
|
|
|
|
div = min_t(u32, div, mask);
|
|
|
|
|
|
|
|
f.pre_div = div;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
/* Parent index is set statically in frequency table */
|
|
|
|
return clk_byte_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_byte_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_byte_set_rate,
|
|
|
|
.set_rate_and_parent = clk_byte_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_byte_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_byte_ops);
|
|
|
|
|
2015-04-10 14:02:02 +08:00
|
|
|
static int clk_byte2_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
unsigned long parent_rate, div;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
struct clk_hw *p;
|
|
|
|
unsigned long rate = req->rate;
|
|
|
|
|
|
|
|
if (rate == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
p = req->best_parent_hw;
|
|
|
|
req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
|
|
|
|
|
|
|
|
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
|
|
|
|
div = min_t(u32, div, mask);
|
|
|
|
|
|
|
|
req->rate = calc_rate(parent_rate, 0, 0, 0, div);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
struct freq_tbl f = { 0 };
|
|
|
|
unsigned long div;
|
|
|
|
int i, num_parents = clk_hw_get_num_parents(hw);
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
u32 cfg;
|
|
|
|
|
|
|
|
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
|
|
|
|
div = min_t(u32, div, mask);
|
|
|
|
|
|
|
|
f.pre_div = div;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
|
|
|
|
cfg &= CFG_SRC_SEL_MASK;
|
|
|
|
cfg >>= CFG_SRC_SEL_SHIFT;
|
|
|
|
|
|
|
|
for (i = 0; i < num_parents; i++) {
|
|
|
|
if (cfg == rcg->parent_map[i].cfg) {
|
|
|
|
f.src = rcg->parent_map[i].src;
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_byte2_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
/* Read the hardware to determine parent during set_rate */
|
|
|
|
return clk_byte2_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_byte2_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_byte2_set_rate,
|
|
|
|
.set_rate_and_parent = clk_byte2_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_byte2_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_byte2_ops);
|
|
|
|
|
2014-05-17 07:07:11 +08:00
|
|
|
static const struct frac_entry frac_table_pixel[] = {
|
|
|
|
{ 3, 8 },
|
|
|
|
{ 2, 9 },
|
|
|
|
{ 4, 9 },
|
|
|
|
{ 1, 1 },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
static int clk_pixel_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
unsigned long request, src_rate;
|
|
|
|
int delta = 100000;
|
|
|
|
const struct frac_entry *frac = frac_table_pixel;
|
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
2015-07-08 02:48:08 +08:00
|
|
|
request = (req->rate * frac->den) / frac->num;
|
2014-05-17 07:07:11 +08:00
|
|
|
|
2015-07-31 08:20:57 +08:00
|
|
|
src_rate = clk_hw_round_rate(req->best_parent_hw, request);
|
2014-05-17 07:07:11 +08:00
|
|
|
if ((src_rate < (request - delta)) ||
|
|
|
|
(src_rate > (request + delta)))
|
|
|
|
continue;
|
|
|
|
|
2015-07-08 02:48:08 +08:00
|
|
|
req->best_parent_rate = src_rate;
|
|
|
|
req->rate = (src_rate * frac->num) / frac->den;
|
|
|
|
return 0;
|
2014-05-17 07:07:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
2015-04-10 14:02:02 +08:00
|
|
|
struct freq_tbl f = { 0 };
|
2014-05-17 07:07:11 +08:00
|
|
|
const struct frac_entry *frac = frac_table_pixel;
|
2015-06-26 06:35:33 +08:00
|
|
|
unsigned long request;
|
2014-05-17 07:07:11 +08:00
|
|
|
int delta = 100000;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
2015-04-10 14:02:02 +08:00
|
|
|
u32 hid_div, cfg;
|
|
|
|
int i, num_parents = clk_hw_get_num_parents(hw);
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
|
|
|
|
cfg &= CFG_SRC_SEL_MASK;
|
|
|
|
cfg >>= CFG_SRC_SEL_SHIFT;
|
|
|
|
|
|
|
|
for (i = 0; i < num_parents; i++)
|
|
|
|
if (cfg == rcg->parent_map[i].cfg) {
|
|
|
|
f.src = rcg->parent_map[i].src;
|
|
|
|
break;
|
|
|
|
}
|
2014-05-17 07:07:11 +08:00
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
|
|
|
request = (rate * frac->den) / frac->num;
|
|
|
|
|
2015-06-26 06:35:33 +08:00
|
|
|
if ((parent_rate < (request - delta)) ||
|
|
|
|
(parent_rate > (request + delta)))
|
2014-05-17 07:07:11 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
&hid_div);
|
|
|
|
f.pre_div = hid_div;
|
|
|
|
f.pre_div >>= CFG_SRC_DIV_SHIFT;
|
|
|
|
f.pre_div &= mask;
|
|
|
|
f.m = frac->num;
|
|
|
|
f.n = frac->den;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
return clk_pixel_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_pixel_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_pixel_set_rate,
|
|
|
|
.set_rate_and_parent = clk_pixel_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_pixel_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_pixel_ops);
|
2015-12-01 09:31:41 +08:00
|
|
|
|
|
|
|
static int clk_gfx3d_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
|
|
|
{
|
|
|
|
struct clk_rate_request parent_req = { };
|
|
|
|
struct clk_hw *p2, *p8, *p9, *xo;
|
|
|
|
unsigned long p9_rate;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
xo = clk_hw_get_parent_by_index(hw, 0);
|
|
|
|
if (req->rate == clk_hw_get_rate(xo)) {
|
|
|
|
req->best_parent_hw = xo;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
p9 = clk_hw_get_parent_by_index(hw, 2);
|
|
|
|
p2 = clk_hw_get_parent_by_index(hw, 3);
|
|
|
|
p8 = clk_hw_get_parent_by_index(hw, 4);
|
|
|
|
|
|
|
|
/* PLL9 is a fixed rate PLL */
|
|
|
|
p9_rate = clk_hw_get_rate(p9);
|
|
|
|
|
|
|
|
parent_req.rate = req->rate = min(req->rate, p9_rate);
|
|
|
|
if (req->rate == p9_rate) {
|
|
|
|
req->rate = req->best_parent_rate = p9_rate;
|
|
|
|
req->best_parent_hw = p9;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req->best_parent_hw == p9) {
|
|
|
|
/* Are we going back to a previously used rate? */
|
|
|
|
if (clk_hw_get_rate(p8) == req->rate)
|
|
|
|
req->best_parent_hw = p8;
|
|
|
|
else
|
|
|
|
req->best_parent_hw = p2;
|
|
|
|
} else if (req->best_parent_hw == p8) {
|
|
|
|
req->best_parent_hw = p2;
|
|
|
|
} else {
|
|
|
|
req->best_parent_hw = p8;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
req->rate = req->best_parent_rate = parent_req.rate;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
u32 cfg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Just mux it, we don't use the division or m/n hardware */
|
|
|
|
cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
|
|
|
|
ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return update_config(rcg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* We should never get here; clk_gfx3d_determine_rate() should always
|
|
|
|
* make us use a different parent than what we're currently using, so
|
|
|
|
* clk_gfx3d_set_rate_and_parent() should always be called.
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_gfx3d_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_gfx3d_set_rate,
|
|
|
|
.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_gfx3d_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
|
clk: qcom: Configure the RCGs to a safe source as needed
For some root clock generators, there could be child branches which are
controlled by an entity other than application processor subsystem. For
such RCGs, as per application processor subsystem clock driver, all of
its downstream clocks are disabled and RCG is in disabled state but in
reality downstream clocks can be left enabled before.
So in this scenario, when RCG is disabled as per clock driver's point of
view and when rate scaling request comes before downstream clock enable
request, then RCG fails to update its configuration because in reality
RCG is on and it expects its new source to already be in enable state but
in reality new source is off. In order to avoid having the RCG to go into
an invalid state, add support to update the CFG, M, N and D registers
during set_rate() without configuration update and defer the actual RCG
configuration update to be done during clk_enable() as at this point of
time, both its new parent and safe source will be already enabled and RCG
can safely switch to new parent.
During clk_disable() request, configure it to safe source as both its
parents, safe source and current parent will be enabled and RCG can
safely execute a switch.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
|
|
|
|
|
|
|
static int clk_rcg2_set_force_enable(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const char *name = clk_hw_get_name(hw);
|
|
|
|
int ret, count;
|
|
|
|
|
|
|
|
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
|
|
|
|
CMD_ROOT_EN, CMD_ROOT_EN);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* wait for RCG to turn ON */
|
|
|
|
for (count = 500; count > 0; count--) {
|
|
|
|
if (clk_rcg2_is_enabled(hw))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_err("%s: RCG did not turn on\n", name);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
|
|
|
|
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
|
|
|
|
CMD_ROOT_EN, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_rcg2_set_force_enable(hw);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_rcg2_configure(rcg, f);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return clk_rcg2_clear_force_enable(hw);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const struct freq_tbl *f;
|
|
|
|
|
|
|
|
f = qcom_find_freq(rcg->freq_tbl, rate);
|
|
|
|
if (!f)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In case clock is disabled, update the CFG, M, N and D registers
|
|
|
|
* and don't hit the update bit of CMD register.
|
|
|
|
*/
|
|
|
|
if (!__clk_is_enabled(hw->clk))
|
|
|
|
return __clk_rcg2_configure(rcg, f);
|
|
|
|
|
|
|
|
return clk_rcg2_shared_force_enable_clear(hw, f);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_shared_enable(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the update bit because required configuration has already
|
|
|
|
* been written in clk_rcg2_shared_set_rate()
|
|
|
|
*/
|
|
|
|
ret = clk_rcg2_set_force_enable(hw);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = update_config(rcg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return clk_rcg2_clear_force_enable(hw);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void clk_rcg2_shared_disable(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
u32 cfg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Store current configuration as switching to safe source would clear
|
|
|
|
* the SRC and DIV of CFG register
|
|
|
|
*/
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Park the RCG at a safe configuration - sourced off of safe source.
|
|
|
|
* Force enable and disable the RCG while configuring it to safeguard
|
|
|
|
* against any update signal coming from the downstream clock.
|
|
|
|
* The current parent is still prepared and enabled at this point, and
|
|
|
|
* the safe source is always on while application processor subsystem
|
|
|
|
* is online. Therefore, the RCG can safely switch its parent.
|
|
|
|
*/
|
|
|
|
clk_rcg2_set_force_enable(hw);
|
|
|
|
|
|
|
|
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
|
|
|
|
|
|
|
|
update_config(rcg);
|
|
|
|
|
|
|
|
clk_rcg2_clear_force_enable(hw);
|
|
|
|
|
|
|
|
/* Write back the stored configuration corresponding to current rate */
|
|
|
|
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_rcg2_shared_ops = {
|
|
|
|
.enable = clk_rcg2_shared_enable,
|
|
|
|
.disable = clk_rcg2_shared_disable,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.determine_rate = clk_rcg2_determine_rate,
|
|
|
|
.set_rate = clk_rcg2_shared_set_rate,
|
|
|
|
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
|
2018-08-11 09:53:55 +08:00
|
|
|
|
|
|
|
/* Common APIs to be used for DFS based RCGR */
|
|
|
|
static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
|
|
|
|
struct freq_tbl *f)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
struct clk_hw *p;
|
|
|
|
unsigned long prate = 0;
|
|
|
|
u32 val, mask, cfg, mode;
|
|
|
|
int i, num_parents;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
|
|
|
|
|
|
|
|
mask = BIT(rcg->hid_width) - 1;
|
|
|
|
f->pre_div = 1;
|
|
|
|
if (cfg & mask)
|
|
|
|
f->pre_div = cfg & mask;
|
|
|
|
|
|
|
|
cfg &= CFG_SRC_SEL_MASK;
|
|
|
|
cfg >>= CFG_SRC_SEL_SHIFT;
|
|
|
|
|
|
|
|
num_parents = clk_hw_get_num_parents(hw);
|
|
|
|
for (i = 0; i < num_parents; i++) {
|
|
|
|
if (cfg == rcg->parent_map[i].cfg) {
|
|
|
|
f->src = rcg->parent_map[i].src;
|
|
|
|
p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
|
|
|
|
prate = clk_hw_get_rate(p);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mode = cfg & CFG_MODE_MASK;
|
|
|
|
mode >>= CFG_MODE_SHIFT;
|
|
|
|
if (mode) {
|
|
|
|
mask = BIT(rcg->mnd_width) - 1;
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
|
|
|
|
&val);
|
|
|
|
val &= mask;
|
|
|
|
f->m = val;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
|
|
|
|
&val);
|
|
|
|
val = ~val;
|
|
|
|
val &= mask;
|
|
|
|
val += f->m;
|
|
|
|
f->n = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
|
|
|
|
{
|
|
|
|
struct freq_tbl *freq_tbl;
|
|
|
|
int i;
|
|
|
|
|
2018-08-31 01:34:37 +08:00
|
|
|
/* Allocate space for 1 extra since table is NULL terminated */
|
|
|
|
freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
|
2018-08-11 09:53:55 +08:00
|
|
|
if (!freq_tbl)
|
|
|
|
return -ENOMEM;
|
|
|
|
rcg->freq_tbl = freq_tbl;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_PERF_LEVEL; i++)
|
|
|
|
clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!rcg->freq_tbl) {
|
|
|
|
ret = clk_rcg2_dfs_populate_freq_table(rcg);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("Failed to update DFS tables for %s\n",
|
|
|
|
clk_hw_get_name(hw));
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return clk_rcg2_determine_rate(hw, req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long
|
|
|
|
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap,
|
|
|
|
rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
|
|
|
|
level &= GENMASK(4, 1);
|
|
|
|
level >>= 1;
|
|
|
|
|
|
|
|
if (rcg->freq_tbl)
|
|
|
|
return rcg->freq_tbl[level].freq;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assume that parent_rate is actually the parent because
|
|
|
|
* we can't do any better at figuring it out when the table
|
|
|
|
* hasn't been populated yet. We only populate the table
|
|
|
|
* in determine_rate because we can't guarantee the parents
|
|
|
|
* will be registered with the framework until then.
|
|
|
|
*/
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
|
|
|
|
&cfg);
|
|
|
|
|
|
|
|
mask = BIT(rcg->hid_width) - 1;
|
|
|
|
pre_div = 1;
|
|
|
|
if (cfg & mask)
|
|
|
|
pre_div = cfg & mask;
|
|
|
|
|
|
|
|
mode = cfg & CFG_MODE_MASK;
|
|
|
|
mode >>= CFG_MODE_SHIFT;
|
|
|
|
if (mode) {
|
|
|
|
mask = BIT(rcg->mnd_width) - 1;
|
|
|
|
regmap_read(rcg->clkr.regmap,
|
|
|
|
rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
|
|
|
|
m &= mask;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap,
|
|
|
|
rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
|
|
|
|
n = ~n;
|
|
|
|
n &= mask;
|
|
|
|
n += m;
|
|
|
|
}
|
|
|
|
|
|
|
|
return calc_rate(parent_rate, m, n, mode, pre_div);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct clk_ops clk_rcg2_dfs_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.determine_rate = clk_rcg2_dfs_determine_rate,
|
|
|
|
.recalc_rate = clk_rcg2_dfs_recalc_rate,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
|
|
|
|
struct regmap *regmap)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = data->rcg;
|
|
|
|
struct clk_init_data *init = data->init;
|
|
|
|
u32 val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!(val & SE_CMD_DFS_EN))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Rate changes with consumer writing a register in
|
|
|
|
* their own I/O region
|
|
|
|
*/
|
|
|
|
init->flags |= CLK_GET_RATE_NOCACHE;
|
|
|
|
init->ops = &clk_rcg2_dfs_ops;
|
|
|
|
|
|
|
|
rcg->freq_tbl = NULL;
|
|
|
|
|
|
|
|
pr_debug("DFS registered for clk %s\n", init->name);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int qcom_cc_register_rcg_dfs(struct regmap *regmap,
|
|
|
|
const struct clk_rcg_dfs_data *rcgs, size_t len)
|
|
|
|
{
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < len; i++) {
|
|
|
|
ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
|
|
|
|
if (ret) {
|
|
|
|
const char *name = rcgs[i].init->name;
|
|
|
|
|
|
|
|
pr_err("DFS register failed for clk %s\n", name);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
|