2019-05-27 14:55:01 +08:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
2005-10-10 12:19:43 +08:00
|
|
|
#ifndef _ASM_POWERPC_PROCESSOR_H
|
|
|
|
|
#define _ASM_POWERPC_PROCESSOR_H
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
2005-10-10 12:19:43 +08:00
|
|
|
* Copyright (C) 2001 PPC 64 Team, IBM Corp
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
|
|
2020-11-26 21:09:59 +08:00
|
|
|
#include <vdso/processor.h>
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#include <asm/reg.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-06-25 12:07:18 +08:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
#define TS_FPRWIDTH 2
|
2013-09-23 10:04:37 +08:00
|
|
|
|
|
|
|
|
#ifdef __BIG_ENDIAN__
|
|
|
|
|
#define TS_FPROFFSET 0
|
|
|
|
|
#define TS_VSRLOWOFFSET 1
|
|
|
|
|
#else
|
|
|
|
|
#define TS_FPROFFSET 1
|
|
|
|
|
#define TS_VSRLOWOFFSET 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-06-25 12:07:18 +08:00
|
|
|
#else
|
2008-06-26 15:07:48 +08:00
|
|
|
#define TS_FPRWIDTH 1
|
2013-09-23 10:04:37 +08:00
|
|
|
#define TS_FPROFFSET 0
|
2008-06-25 12:07:18 +08:00
|
|
|
#endif
|
2008-06-26 15:07:48 +08:00
|
|
|
|
2012-12-07 05:49:56 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
|
|
|
|
|
#define PPR_PRIORITY 3
|
|
|
|
|
#ifdef __ASSEMBLY__
|
2018-10-12 21:15:16 +08:00
|
|
|
#define DEFAULT_PPR (PPR_PRIORITY << 50)
|
2012-12-07 05:49:56 +08:00
|
|
|
#else
|
2018-10-12 21:15:16 +08:00
|
|
|
#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
|
2012-12-07 05:49:56 +08:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#ifndef __ASSEMBLY__
|
2018-07-06 00:25:09 +08:00
|
|
|
#include <linux/types.h>
|
2019-01-17 20:27:28 +08:00
|
|
|
#include <linux/thread_info.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/ptrace.h>
|
2012-12-20 22:06:44 +08:00
|
|
|
#include <asm/hw_breakpoint.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-11-10 10:37:51 +08:00
|
|
|
/* We do _not_ want to define new machine types at all, those must die
|
|
|
|
|
* in favor of using the device-tree
|
|
|
|
|
* -- BenH.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
|
|
2013-03-27 08:47:03 +08:00
|
|
|
/* PREP sub-platform types. Unused */
|
2005-04-17 06:20:36 +08:00
|
|
|
#define _PREP_Motorola 0x01 /* motorola prep */
|
|
|
|
|
#define _PREP_Firm 0x02 /* firmworks prep */
|
|
|
|
|
#define _PREP_IBM 0x00 /* ibm prep */
|
|
|
|
|
#define _PREP_Bull 0x03 /* bull prep */
|
|
|
|
|
|
2005-11-10 10:37:51 +08:00
|
|
|
/* CHRP sub-platform types. These are arbitrary */
|
2005-04-17 06:20:36 +08:00
|
|
|
#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
|
|
|
|
|
#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
|
|
|
|
|
#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
|
2006-07-04 12:16:28 +08:00
|
|
|
#define _CHRP_briq 0x07 /* TotalImpact's briQ */
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-03-28 20:15:54 +08:00
|
|
|
#if defined(__KERNEL__) && defined(CONFIG_PPC32)
|
|
|
|
|
|
|
|
|
|
extern int _chrp_type;
|
2005-11-10 10:37:51 +08:00
|
|
|
|
2006-03-28 20:15:54 +08:00
|
|
|
#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
2019-01-31 18:08:48 +08:00
|
|
|
#include <asm/task_size_64.h>
|
2017-03-30 19:05:21 +08:00
|
|
|
#else
|
2019-01-31 18:08:48 +08:00
|
|
|
#include <asm/task_size_32.h>
|
2017-03-30 19:05:21 +08:00
|
|
|
#endif
|
|
|
|
|
|
2019-01-31 18:08:48 +08:00
|
|
|
struct task_struct;
|
|
|
|
|
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
|
|
|
|
|
void release_thread(struct task_struct *);
|
2008-02-08 20:19:26 +08:00
|
|
|
|
2013-09-10 18:20:42 +08:00
|
|
|
#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
|
2016-09-23 14:18:25 +08:00
|
|
|
#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
|
2013-09-10 18:20:42 +08:00
|
|
|
|
|
|
|
|
/* FP and VSX 0-31 register set */
|
|
|
|
|
struct thread_fp_state {
|
|
|
|
|
u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
|
|
|
|
|
u64 fpscr; /* Floating point status */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Complete AltiVec register set including VSCR */
|
|
|
|
|
struct thread_vr_state {
|
|
|
|
|
vector128 vr[32] __attribute__((aligned(16)));
|
|
|
|
|
vector128 vscr __attribute__((aligned(16)));
|
|
|
|
|
};
|
2008-06-26 15:07:48 +08:00
|
|
|
|
2013-07-04 14:15:46 +08:00
|
|
|
struct debug_reg {
|
2010-02-08 19:53:26 +08:00
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
|
|
|
/*
|
|
|
|
|
* The following help to manage the use of Debug Control Registers
|
|
|
|
|
* om the BookE platforms.
|
|
|
|
|
*/
|
2013-05-22 12:20:58 +08:00
|
|
|
uint32_t dbcr0;
|
|
|
|
|
uint32_t dbcr1;
|
2010-02-08 19:53:26 +08:00
|
|
|
#ifdef CONFIG_BOOKE
|
2013-05-22 12:20:58 +08:00
|
|
|
uint32_t dbcr2;
|
2010-02-08 19:53:26 +08:00
|
|
|
#endif
|
|
|
|
|
/*
|
|
|
|
|
* The stored value of the DBSR register will be the value at the
|
|
|
|
|
* last debug interrupt. This register can only be read from the
|
|
|
|
|
* user (will never be written to) and has value while helping to
|
|
|
|
|
* describe the reason for the last debug trap. Torez
|
|
|
|
|
*/
|
2013-05-22 12:20:58 +08:00
|
|
|
uint32_t dbsr;
|
2010-02-08 19:53:26 +08:00
|
|
|
/*
|
|
|
|
|
* The following will contain addresses used by debug applications
|
|
|
|
|
* to help trace and trap on particular address locations.
|
|
|
|
|
* The bits in the Debug Control Registers above help define which
|
|
|
|
|
* of the following registers will contain valid data and/or addresses.
|
|
|
|
|
*/
|
|
|
|
|
unsigned long iac1;
|
|
|
|
|
unsigned long iac2;
|
|
|
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
|
|
|
|
unsigned long iac3;
|
|
|
|
|
unsigned long iac4;
|
|
|
|
|
#endif
|
|
|
|
|
unsigned long dac1;
|
|
|
|
|
unsigned long dac2;
|
|
|
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
|
|
|
unsigned long dvc1;
|
|
|
|
|
unsigned long dvc2;
|
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif
|
2013-07-04 14:15:46 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct thread_struct {
|
|
|
|
|
unsigned long ksp; /* Kernel stack pointer */
|
2013-06-26 13:42:22 +08:00
|
|
|
|
2013-07-04 14:15:46 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
unsigned long ksp_vsid;
|
|
|
|
|
#endif
|
|
|
|
|
struct pt_regs *regs; /* Pointer to saved register state */
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
/* BookE base exception scratch space; align on cacheline */
|
|
|
|
|
unsigned long normsave[8] ____cacheline_aligned;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_PPC32
|
|
|
|
|
void *pgdir; /* root of page-table tree */
|
2019-02-21 18:37:54 +08:00
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
|
|
|
unsigned long rtas_sp; /* stack pointer for when in RTAS */
|
|
|
|
|
#endif
|
2019-03-11 16:30:38 +08:00
|
|
|
#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
|
|
|
|
|
unsigned long kuap; /* opened segments for user access */
|
2019-12-21 16:32:27 +08:00
|
|
|
#endif
|
|
|
|
|
unsigned long srr0;
|
|
|
|
|
unsigned long srr1;
|
|
|
|
|
unsigned long dar;
|
|
|
|
|
unsigned long dsisr;
|
powerpc/32s: Fix DSI and ISI exceptions for CONFIG_VMAP_STACK
hash_page() needs to read page tables from kernel memory. When entire
kernel memory is mapped by BATs, which is normally the case when
CONFIG_STRICT_KERNEL_RWX is not set, it works even if the page hosting
the page table is not referenced in the MMU hash table.
However, if the page where the page table resides is not covered by
a BAT, a DSI fault can be encountered from hash_page(), and it loops
forever. This can happen when CONFIG_STRICT_KERNEL_RWX is selected
and the alignment of the different regions is too small to allow
covering the entire memory with BATs. This also happens when
CONFIG_DEBUG_PAGEALLOC is selected or when booting with 'nobats'
flag.
Also, if the page containing the kernel stack is not present in the
MMU hash table, registers cannot be saved and a recursive DSI fault
is encountered.
To allow hash_page() to properly do its job at all time and load the
MMU hash table whenever needed, it must run with data MMU disabled.
This means it must be called before re-enabling data MMU. To allow
this, registers clobbered by hash_page() and create_hpte() have to
be saved in the thread struct together with SRR0, SSR1, DAR and DSISR.
It is also necessary to ensure that DSI prolog doesn't overwrite
regs saved by prolog of the current running exception. That means:
- DSI can only use SPRN_SPRG_SCRATCH0
- Exceptions must free SPRN_SPRG_SCRATCH0 before writing to the stack.
This also fixes the Oops reported by Erhard when create_hpte() is
called by add_hash_page().
Due to prolog size increase, a few more exceptions had to get split
in two parts.
Fixes: cd08f109e262 ("powerpc/32s: Enable CONFIG_VMAP_STACK")
Reported-by: Erhard F. <erhard_f@mailbox.org>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Tested-by: Erhard F. <erhard_f@mailbox.org>
Tested-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206501
Link: https://lore.kernel.org/r/64a4aa44686e9fd4b01333401367029771d9b231.1581761633.git.christophe.leroy@c-s.fr
2020-02-15 18:14:25 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
|
|
|
|
unsigned long r0, r3, r4, r5, r6, r8, r9, r11;
|
|
|
|
|
unsigned long lr, ctr;
|
|
|
|
|
#endif
|
2021-03-12 20:50:22 +08:00
|
|
|
#endif /* CONFIG_PPC32 */
|
2013-06-26 13:42:22 +08:00
|
|
|
/* Debug Registers */
|
2013-07-04 14:15:46 +08:00
|
|
|
struct debug_reg debug;
|
2020-08-19 01:19:17 +08:00
|
|
|
#ifdef CONFIG_PPC_FPU_REGS
|
2013-09-10 18:20:42 +08:00
|
|
|
struct thread_fp_state fp_state;
|
2013-09-10 18:21:10 +08:00
|
|
|
struct thread_fp_state *fp_save_area;
|
2020-08-19 01:19:17 +08:00
|
|
|
#endif
|
2005-10-10 12:19:43 +08:00
|
|
|
int fpexc_mode; /* floating-point exception mode */
|
2006-06-07 14:15:39 +08:00
|
|
|
unsigned int align_ctl; /* alignment handling control */
|
2010-06-15 14:05:19 +08:00
|
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
2020-05-14 19:17:28 +08:00
|
|
|
struct perf_event *ptrace_bps[HBP_NUM_MAX];
|
2010-06-15 14:05:19 +08:00
|
|
|
/*
|
|
|
|
|
* Helps identify source of single-step exception and subsequent
|
|
|
|
|
* hw-breakpoint enablement
|
|
|
|
|
*/
|
2020-05-14 19:17:38 +08:00
|
|
|
struct perf_event *last_hit_ubp[HBP_NUM_MAX];
|
2010-06-15 14:05:19 +08:00
|
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
2020-05-14 19:17:34 +08:00
|
|
|
struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
|
2012-08-24 05:27:09 +08:00
|
|
|
unsigned long trap_nr; /* last trap # on this thread */
|
powerpc/64s/hash: Add a SLB preload cache
When switching processes, currently all user SLBEs are cleared, and a
few (exec_base, pc, and stack) are preloaded. In trivial testing with
small apps, this tends to miss the heap and low 256MB segments, and it
will also miss commonly accessed segments on large memory workloads.
Add a simple round-robin preload cache that just inserts the last SLB
miss into the head of the cache and preloads those at context switch
time. Every 256 context switches, the oldest entry is removed from the
cache to shrink the cache and require fewer slbmte if they are unused.
Much more could go into this, including into the SLB entry reclaim
side to track some LRU information etc, which would require a study of
large memory workloads. But this is a simple thing we can do now that
is an obvious win for common workloads.
With the full series, process switching speed on the context_switch
benchmark on POWER9/hash (with kernel speculation security masures
disabled) increases from 140K/s to 178K/s (27%).
POWER8 does not change much (within 1%), it's unclear why it does not
see a big gain like POWER9.
Booting to busybox init with 256MB segments has SLB misses go down
from 945 to 69, and with 1T segments 900 to 21. These could almost all
be eliminated by preloading a bit more carefully with ELF binary
loading.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-09-14 23:30:56 +08:00
|
|
|
u8 load_slb; /* Ages out SLB preload cache entries */
|
2016-02-29 14:53:47 +08:00
|
|
|
u8 load_fp;
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
2016-02-29 14:53:47 +08:00
|
|
|
u8 load_vec;
|
2013-09-10 18:20:42 +08:00
|
|
|
struct thread_vr_state vr_state;
|
2013-09-10 18:21:10 +08:00
|
|
|
struct thread_vr_state *vr_save_area;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long vrsave;
|
|
|
|
|
int used_vr; /* set if process has used altivec */
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
2008-06-25 12:07:18 +08:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
/* VSR status */
|
2016-03-25 01:12:21 +08:00
|
|
|
int used_vsr; /* set if process has used VSX */
|
2008-06-25 12:07:18 +08:00
|
|
|
#endif /* CONFIG_VSX */
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
|
unsigned long evr[32]; /* upper 32-bits of SPE regs */
|
|
|
|
|
u64 acc; /* Accumulator */
|
|
|
|
|
unsigned long spefscr; /* SPE & eFP status */
|
powerpc: fix exception clearing in e500 SPE float emulation
The e500 SPE floating-point emulation code clears existing exceptions
(__FPU_FPSCR &= ~FP_EX_MASK;) before ORing in the exceptions from the
emulated operation. However, these exception bits are the "sticky",
cumulative exception bits, and should only be cleared by the user
program setting SPEFSCR, not implicitly by any floating-point
instruction (whether executed purely by the hardware or emulated).
The spurious clearing of these bits shows up as missing exceptions in
glibc testing.
Fixing this, however, is not as simple as just not clearing the bits,
because while the bits may be from previous floating-point operations
(in which case they should not be cleared), the processor can also set
the sticky bits itself before the interrupt for an exception occurs,
and this can happen in cases when IEEE 754 semantics are that the
sticky bit should not be set. Specifically, the "invalid" sticky bit
is set in various cases with non-finite operands, where IEEE 754
semantics do not involve raising such an exception, and the
"underflow" sticky bit is set in cases of exact underflow, whereas
IEEE 754 semantics are that this flag is set only for inexact
underflow. Thus, for correct emulation the kernel needs to know the
setting of these two sticky bits before the instruction being
emulated.
When a floating-point operation raises an exception, the kernel can
note the state of the sticky bits immediately afterwards. Some
<fenv.h> functions that affect the state of these bits, such as
fesetenv and feholdexcept, need to use prctl with PR_GET_FPEXC and
PR_SET_FPEXC anyway, and so it is natural to record the state of those
bits during that call into the kernel and so avoid any need for a
separate call into the kernel to inform it of a change to those bits.
Thus, the interface I chose to use (in this patch and the glibc port)
is that one of those prctl calls must be made after any userspace
change to those sticky bits, other than through a floating-point
operation that traps into the kernel anyway. feclearexcept and
fesetexceptflag duly make those calls, which would not be required
were it not for this issue.
The previous EGLIBC port, and the uClibc code copied from it, is
fundamentally broken as regards any use of prctl for floating-point
exceptions because it didn't use the PR_FP_EXC_SW_ENABLE bit in its
prctl calls (and did various worse things, such as passing a pointer
when prctl expected an integer). If you avoid anything where prctl is
used, the clearing of sticky bits still means it will never give
anything approximating correct exception semantics with existing
kernels. I don't believe the patch makes things any worse for
existing code that doesn't try to inform the kernel of changes to
sticky bits - such code may get incorrect exceptions in some cases,
but it would have done so anyway in other cases.
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-12-11 07:07:45 +08:00
|
|
|
unsigned long spefscr_last; /* SPEFSCR value on last prctl
|
|
|
|
|
call or trap return */
|
2005-04-17 06:20:36 +08:00
|
|
|
int used_spe; /* set if process has used spe */
|
|
|
|
|
#endif /* CONFIG_SPE */
|
2013-02-14 00:21:31 +08:00
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
2016-09-14 16:02:16 +08:00
|
|
|
u8 load_tm;
|
2013-02-14 00:21:31 +08:00
|
|
|
u64 tm_tfhar; /* Transaction fail handler addr */
|
|
|
|
|
u64 tm_texasr; /* Transaction exception & summary */
|
|
|
|
|
u64 tm_tfiar; /* Transaction fail instr address reg */
|
|
|
|
|
struct pt_regs ckpt_regs; /* Checkpointed registers */
|
|
|
|
|
|
2013-08-09 15:29:31 +08:00
|
|
|
unsigned long tm_tar;
|
|
|
|
|
unsigned long tm_ppr;
|
|
|
|
|
unsigned long tm_dscr;
|
2020-09-19 23:00:25 +08:00
|
|
|
unsigned long tm_amr;
|
2013-08-09 15:29:31 +08:00
|
|
|
|
2013-02-14 00:21:31 +08:00
|
|
|
/*
|
2016-09-23 14:18:24 +08:00
|
|
|
* Checkpointed FP and VSX 0-31 register set.
|
2013-02-14 00:21:31 +08:00
|
|
|
*
|
|
|
|
|
* When a transaction is active/signalled/scheduled etc., *regs is the
|
|
|
|
|
* most recent set of/speculated GPRs with ckpt_regs being the older
|
|
|
|
|
* checkpointed regs to which we roll back if transaction aborts.
|
|
|
|
|
*
|
2016-09-23 14:18:24 +08:00
|
|
|
* These are analogous to how ckpt_regs and pt_regs work
|
2013-02-14 00:21:31 +08:00
|
|
|
*/
|
2016-09-23 14:18:25 +08:00
|
|
|
struct thread_fp_state ckfp_state; /* Checkpointed FP state */
|
|
|
|
|
struct thread_vr_state ckvr_state; /* Checkpointed VR state */
|
|
|
|
|
unsigned long ckvrsave; /* Checkpointed VRSAVE */
|
2013-02-14 00:21:31 +08:00
|
|
|
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
|
2010-04-16 06:11:51 +08:00
|
|
|
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
|
|
|
|
|
void* kvm_shadow_vcpu; /* KVM internal data */
|
|
|
|
|
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
|
2011-12-20 23:34:43 +08:00
|
|
|
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
|
|
|
|
|
struct kvm_vcpu *kvm_vcpu;
|
|
|
|
|
#endif
|
2011-03-02 23:18:48 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
unsigned long dscr;
|
2015-10-29 08:43:55 +08:00
|
|
|
unsigned long fscr;
|
2015-05-21 14:43:04 +08:00
|
|
|
/*
|
|
|
|
|
* This member element dscr_inherit indicates that the process
|
|
|
|
|
* has explicitly attempted and changed the DSCR register value
|
|
|
|
|
* for itself. Hence kernel wont use the default CPU DSCR value
|
|
|
|
|
* contained in the PACA structure anymore during process context
|
|
|
|
|
* switch. Once this variable is set, this behaviour will also be
|
|
|
|
|
* inherited to all the children of this process from that point
|
|
|
|
|
* onwards.
|
|
|
|
|
*/
|
2011-03-02 23:18:48 +08:00
|
|
|
int dscr_inherit;
|
2017-11-08 10:23:53 +08:00
|
|
|
unsigned long tidr;
|
2011-03-02 23:18:48 +08:00
|
|
|
#endif
|
2013-02-07 23:46:58 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
unsigned long tar;
|
2013-05-01 04:17:04 +08:00
|
|
|
unsigned long ebbrr;
|
|
|
|
|
unsigned long ebbhr;
|
|
|
|
|
unsigned long bescr;
|
2013-05-22 00:31:12 +08:00
|
|
|
unsigned long siar;
|
|
|
|
|
unsigned long sdar;
|
|
|
|
|
unsigned long sier;
|
|
|
|
|
unsigned long mmcr2;
|
2013-06-28 16:15:16 +08:00
|
|
|
unsigned mmcr0;
|
2017-11-08 10:23:54 +08:00
|
|
|
|
2013-06-28 16:15:16 +08:00
|
|
|
unsigned used_ebb;
|
2020-07-17 22:38:16 +08:00
|
|
|
unsigned long mmcr3;
|
|
|
|
|
unsigned long sier2;
|
|
|
|
|
unsigned long sier3;
|
|
|
|
|
|
2013-02-07 23:46:58 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define ARCH_MIN_TASKALIGN 16
|
|
|
|
|
|
|
|
|
|
#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
|
2019-01-31 18:09:00 +08:00
|
|
|
#define INIT_SP_LIMIT ((unsigned long)&init_stack)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-10-28 11:50:21 +08:00
|
|
|
#ifdef CONFIG_SPE
|
powerpc: fix exception clearing in e500 SPE float emulation
The e500 SPE floating-point emulation code clears existing exceptions
(__FPU_FPSCR &= ~FP_EX_MASK;) before ORing in the exceptions from the
emulated operation. However, these exception bits are the "sticky",
cumulative exception bits, and should only be cleared by the user
program setting SPEFSCR, not implicitly by any floating-point
instruction (whether executed purely by the hardware or emulated).
The spurious clearing of these bits shows up as missing exceptions in
glibc testing.
Fixing this, however, is not as simple as just not clearing the bits,
because while the bits may be from previous floating-point operations
(in which case they should not be cleared), the processor can also set
the sticky bits itself before the interrupt for an exception occurs,
and this can happen in cases when IEEE 754 semantics are that the
sticky bit should not be set. Specifically, the "invalid" sticky bit
is set in various cases with non-finite operands, where IEEE 754
semantics do not involve raising such an exception, and the
"underflow" sticky bit is set in cases of exact underflow, whereas
IEEE 754 semantics are that this flag is set only for inexact
underflow. Thus, for correct emulation the kernel needs to know the
setting of these two sticky bits before the instruction being
emulated.
When a floating-point operation raises an exception, the kernel can
note the state of the sticky bits immediately afterwards. Some
<fenv.h> functions that affect the state of these bits, such as
fesetenv and feholdexcept, need to use prctl with PR_GET_FPEXC and
PR_SET_FPEXC anyway, and so it is natural to record the state of those
bits during that call into the kernel and so avoid any need for a
separate call into the kernel to inform it of a change to those bits.
Thus, the interface I chose to use (in this patch and the glibc port)
is that one of those prctl calls must be made after any userspace
change to those sticky bits, other than through a floating-point
operation that traps into the kernel anyway. feclearexcept and
fesetexceptflag duly make those calls, which would not be required
were it not for this issue.
The previous EGLIBC port, and the uClibc code copied from it, is
fundamentally broken as regards any use of prctl for floating-point
exceptions because it didn't use the PR_FP_EXC_SW_ENABLE bit in its
prctl calls (and did various worse things, such as passing a pointer
when prctl expected an integer). If you avoid anything where prctl is
used, the clearing of sticky bits still means it will never give
anything approximating correct exception semantics with existing
kernels. I don't believe the patch makes things any worse for
existing code that doesn't try to inform the kernel of changes to
sticky bits - such code may get incorrect exceptions in some cases,
but it would have done so anyway in other cases.
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-12-11 07:07:45 +08:00
|
|
|
#define SPEFSCR_INIT \
|
|
|
|
|
.spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
|
|
|
|
|
.spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
|
2008-10-28 11:50:21 +08:00
|
|
|
#else
|
|
|
|
|
#define SPEFSCR_INIT
|
|
|
|
|
#endif
|
2005-10-10 12:19:43 +08:00
|
|
|
|
powerpc/32s: Rework Kernel Userspace Access Protection
On book3s/32, KUAP is provided by toggling Ks bit in segment registers.
One segment register addresses 256M of virtual memory.
At the time being, KUAP implements a complex logic to apply the
unlock/lock on the exact number of segments covering the user range
to access, with saving the boundaries of the range of segments in
a member of thread struct.
But most if not all user accesses are within a single segment.
Rework KUAP with a different approach:
- Open only one segment, the one corresponding to the starting
address of the range to be accessed.
- If a second segment is involved, it will generate a page fault. The
segment will then be open by the page fault handler.
The kuap member of thread struct will now contain:
- The start address of the current on going user access, that will be
used to know which segment to lock at the end of the user access.
- ~0 when no user access is open
- ~1 when additionnal segments are opened by a page fault.
Then, at lock time
- When only one segment is open, close it.
- When several segments are open, close all user segments.
Almost 100% of the time, only one segment will be involved.
In interrupts, inline the function that unlock/lock all segments,
because not inlining them implies a lot of register save/restore.
With the patch, writing value 128 in userspace in perf_copy_attr() is
done with 16 instructions:
3890: 93 82 04 dc stw r28,1244(r2)
3894: 7d 20 e5 26 mfsrin r9,r28
3898: 55 29 00 80 rlwinm r9,r9,0,2,0
389c: 7d 20 e1 e4 mtsrin r9,r28
38a0: 4c 00 01 2c isync
38a4: 39 20 00 80 li r9,128
38a8: 91 3c 00 00 stw r9,0(r28)
38ac: 81 42 04 dc lwz r10,1244(r2)
38b0: 39 00 ff ff li r8,-1
38b4: 91 02 04 dc stw r8,1244(r2)
38b8: 2c 0a ff fe cmpwi r10,-2
38bc: 41 82 00 88 beq 3944 <perf_copy_attr+0x36c>
38c0: 7d 20 55 26 mfsrin r9,r10
38c4: 65 29 40 00 oris r9,r9,16384
38c8: 7d 20 51 e4 mtsrin r9,r10
38cc: 4c 00 01 2c isync
...
3944: 48 00 00 01 bl 3944 <perf_copy_attr+0x36c>
3944: R_PPC_REL24 kuap_lock_all_ool
Before the patch it was 118 instructions. In reality only 42 are
executed in most cases, but GCC is not able to see that a properly
aligned user access cannot involve more than one segment.
5060: 39 1d 00 04 addi r8,r29,4
5064: 3d 20 b0 00 lis r9,-20480
5068: 7c 08 48 40 cmplw r8,r9
506c: 40 81 00 08 ble 5074 <perf_copy_attr+0x2cc>
5070: 3d 00 b0 00 lis r8,-20480
5074: 39 28 ff ff addi r9,r8,-1
5078: 57 aa 00 06 rlwinm r10,r29,0,0,3
507c: 55 29 27 3e rlwinm r9,r9,4,28,31
5080: 39 29 00 01 addi r9,r9,1
5084: 7d 29 53 78 or r9,r9,r10
5088: 91 22 04 dc stw r9,1244(r2)
508c: 7d 20 ed 26 mfsrin r9,r29
5090: 55 29 00 80 rlwinm r9,r9,0,2,0
5094: 7c 08 50 40 cmplw r8,r10
5098: 40 81 00 c0 ble 5158 <perf_copy_attr+0x3b0>
509c: 7d 46 50 f8 not r6,r10
50a0: 7c c6 42 14 add r6,r6,r8
50a4: 54 c6 27 be rlwinm r6,r6,4,30,31
50a8: 7d 20 51 e4 mtsrin r9,r10
50ac: 3c ea 10 00 addis r7,r10,4096
50b0: 39 29 01 11 addi r9,r9,273
50b4: 7f 88 38 40 cmplw cr7,r8,r7
50b8: 55 29 02 06 rlwinm r9,r9,0,8,3
50bc: 40 9d 00 9c ble cr7,5158 <perf_copy_attr+0x3b0>
50c0: 2f 86 00 00 cmpwi cr7,r6,0
50c4: 41 9e 00 4c beq cr7,5110 <perf_copy_attr+0x368>
50c8: 2f 86 00 01 cmpwi cr7,r6,1
50cc: 41 9e 00 2c beq cr7,50f8 <perf_copy_attr+0x350>
50d0: 2f 86 00 02 cmpwi cr7,r6,2
50d4: 41 9e 00 14 beq cr7,50e8 <perf_copy_attr+0x340>
50d8: 7d 20 39 e4 mtsrin r9,r7
50dc: 39 29 01 11 addi r9,r9,273
50e0: 3c e7 10 00 addis r7,r7,4096
50e4: 55 29 02 06 rlwinm r9,r9,0,8,3
50e8: 7d 20 39 e4 mtsrin r9,r7
50ec: 39 29 01 11 addi r9,r9,273
50f0: 3c e7 10 00 addis r7,r7,4096
50f4: 55 29 02 06 rlwinm r9,r9,0,8,3
50f8: 7d 20 39 e4 mtsrin r9,r7
50fc: 3c e7 10 00 addis r7,r7,4096
5100: 39 29 01 11 addi r9,r9,273
5104: 7f 88 38 40 cmplw cr7,r8,r7
5108: 55 29 02 06 rlwinm r9,r9,0,8,3
510c: 40 9d 00 4c ble cr7,5158 <perf_copy_attr+0x3b0>
5110: 7d 20 39 e4 mtsrin r9,r7
5114: 39 29 01 11 addi r9,r9,273
5118: 3c c7 10 00 addis r6,r7,4096
511c: 55 29 02 06 rlwinm r9,r9,0,8,3
5120: 7d 20 31 e4 mtsrin r9,r6
5124: 39 29 01 11 addi r9,r9,273
5128: 3c c6 10 00 addis r6,r6,4096
512c: 55 29 02 06 rlwinm r9,r9,0,8,3
5130: 7d 20 31 e4 mtsrin r9,r6
5134: 39 29 01 11 addi r9,r9,273
5138: 3c c7 30 00 addis r6,r7,12288
513c: 55 29 02 06 rlwinm r9,r9,0,8,3
5140: 7d 20 31 e4 mtsrin r9,r6
5144: 3c e7 40 00 addis r7,r7,16384
5148: 39 29 01 11 addi r9,r9,273
514c: 7f 88 38 40 cmplw cr7,r8,r7
5150: 55 29 02 06 rlwinm r9,r9,0,8,3
5154: 41 9d ff bc bgt cr7,5110 <perf_copy_attr+0x368>
5158: 4c 00 01 2c isync
515c: 39 20 00 80 li r9,128
5160: 91 3d 00 00 stw r9,0(r29)
5164: 38 e0 00 00 li r7,0
5168: 90 e2 04 dc stw r7,1244(r2)
516c: 7d 20 ed 26 mfsrin r9,r29
5170: 65 29 40 00 oris r9,r9,16384
5174: 40 81 00 c0 ble 5234 <perf_copy_attr+0x48c>
5178: 7d 47 50 f8 not r7,r10
517c: 7c e7 42 14 add r7,r7,r8
5180: 54 e7 27 be rlwinm r7,r7,4,30,31
5184: 7d 20 51 e4 mtsrin r9,r10
5188: 3d 4a 10 00 addis r10,r10,4096
518c: 39 29 01 11 addi r9,r9,273
5190: 7c 08 50 40 cmplw r8,r10
5194: 55 29 02 06 rlwinm r9,r9,0,8,3
5198: 40 81 00 9c ble 5234 <perf_copy_attr+0x48c>
519c: 2c 07 00 00 cmpwi r7,0
51a0: 41 82 00 4c beq 51ec <perf_copy_attr+0x444>
51a4: 2c 07 00 01 cmpwi r7,1
51a8: 41 82 00 2c beq 51d4 <perf_copy_attr+0x42c>
51ac: 2c 07 00 02 cmpwi r7,2
51b0: 41 82 00 14 beq 51c4 <perf_copy_attr+0x41c>
51b4: 7d 20 51 e4 mtsrin r9,r10
51b8: 39 29 01 11 addi r9,r9,273
51bc: 3d 4a 10 00 addis r10,r10,4096
51c0: 55 29 02 06 rlwinm r9,r9,0,8,3
51c4: 7d 20 51 e4 mtsrin r9,r10
51c8: 39 29 01 11 addi r9,r9,273
51cc: 3d 4a 10 00 addis r10,r10,4096
51d0: 55 29 02 06 rlwinm r9,r9,0,8,3
51d4: 7d 20 51 e4 mtsrin r9,r10
51d8: 3d 4a 10 00 addis r10,r10,4096
51dc: 39 29 01 11 addi r9,r9,273
51e0: 7c 08 50 40 cmplw r8,r10
51e4: 55 29 02 06 rlwinm r9,r9,0,8,3
51e8: 40 81 00 4c ble 5234 <perf_copy_attr+0x48c>
51ec: 7d 20 51 e4 mtsrin r9,r10
51f0: 39 29 01 11 addi r9,r9,273
51f4: 3c ea 10 00 addis r7,r10,4096
51f8: 55 29 02 06 rlwinm r9,r9,0,8,3
51fc: 7d 20 39 e4 mtsrin r9,r7
5200: 39 29 01 11 addi r9,r9,273
5204: 3c e7 10 00 addis r7,r7,4096
5208: 55 29 02 06 rlwinm r9,r9,0,8,3
520c: 7d 20 39 e4 mtsrin r9,r7
5210: 39 29 01 11 addi r9,r9,273
5214: 3c ea 30 00 addis r7,r10,12288
5218: 55 29 02 06 rlwinm r9,r9,0,8,3
521c: 7d 20 39 e4 mtsrin r9,r7
5220: 3d 4a 40 00 addis r10,r10,16384
5224: 39 29 01 11 addi r9,r9,273
5228: 7c 08 50 40 cmplw r8,r10
522c: 55 29 02 06 rlwinm r9,r9,0,8,3
5230: 41 81 ff bc bgt 51ec <perf_copy_attr+0x444>
5234: 4c 00 01 2c isync
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
[mpe: Export the ool handlers to fix build errors]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/d9121f96a7c4302946839a0771f5d1daeeb6968c.1622708530.git.christophe.leroy@csgroup.eu
2021-06-03 16:41:44 +08:00
|
|
|
#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
|
|
|
|
|
#define INIT_THREAD { \
|
|
|
|
|
.ksp = INIT_SP, \
|
|
|
|
|
.pgdir = swapper_pg_dir, \
|
|
|
|
|
.kuap = ~0UL, /* KUAP_NONE */ \
|
|
|
|
|
.fpexc_mode = MSR_FE0 | MSR_FE1, \
|
|
|
|
|
SPEFSCR_INIT \
|
|
|
|
|
}
|
|
|
|
|
#elif defined(CONFIG_PPC32)
|
2005-04-17 06:20:36 +08:00
|
|
|
#define INIT_THREAD { \
|
|
|
|
|
.ksp = INIT_SP, \
|
|
|
|
|
.pgdir = swapper_pg_dir, \
|
|
|
|
|
.fpexc_mode = MSR_FE0 | MSR_FE1, \
|
2008-10-28 11:50:21 +08:00
|
|
|
SPEFSCR_INIT \
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2005-10-10 12:19:43 +08:00
|
|
|
#else
|
|
|
|
|
#define INIT_THREAD { \
|
|
|
|
|
.ksp = INIT_SP, \
|
[POWERPC] disable floating point exceptions for init
Floating point exceptions should not be enabled by default,
as this setting impacts the performance on some CPUs, in
particular the Cell BE. Since the bits are inherited from
parent processes, the place to change the default is the
thread struct used for init.
glibc sets this up correctly per thread in its fesetenv
function, so user space should not be impacted by this
setting. None of the other common libc implementations
(uClibc, dietlibc, newlib, klibc) has support for fp
exceptions, so they are unlikely to be hit by this either.
There is a small risk that somebody wrote their own
application that manually sets the fpscr bits instead
of calling fesetenv, without changing the MSR bits as well.
Those programs will break with this change.
It probably makes sense to change glibc in the future
to be more clever about FE bits, so that when running
on a CPU where this is expensive, it disables exceptions
ASAP, while it keeps them enabled on CPUs where running
with exceptions on is cheaper than changing the state
often.
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-20 08:30:33 +08:00
|
|
|
.fpexc_mode = 0, \
|
2005-10-10 12:19:43 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2020-04-28 20:31:52 +08:00
|
|
|
#define task_pt_regs(tsk) ((tsk)->thread.regs)
|
2008-07-07 22:22:27 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long get_wchan(struct task_struct *p);
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
|
|
|
|
|
#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* Get/set floating-point exception mode */
|
2005-10-10 12:19:43 +08:00
|
|
|
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
|
|
|
|
|
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
|
|
|
|
|
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
|
|
|
|
|
|
2006-06-07 14:14:40 +08:00
|
|
|
#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
|
|
|
|
|
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
|
|
|
|
|
|
|
|
|
|
extern int get_endian(struct task_struct *tsk, unsigned long adr);
|
|
|
|
|
extern int set_endian(struct task_struct *tsk, unsigned int val);
|
|
|
|
|
|
2006-06-07 14:15:39 +08:00
|
|
|
#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
|
|
|
|
|
#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
|
|
|
|
|
|
|
|
|
|
extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
|
|
|
|
|
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
|
|
|
|
|
|
2013-09-10 18:21:10 +08:00
|
|
|
extern void load_fp_state(struct thread_fp_state *fp);
|
|
|
|
|
extern void store_fp_state(struct thread_fp_state *fp);
|
|
|
|
|
extern void load_vr_state(struct thread_vr_state *vr);
|
|
|
|
|
extern void store_vr_state(struct thread_vr_state *vr);
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline unsigned int __unpack_fe01(unsigned long msr_bits)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline unsigned long __pack_fe01(unsigned int fpmode)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2017-06-06 21:08:31 +08:00
|
|
|
|
|
|
|
|
#define spin_begin() HMT_low()
|
|
|
|
|
|
|
|
|
|
#define spin_cpu_relax() barrier()
|
|
|
|
|
|
|
|
|
|
#define spin_end() HMT_medium()
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-03-27 08:46:18 +08:00
|
|
|
/* Check that a certain kernel stack pointer is valid in task_struct p */
|
|
|
|
|
int validate_sp(unsigned long sp, struct task_struct *p,
|
|
|
|
|
unsigned long nbytes);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* Prefetch macros.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCH_HAS_PREFETCH
|
|
|
|
|
#define ARCH_HAS_PREFETCHW
|
|
|
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline void prefetch(const void *x)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-10-10 12:19:43 +08:00
|
|
|
if (unlikely(!x))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
static inline void prefetchw(const void *x)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-10-10 12:19:43 +08:00
|
|
|
if (unlikely(!x))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define spin_lock_prefetch(x) prefetchw(x)
|
|
|
|
|
|
2005-10-10 12:19:43 +08:00
|
|
|
#define HAVE_ARCH_PICK_MMAP_LAYOUT
|
2005-04-17 06:20:36 +08:00
|
|
|
|
powerpc/64s: Reimplement book3s idle code in C
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack and reloading GPRs then
returning to C after waking from idle.
The complex logic dealing with threads and subcores, locking, SPRs,
HMIs, timebase resync, etc., is all done in C which makes it more
maintainable.
This is not a strict translation to C code, there are some
significant differences:
- Idle wakeup no longer uses the ->cpu_restore call to reinit SPRs,
but saves and restores them itself.
- The optimisation where EC=ESL=0 idle modes did not have to save GPRs
or change MSR is restored, because it's now simple to do. ESL=1
sleeps that do not lose GPRs can use this optimization too.
- KVM secondary entry and cede is now more of a call/return style
rather than branchy. nap_state_lost is not required because KVM
always returns via NVGPR restoring path.
- KVM secondary wakeup from offline sequence is moved entirely into
the offline wakeup, which avoids a hwsync in the normal idle wakeup
path.
Performance measured with context switch ping-pong on different
threads or cores, is possibly improved a small amount, 1-3% depending
on stop state and core vs thread test for shallow states. Deep states
it's in the noise compared with other latencies.
KVM improvements:
- Idle sleepers now always return to caller rather than branch out
to KVM first.
- This allows optimisations like very fast return to caller when no
state has been lost.
- KVM no longer requires nap_state_lost because it controls NVGPR
save/restore itself on the way in and out.
- The heavy idle wakeup KVM request check can be moved out of the
normal host idle code and into the not-performance-critical offline
code.
- KVM nap code now returns from where it is called, which makes the
flow a bit easier to follow.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Squash the KVM changes in]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-12 22:30:52 +08:00
|
|
|
/* asm stubs */
|
|
|
|
|
extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
|
|
|
|
|
extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
|
|
|
|
|
extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
|
2019-07-11 10:24:03 +08:00
|
|
|
#ifdef CONFIG_PPC_970_NAP
|
|
|
|
|
extern void power4_idle_nap(void);
|
2021-04-06 10:55:08 +08:00
|
|
|
void power4_idle_nap_return(void);
|
2019-07-11 10:24:03 +08:00
|
|
|
#endif
|
powerpc/64s: Reimplement book3s idle code in C
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack and reloading GPRs then
returning to C after waking from idle.
The complex logic dealing with threads and subcores, locking, SPRs,
HMIs, timebase resync, etc., is all done in C which makes it more
maintainable.
This is not a strict translation to C code, there are some
significant differences:
- Idle wakeup no longer uses the ->cpu_restore call to reinit SPRs,
but saves and restores them itself.
- The optimisation where EC=ESL=0 idle modes did not have to save GPRs
or change MSR is restored, because it's now simple to do. ESL=1
sleeps that do not lose GPRs can use this optimization too.
- KVM secondary entry and cede is now more of a call/return style
rather than branchy. nap_state_lost is not required because KVM
always returns via NVGPR restoring path.
- KVM secondary wakeup from offline sequence is moved entirely into
the offline wakeup, which avoids a hwsync in the normal idle wakeup
path.
Performance measured with context switch ping-pong on different
threads or cores, is possibly improved a small amount, 1-3% depending
on stop state and core vs thread test for shallow states. Deep states
it's in the noise compared with other latencies.
KVM improvements:
- Idle sleepers now always return to caller rather than branch out
to KVM first.
- This allows optimisations like very fast return to caller when no
state has been lost.
- KVM no longer requires nap_state_lost because it controls NVGPR
save/restore itself on the way in and out.
- The heavy idle wakeup KVM request check can be moved out of the
normal host idle code and into the not-performance-critical offline
code.
- KVM nap code now returns from where it is called, which makes the
flow a bit easier to follow.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Squash the KVM changes in]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-12 22:30:52 +08:00
|
|
|
|
2011-11-30 10:47:03 +08:00
|
|
|
extern unsigned long cpuidle_disable;
|
2011-11-30 10:46:31 +08:00
|
|
|
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
|
|
|
|
|
|
2012-03-29 01:30:02 +08:00
|
|
|
extern int powersave_nap; /* set if nap mode can be used in idle loop */
|
powerpc/64s: Reimplement book3s idle code in C
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack and reloading GPRs then
returning to C after waking from idle.
The complex logic dealing with threads and subcores, locking, SPRs,
HMIs, timebase resync, etc., is all done in C which makes it more
maintainable.
This is not a strict translation to C code, there are some
significant differences:
- Idle wakeup no longer uses the ->cpu_restore call to reinit SPRs,
but saves and restores them itself.
- The optimisation where EC=ESL=0 idle modes did not have to save GPRs
or change MSR is restored, because it's now simple to do. ESL=1
sleeps that do not lose GPRs can use this optimization too.
- KVM secondary entry and cede is now more of a call/return style
rather than branchy. nap_state_lost is not required because KVM
always returns via NVGPR restoring path.
- KVM secondary wakeup from offline sequence is moved entirely into
the offline wakeup, which avoids a hwsync in the normal idle wakeup
path.
Performance measured with context switch ping-pong on different
threads or cores, is possibly improved a small amount, 1-3% depending
on stop state and core vs thread test for shallow states. Deep states
it's in the noise compared with other latencies.
KVM improvements:
- Idle sleepers now always return to caller rather than branch out
to KVM first.
- This allows optimisations like very fast return to caller when no
state has been lost.
- KVM no longer requires nap_state_lost because it controls NVGPR
save/restore itself on the way in and out.
- The heavy idle wakeup KVM request check can be moved out of the
normal host idle code and into the not-performance-critical offline
code.
- KVM nap code now returns from where it is called, which makes the
flow a bit easier to follow.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Squash the KVM changes in]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-12 22:30:52 +08:00
|
|
|
|
2017-06-13 21:05:45 +08:00
|
|
|
extern void power7_idle_type(unsigned long type);
|
2020-08-19 17:47:00 +08:00
|
|
|
extern void arch300_idle_type(unsigned long stop_psscr_val,
|
2017-06-13 21:05:45 +08:00
|
|
|
unsigned long stop_psscr_mask);
|
2016-07-08 14:20:49 +08:00
|
|
|
|
2012-03-29 01:30:02 +08:00
|
|
|
extern int fix_alignment(struct pt_regs *);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
/*
|
|
|
|
|
* We handle most unaligned accesses in hardware. On the other hand
|
|
|
|
|
* unaligned DMA can be very expensive on some ppc64 IO chips (it does
|
|
|
|
|
* powers of 2 writes until it reaches sufficient alignment).
|
|
|
|
|
*
|
|
|
|
|
* Based on this we disable the IP header alignment in network drivers.
|
|
|
|
|
*/
|
|
|
|
|
#define NET_IP_ALIGN 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2021-03-15 20:00:09 +08:00
|
|
|
int do_mathemu(struct pt_regs *regs);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif /* __KERNEL__ */
|
2005-10-10 12:19:43 +08:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
#endif /* _ASM_POWERPC_PROCESSOR_H */
|