56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
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/*
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* m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
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*/
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#ifndef m54xxsim_h
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#define m54xxsim_h
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#define MCFINT_VECBASE 64
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/*
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* Interrupt Controller Registers
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*/
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#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
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#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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/*
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* Some PSC related definitions
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*/
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#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
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#define MCF_PAR_SDA (0x0008)
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#define MCF_PAR_SCL (0x0004)
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#define MCF_PAR_PSC_TXD (0x04)
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#define MCF_PAR_PSC_RXD (0x08)
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#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
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#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
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#define MCF_PAR_PSC_CTS_GPIO (0x00)
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#define MCF_PAR_PSC_CTS_BCLK (0x80)
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#define MCF_PAR_PSC_CTS_CTS (0xC0)
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#define MCF_PAR_PSC_RTS_GPIO (0x00)
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#define MCF_PAR_PSC_RTS_FSYNC (0x20)
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#define MCF_PAR_PSC_RTS_RTS (0x30)
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#define MCF_PAR_PSC_CANRX (0x40)
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#endif /* m54xxsim_h */
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