2019-05-27 14:55:06 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2011-03-17 16:40:29 +08:00
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/*
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* Copyright (C) 1999,2000 Arm Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* - add MX31 specific definitions
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/err.h>
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2016-06-24 18:49:58 +08:00
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#include <linux/io.h>
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2020-09-17 08:41:18 +08:00
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#include <linux/of_address.h>
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2012-05-02 19:31:20 +08:00
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#include <linux/pinctrl/machine.h>
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2011-03-17 16:40:29 +08:00
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2012-03-30 14:22:44 +08:00
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#include <asm/system_misc.h>
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2011-09-28 17:16:05 +08:00
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#include <asm/hardware/cache-l2x0.h>
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2011-03-17 16:40:29 +08:00
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#include <asm/mach/map.h>
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2012-09-13 21:01:00 +08:00
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#include "common.h"
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2012-04-03 18:42:27 +08:00
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#include "crmregs-imx3.h"
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2012-09-14 14:14:45 +08:00
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#include "hardware.h"
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2012-04-03 18:42:27 +08:00
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void __iomem *mx3_ccm_base;
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2011-09-28 17:16:06 +08:00
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static void imx3_idle(void)
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{
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unsigned long reg = 0;
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2011-11-11 13:09:18 +08:00
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2011-08-03 23:34:59 +08:00
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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2011-09-28 17:16:06 +08:00
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}
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2013-05-17 02:40:22 +08:00
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static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
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2012-02-14 03:24:15 +08:00
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unsigned int mtype, void *caller)
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2011-09-28 17:16:07 +08:00
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{
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if (mtype == MT_DEVICE) {
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/*
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* Access all peripherals below 0x80000000 as nonshared device
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* on mx3, but leave l2cc alone. Otherwise cache corruptions
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* can occur.
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*/
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if (phys_addr < 0x80000000 &&
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!addr_in_module(phys_addr, MX3x_L2CC))
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mtype = MT_DEVICE_NONSHARED;
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}
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2012-02-14 03:24:15 +08:00
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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2011-09-28 17:16:07 +08:00
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}
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2011-11-22 17:07:26 +08:00
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#ifdef CONFIG_SOC_IMX31
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2011-03-17 16:40:29 +08:00
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static struct map_desc mx31_io_desc[] __initdata = {
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imx_map_entry(MX31, X_MEMC, MT_DEVICE),
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imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
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imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
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imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
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imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
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};
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/*
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx31_map_io(void)
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{
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iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
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}
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2016-06-24 18:49:58 +08:00
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static void imx31_idle(void)
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{
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int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_LPM_MASK;
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imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
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imx3_idle();
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}
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2011-03-17 16:40:29 +08:00
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void __init imx31_init_early(void)
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{
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2020-09-17 08:41:18 +08:00
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struct device_node *np;
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2011-03-17 16:40:29 +08:00
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mxc_set_cpu_type(MXC_CPU_MX31);
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2012-02-14 03:24:15 +08:00
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arch_ioremap_caller = imx3_ioremap_caller;
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2016-06-24 18:49:58 +08:00
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arm_pm_idle = imx31_idle;
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2020-09-17 08:41:18 +08:00
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np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
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mx3_ccm_base = of_iomap(np, 0);
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BUG_ON(!mx3_ccm_base);
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2011-03-17 16:40:29 +08:00
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}
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void __init mx31_init_irq(void)
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{
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2020-09-17 08:41:19 +08:00
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void __iomem *avic_base;
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx31-avic");
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avic_base = of_iomap(np, 0);
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BUG_ON(!avic_base);
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mxc_init_irq(avic_base);
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2011-06-06 00:07:55 +08:00
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}
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2011-11-22 17:07:26 +08:00
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#endif /* ifdef CONFIG_SOC_IMX31 */
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#ifdef CONFIG_SOC_IMX35
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static struct map_desc mx35_io_desc[] __initdata = {
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imx_map_entry(MX35, X_MEMC, MT_DEVICE),
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imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
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imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
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imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
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imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
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};
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void __init mx35_map_io(void)
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{
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iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
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}
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2016-06-24 18:49:58 +08:00
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static void imx35_idle(void)
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{
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int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
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reg &= ~MXC_CCM_CCMR_LPM_MASK;
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reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
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imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
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imx3_idle();
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}
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2011-11-22 17:07:26 +08:00
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void __init imx35_init_early(void)
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{
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2020-09-17 08:41:18 +08:00
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struct device_node *np;
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2011-11-22 17:07:26 +08:00
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mxc_set_cpu_type(MXC_CPU_MX35);
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2016-06-24 18:49:58 +08:00
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arm_pm_idle = imx35_idle;
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2012-02-14 03:24:15 +08:00
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arch_ioremap_caller = imx3_ioremap_caller;
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2020-09-17 08:41:18 +08:00
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np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
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mx3_ccm_base = of_iomap(np, 0);
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BUG_ON(!mx3_ccm_base);
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2011-11-22 17:07:26 +08:00
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}
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void __init mx35_init_irq(void)
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{
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2020-09-17 08:41:19 +08:00
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void __iomem *avic_base;
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx35-avic");
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avic_base = of_iomap(np, 0);
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BUG_ON(!avic_base);
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mxc_init_irq(avic_base);
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2011-11-22 17:07:26 +08:00
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}
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#endif /* ifdef CONFIG_SOC_IMX35 */
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