2006-05-24 08:18:44 +08:00
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#
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# DMA engine configuration
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#
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2007-10-16 16:27:42 +08:00
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menuconfig DMADEVICES
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2007-11-29 08:21:43 +08:00
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bool "DMA Engine support"
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2009-06-04 05:22:28 +08:00
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depends on HAS_DMA
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2007-10-16 16:27:42 +08:00
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help
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2007-11-29 08:21:43 +08:00
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DMA engines can do asynchronous data transfers without
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involving the host CPU. Currently, this framework can be
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used to offload memory copies in the network stack and
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2008-06-27 16:21:11 +08:00
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RAID operations in the MD driver. This menu only presents
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DMA Device drivers supported by the configured arch, it may
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be empty in some cases.
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2007-10-16 16:27:42 +08:00
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2010-02-10 05:34:54 +08:00
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config DMADEVICES_DEBUG
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bool "DMA Engine debugging"
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depends on DMADEVICES != n
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help
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This is an option for use by developers; most people should
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say N here. This enables DMA engine core and driver debugging.
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config DMADEVICES_VDEBUG
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bool "DMA Engine verbose debugging"
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depends on DMADEVICES_DEBUG != n
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help
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This is an option for use by developers; most people should
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say N here. This enables deeper (more verbose) debugging of
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the DMA engine core and drivers.
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2007-10-16 16:27:42 +08:00
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if DMADEVICES
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comment "DMA Devices"
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2015-08-24 16:13:14 +08:00
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#core
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config ASYNC_TX_ENABLE_CHANNEL_SWITCH
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bool
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2014-07-12 05:04:21 +08:00
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2015-08-24 16:13:14 +08:00
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config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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bool
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2014-07-12 05:04:21 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_ENGINE
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2009-09-09 08:42:51 +08:00
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bool
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2015-08-24 16:13:14 +08:00
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config DMA_VIRTUAL_CHANNELS
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tristate
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config DMA_ACPI
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def_bool y
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depends on ACPI
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config DMA_OF
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def_bool y
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depends on OF
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select DMA_ENGINE
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#devices
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2010-09-28 21:57:37 +08:00
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config AMBA_PL08X
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bool "ARM PrimeCell PL080 or PL081 support"
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2012-10-24 04:01:54 +08:00
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depends on ARM_AMBA
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2010-09-28 21:57:37 +08:00
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select DMA_ENGINE
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2012-05-26 21:09:53 +08:00
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select DMA_VIRTUAL_CHANNELS
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2010-09-28 21:57:37 +08:00
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help
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Platform has a PL08x DMAC device
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which can provide DMA engine support
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2015-08-24 16:13:14 +08:00
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config AMCC_PPC440SPE_ADMA
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tristate "AMCC PPC440SPe ADMA support"
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depends on 440SPe || 440SP
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2007-10-16 16:27:42 +08:00
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select DMA_ENGINE
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2013-12-10 02:33:16 +08:00
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select DMA_ENGINE_RAID
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2015-08-24 16:13:14 +08:00
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select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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2010-10-08 07:44:50 +08:00
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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2007-10-16 16:27:42 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Enable support for the AMCC PPC440SPe RAID engines.
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2007-10-16 16:27:42 +08:00
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2009-07-04 01:24:33 +08:00
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config AT_HDMAC
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tristate "Atmel AHB DMA support"
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2012-03-15 18:31:58 +08:00
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depends on ARCH_AT91
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2009-07-04 01:24:33 +08:00
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select DMA_ENGINE
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help
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2012-03-15 18:31:58 +08:00
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Support the Atmel AHB DMA controller.
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2007-10-16 16:27:42 +08:00
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2014-10-22 23:22:18 +08:00
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config AT_XDMAC
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tristate "Atmel XDMA support"
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2014-11-13 18:52:39 +08:00
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depends on ARCH_AT91
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2014-10-22 23:22:18 +08:00
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select DMA_ENGINE
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help
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Support the Atmel XDMA controller.
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2007-10-16 16:27:42 +08:00
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2015-08-24 16:13:14 +08:00
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config AXI_DMAC
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tristate "Analog Devices AXI-DMAC DMA support"
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depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_SOCFPGA || COMPILE_TEST
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2007-10-16 16:27:42 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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2007-10-16 16:27:42 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
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controller is often used in Analog Device's reference designs for FPGA
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platforms.
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2006-05-24 08:18:44 +08:00
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2015-08-24 16:13:14 +08:00
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config COH901318
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bool "ST-Ericsson COH901318 DMA support"
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select DMA_ENGINE
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2016-09-02 17:59:49 +08:00
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depends on ARCH_U300 || COMPILE_TEST
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2015-08-24 16:13:14 +08:00
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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config DMA_BCM2835
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tristate "BCM2835 DMA engine support"
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depends on ARCH_BCM2835
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config DMA_JZ4740
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tristate "JZ4740 DMA support"
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2016-09-02 17:55:11 +08:00
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depends on MACH_JZ4740 || COMPILE_TEST
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2015-08-24 16:13:14 +08:00
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config DMA_JZ4780
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tristate "JZ4780 DMA support"
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2016-09-02 17:57:20 +08:00
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depends on MACH_JZ4780 || COMPILE_TEST
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2015-07-27 23:04:02 +08:00
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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2015-08-24 16:13:14 +08:00
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This selects support for the DMA controller in Ingenic JZ4780 SoCs.
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If you have a board based on such a SoC and wish to use DMA for
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devices which can use the DMA controller, say Y or M here.
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2015-07-27 23:04:02 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_OMAP
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tristate "OMAP DMA support"
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depends on ARCH_OMAP
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select TI_DMA_CROSSBAR if SOC_DRA7XX
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2012-10-26 04:38:05 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_SA11X0
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tristate "SA-11x0 DMA support"
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2016-09-02 18:01:42 +08:00
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depends on ARCH_SA1100 || COMPILE_TEST
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2009-07-04 01:24:33 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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2009-07-04 01:24:33 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Support the DMA engine found on Intel StrongARM SA-1100 and
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SA-1110 SoCs. This DMA engine can only be used with on-chip
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devices.
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2009-07-04 01:24:33 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_SUN4I
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tristate "Allwinner A10 DMA SoCs support"
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2015-09-05 02:10:18 +08:00
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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2015-08-24 16:13:14 +08:00
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default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
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2014-10-22 23:22:18 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_OF
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select DMA_VIRTUAL_CHANNELS
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2014-10-22 23:22:18 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Enable support for the DMA controller present in the sun4i,
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sun5i and sun7i Allwinner ARM SoCs.
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config DMA_SUN6I
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tristate "Allwinner A31 SoCs DMA support"
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depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST
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depends on RESET_CONTROLLER
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support for the DMA engine first found in Allwinner A31 SoCs.
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config EP93XX_DMA
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bool "Cirrus Logic EP93xx DMA support"
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2016-09-02 18:08:43 +08:00
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depends on ARCH_EP93XX || COMPILE_TEST
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2015-08-24 16:13:14 +08:00
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select DMA_ENGINE
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help
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Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
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2014-10-22 23:22:18 +08:00
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2008-03-01 22:42:48 +08:00
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config FSL_DMA
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2013-09-26 17:33:43 +08:00
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tristate "Freescale Elo series DMA support"
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2008-09-27 08:00:11 +08:00
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depends on FSL_SOC
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2008-03-01 22:42:48 +08:00
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select DMA_ENGINE
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2010-10-08 07:44:50 +08:00
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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2008-03-01 22:42:48 +08:00
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---help---
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2013-09-26 17:33:43 +08:00
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Enable support for the Freescale Elo series DMA controllers.
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The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
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EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
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some Txxx and Bxxx parts.
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2008-03-01 22:42:48 +08:00
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2015-08-24 16:13:14 +08:00
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config FSL_EDMA
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tristate "Freescale eDMA engine support"
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depends on OF
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support the Freescale eDMA engine with programmable channel
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multiplexing capability for DMA request sources(slot).
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This module can be found on Freescale Vybrid and LS-1 SoCs.
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2015-03-03 14:26:22 +08:00
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config FSL_RAID
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tristate "Freescale RAID engine Support"
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depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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---help---
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Enable support for Freescale RAID Engine. RAID Engine is
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available on some QorIQ SoCs (like P5020/P5040). It has
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the capability to offload memcpy, xor and pq computation
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for raid5/6.
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2015-08-24 16:13:14 +08:00
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config IMG_MDC_DMA
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tristate "IMG MDC support"
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depends on MIPS || COMPILE_TEST
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depends on MFD_SYSCON
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2010-02-05 11:42:52 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for the IMG multi-threaded DMA controller (MDC).
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2012-10-12 23:52:45 +08:00
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2015-08-24 16:13:14 +08:00
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config IMX_DMA
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tristate "i.MX DMA support"
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2011-08-24 14:41:09 +08:00
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depends on ARCH_MXC
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2008-07-09 02:58:36 +08:00
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select DMA_ENGINE
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i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Support the i.MX DMA engine. This engine is integrated into
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Freescale i.MX1/21/27 chips.
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2008-07-09 02:58:36 +08:00
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2015-08-24 16:13:14 +08:00
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config IMX_SDMA
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tristate "i.MX SDMA support"
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2011-08-24 14:41:09 +08:00
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depends on ARCH_MXC
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i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
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select DMA_ENGINE
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help
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2015-08-24 16:13:14 +08:00
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Support the i.MX SDMA engine. This engine is integrated into
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Freescale i.MX25/31/35/51/53/6 chips.
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i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
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2015-09-22 00:48:45 +08:00
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config INTEL_IDMA64
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2015-09-05 02:10:18 +08:00
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tristate "Intel integrated DMA 64-bit support"
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
help
|
2015-09-05 02:10:18 +08:00
|
|
|
Enable DMA support for Intel Low Power Subsystem such as found on
|
|
|
|
|
Intel Skylake PCH.
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config INTEL_IOATDMA
|
|
|
|
|
tristate "Intel I/OAT DMA support"
|
|
|
|
|
depends on PCI && X86_64
|
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 05:29:20 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select DCA
|
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 05:29:20 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the Intel(R) I/OAT DMA engine present
|
|
|
|
|
in recent Intel Xeon chipsets.
|
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 05:29:20 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
Say Y here if you have such a chipset.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config INTEL_IOP_ADMA
|
|
|
|
|
tristate "Intel IOP ADMA support"
|
|
|
|
|
depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
|
2009-04-22 23:40:30 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2009-04-22 23:40:30 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the Intel(R) IOP Series RAID engines.
|
2009-04-22 23:40:30 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config INTEL_MIC_X100_DMA
|
|
|
|
|
tristate "Intel MIC X100 DMA Driver"
|
|
|
|
|
depends on 64BIT && X86 && INTEL_MIC_BUS
|
2012-06-06 13:25:27 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
This enables DMA support for the Intel Many Integrated Core
|
|
|
|
|
(MIC) family of PCIe form factor coprocessor X100 devices that
|
|
|
|
|
run a 64 bit Linux OS. This driver will be used by both MIC
|
|
|
|
|
host and card drivers.
|
2012-06-06 13:25:27 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
If you are building host kernel with a MIC device or a card
|
|
|
|
|
kernel for a MIC device, then say M (recommended) or Y, else
|
|
|
|
|
say N. If unsure say N.
|
|
|
|
|
|
|
|
|
|
More information about the Intel MIC family as well as the Linux
|
|
|
|
|
OS and tools for MIC to use with this driver are available from
|
|
|
|
|
<http://software.intel.com/en-us/mic-developer>.
|
|
|
|
|
|
|
|
|
|
config K3_DMA
|
|
|
|
|
tristate "Hisilicon K3 DMA support"
|
|
|
|
|
depends on ARCH_HI3xxx
|
2013-10-08 05:42:10 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the DMA engine for Hisilicon K3 platform
|
|
|
|
|
devices.
|
2013-10-08 05:42:10 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config LPC18XX_DMAMUX
|
|
|
|
|
bool "NXP LPC18xx/43xx DMA MUX for PL080"
|
|
|
|
|
depends on ARCH_LPC18XX || COMPILE_TEST
|
|
|
|
|
depends on OF && AMBA_PL08X
|
|
|
|
|
select MFD_SYSCON
|
|
|
|
|
help
|
|
|
|
|
Enable support for DMA on NXP LPC18xx/43xx platforms
|
|
|
|
|
with PL080 and multiplexed DMA request lines.
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MMP_PDMA
|
|
|
|
|
bool "MMP PDMA support"
|
2016-09-02 18:25:56 +08:00
|
|
|
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
|
2009-11-20 02:49:17 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the MMP PDMA engine for PXA and MMP platform.
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MMP_TDMA
|
|
|
|
|
bool "MMP Two-Channel DMA support"
|
2016-09-02 18:27:09 +08:00
|
|
|
depends on ARCH_MMP || COMPILE_TEST
|
2010-03-30 21:33:42 +08:00
|
|
|
select DMA_ENGINE
|
2016-09-02 18:27:09 +08:00
|
|
|
select MMP_SRAM if ARCH_MMP
|
2010-03-30 21:33:42 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the MMP Two-Channel DMA engine.
|
|
|
|
|
This engine used for MMP Audio DMA and pxa910 SQU.
|
|
|
|
|
It needs sram driver under mach-mmp.
|
2010-03-30 21:33:42 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MOXART_DMA
|
|
|
|
|
tristate "MOXART DMA support"
|
|
|
|
|
depends on ARCH_MOXART
|
2009-12-12 12:24:44 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_OF
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
2009-12-12 12:24:44 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the MOXA ART SoC DMA controller.
|
|
|
|
|
|
|
|
|
|
Say Y here if you enabled MMP ADMA, otherwise say N.
|
2009-12-12 12:24:44 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MPC512X_DMA
|
|
|
|
|
tristate "Freescale MPC512x built-in DMA engine support"
|
|
|
|
|
depends on PPC_MPC512x || PPC_MPC831x
|
2010-03-26 02:44:21 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
---help---
|
|
|
|
|
Enable support for the Freescale MPC512x built-in DMA engine.
|
2010-03-26 02:44:21 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MV_XOR
|
|
|
|
|
bool "Marvell XOR engine support"
|
2016-04-29 15:49:08 +08:00
|
|
|
depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
|
2011-10-28 10:22:39 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
|
|
|
|
---help---
|
|
|
|
|
Enable support for the Marvell XOR engine.
|
2011-10-28 10:22:39 +08:00
|
|
|
|
2016-06-16 20:28:34 +08:00
|
|
|
config MV_XOR_V2
|
|
|
|
|
bool "Marvell XOR engine version 2 support "
|
|
|
|
|
depends on ARM64
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
|
|
|
|
select GENERIC_MSI_IRQ_DOMAIN
|
|
|
|
|
---help---
|
|
|
|
|
Enable support for the Marvell version 2 XOR engine.
|
|
|
|
|
|
|
|
|
|
This engine provides acceleration for copy, XOR and RAID6
|
|
|
|
|
operations, and is available on Marvell Armada 7K and 8K
|
|
|
|
|
platforms.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MXS_DMA
|
|
|
|
|
bool "MXS DMA support"
|
2016-02-11 21:19:54 +08:00
|
|
|
depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q || SOC_IMX6UL
|
2015-08-24 16:13:14 +08:00
|
|
|
select STMP_DEVICE
|
2011-10-28 10:22:39 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the MXS DMA engine. This engine including APBH-DMA
|
2016-02-11 21:19:54 +08:00
|
|
|
and APBX-DMA is integrated into Freescale
|
|
|
|
|
i.MX23/28/MX6Q/MX6DL/MX6UL chips.
|
2011-10-28 10:22:39 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MX3_IPU
|
|
|
|
|
bool "MX3x Image Processing Unit support"
|
|
|
|
|
depends on ARCH_MXC
|
2012-08-23 09:09:34 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
default y
|
2012-08-23 09:09:34 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
If you plan to use the Image Processing unit in the i.MX3x, say
|
|
|
|
|
Y here. If unsure, select Y.
|
2015-04-09 17:35:49 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MX3_IPU_IRQS
|
|
|
|
|
int "Number of dynamically mapped interrupts for IPU"
|
|
|
|
|
depends on MX3_IPU
|
|
|
|
|
range 2 137
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
|
|
|
|
|
To avoid bloating the irq_desc[] array we allocate a sufficient
|
|
|
|
|
number of IRQ slots and map them dynamically to specific sources.
|
2009-12-12 12:24:44 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config NBPFAXI_DMA
|
|
|
|
|
tristate "Renesas Type-AXI NBPF DMA support"
|
2010-05-24 11:28:19 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
depends on ARM || COMPILE_TEST
|
2010-05-24 11:28:19 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support for "Type-AXI" NBPF DMA IPs from Renesas
|
2010-05-24 11:28:19 +08:00
|
|
|
|
2010-07-30 16:23:03 +08:00
|
|
|
config PCH_DMA
|
2011-11-17 15:14:23 +08:00
|
|
|
tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
|
2014-05-16 22:17:37 +08:00
|
|
|
depends on PCI && (X86_32 || COMPILE_TEST)
|
2010-07-30 16:23:03 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2011-01-05 16:43:52 +08:00
|
|
|
Enable support for Intel EG20T PCH DMA engine.
|
|
|
|
|
|
2011-11-17 15:14:22 +08:00
|
|
|
This driver also can be used for LAPIS Semiconductor IOH(Input/
|
2011-11-17 15:14:23 +08:00
|
|
|
Output Hub), ML7213, ML7223 and ML7831.
|
|
|
|
|
ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
|
|
|
|
|
for MP(Media Phone) use and ML7831 IOH is for general purpose use.
|
|
|
|
|
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
|
|
|
|
|
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
|
2010-07-30 16:23:03 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config PL330_DMA
|
|
|
|
|
tristate "DMA API Driver for PL330"
|
2010-09-30 21:56:34 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
depends on ARM_AMBA
|
2010-09-30 21:56:34 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Select if your platform has one or more PL330 DMACs.
|
|
|
|
|
You need to provide platform specific settings via
|
|
|
|
|
platform_data for a dma-pl330 device.
|
2010-09-30 21:56:34 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config PXA_DMA
|
|
|
|
|
bool "PXA DMA support"
|
|
|
|
|
depends on (ARCH_MMP || ARCH_PXA)
|
2010-10-06 16:25:55 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
2010-10-06 16:25:55 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the DMA engine for PXA. It is also compatible with MMP PDMA
|
|
|
|
|
platform. The internal DMA IP of all PXA variants is supported, with
|
|
|
|
|
16 to 32 channels for peripheral to memory or memory to memory
|
|
|
|
|
transfers.
|
2010-10-06 16:25:55 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config SIRF_DMA
|
|
|
|
|
tristate "CSR SiRFprimaII/SiRFmarco DMA support"
|
|
|
|
|
depends on ARCH_SIRF
|
2011-02-27 00:47:42 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the CSR SiRFprimaII DMA engine.
|
2011-02-27 00:47:42 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config STE_DMA40
|
|
|
|
|
bool "ST-Ericsson DMA40 support"
|
|
|
|
|
depends on ARCH_U8500
|
2011-05-29 18:10:02 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support for ST-Ericsson DMA40 controller
|
2011-05-29 18:10:02 +08:00
|
|
|
|
2015-10-16 21:59:14 +08:00
|
|
|
config STM32_DMA
|
|
|
|
|
bool "STMicroelectronics STM32 DMA support"
|
2016-09-02 18:27:51 +08:00
|
|
|
depends on ARCH_STM32 || COMPILE_TEST
|
2015-10-16 21:59:14 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the on-chip DMA controller on STMicroelectronics
|
|
|
|
|
STM32 MCUs.
|
|
|
|
|
If you have a board based on such a MCU and wish to use DMA say Y or M
|
|
|
|
|
here.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config S3C24XX_DMAC
|
2015-11-19 05:31:11 +08:00
|
|
|
bool "Samsung S3C24XX DMA support"
|
2015-08-24 16:13:14 +08:00
|
|
|
depends on ARCH_S3C24XX
|
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 05:44:07 +08:00
|
|
|
select DMA_ENGINE
|
2012-04-13 19:07:23 +08:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 05:44:07 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support for the Samsung S3C24XX DMA controller driver. The
|
|
|
|
|
DMA controller is having multiple DMA channels which can be
|
|
|
|
|
configured for different peripherals like audio, UART, SPI.
|
|
|
|
|
The DMA controller can transfer data from memory to peripheral,
|
|
|
|
|
periphal to memory, periphal to periphal and memory to memory.
|
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 05:44:07 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TXX9_DMAC
|
|
|
|
|
tristate "Toshiba TXx9 SoC DMA support"
|
|
|
|
|
depends on MACH_TX49XX || MACH_TX39XX
|
2012-06-15 11:04:08 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the TXx9 SoC internal DMA controller. This can be
|
|
|
|
|
integrated in chips such as the Toshiba TX4927/38/39.
|
2012-06-15 11:04:08 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TEGRA20_APB_DMA
|
|
|
|
|
bool "NVIDIA Tegra20 APB DMA support"
|
|
|
|
|
depends on ARCH_TEGRA
|
2012-04-13 19:10:24 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
help
|
|
|
|
|
Support for the NVIDIA Tegra20 APB DMA controller driver. The
|
|
|
|
|
DMA controller is having multiple DMA channel which can be
|
|
|
|
|
configured for different peripherals like audio, UART, SPI,
|
|
|
|
|
I2C etc which is in APB bus.
|
|
|
|
|
This DMA controller transfers data from memory to peripheral fifo
|
|
|
|
|
or vice versa. It does not support memory to memory data transfer.
|
2012-04-13 19:10:24 +08:00
|
|
|
|
2016-05-13 01:02:23 +08:00
|
|
|
config TEGRA210_ADMA
|
|
|
|
|
bool "NVIDIA Tegra210 ADMA support"
|
|
|
|
|
depends on ARCH_TEGRA_210_SOC
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
select PM_CLK
|
|
|
|
|
help
|
|
|
|
|
Support for the NVIDIA Tegra210 ADMA controller driver. The
|
|
|
|
|
DMA controller has multiple DMA channels and is used to service
|
|
|
|
|
various audio clients in the Tegra210 audio processing engine
|
|
|
|
|
(APE). This DMA controller transfers data from memory to
|
|
|
|
|
peripheral and vice versa. It does not support memory to
|
|
|
|
|
memory data transfer.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TIMB_DMA
|
|
|
|
|
tristate "Timberdale FPGA DMA support"
|
|
|
|
|
depends on MFD_TIMBERDALE
|
2014-01-07 03:18:24 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
help
|
|
|
|
|
Enable support for the Timberdale FPGA DMA engine.
|
2014-01-07 03:18:24 +08:00
|
|
|
|
2013-06-20 18:13:04 +08:00
|
|
|
config TI_CPPI41
|
|
|
|
|
tristate "AM33xx CPPI41 DMA support"
|
|
|
|
|
depends on ARCH_OMAP
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
The Communications Port Programming Interface (CPPI) 4.1 DMA engine
|
|
|
|
|
is currently used by the USB driver on AM335x platforms.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TI_DMA_CROSSBAR
|
|
|
|
|
bool
|
2015-03-19 00:16:36 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TI_EDMA
|
|
|
|
|
bool "TI EDMA support"
|
|
|
|
|
depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE
|
2013-08-27 10:20:10 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
2015-10-16 15:18:09 +08:00
|
|
|
select TI_DMA_CROSSBAR if ARCH_OMAP
|
2015-08-24 16:13:14 +08:00
|
|
|
default n
|
2013-08-27 10:20:10 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the TI EDMA controller. This DMA
|
|
|
|
|
engine is found on TI DaVinci and AM33xx parts.
|
2013-08-27 10:20:10 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config XGENE_DMA
|
|
|
|
|
tristate "APM X-Gene DMA support"
|
|
|
|
|
depends on ARCH_XGENE || COMPILE_TEST
|
2014-02-18 10:17:12 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2014-02-18 10:17:12 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the APM X-Gene SoC DMA engine.
|
2014-01-17 16:46:05 +08:00
|
|
|
|
2016-06-24 13:21:25 +08:00
|
|
|
config XILINX_DMA
|
|
|
|
|
tristate "Xilinx AXI DMAS Engine"
|
2016-04-06 13:08:08 +08:00
|
|
|
depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
|
2014-04-23 22:53:26 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for Xilinx AXI VDMA Soft IP.
|
|
|
|
|
|
2016-06-24 13:21:25 +08:00
|
|
|
AXI VDMA engine provides high-bandwidth direct memory access
|
2014-04-23 22:53:26 +08:00
|
|
|
between memory and AXI4-Stream video type target
|
|
|
|
|
peripherals including peripherals which support AXI4-
|
|
|
|
|
Stream Video Protocol. It has two stream interfaces/
|
|
|
|
|
channels, Memory Mapped to Stream (MM2S) and Stream to
|
|
|
|
|
Memory Mapped (S2MM) for the data transfers.
|
2016-06-24 13:21:25 +08:00
|
|
|
AXI CDMA engine provides high-bandwidth direct memory access
|
|
|
|
|
between a memory-mapped source address and a memory-mapped
|
|
|
|
|
destination address.
|
|
|
|
|
AXI DMA engine provides high-bandwidth one dimensional direct
|
|
|
|
|
memory access between memory and AXI4-Stream target peripherals.
|
2014-04-23 22:53:26 +08:00
|
|
|
|
2016-07-01 19:37:06 +08:00
|
|
|
config XILINX_ZYNQMP_DMA
|
|
|
|
|
tristate "Xilinx ZynqMP DMA Engine"
|
|
|
|
|
depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for Xilinx ZynqMP DMA controller.
|
2014-04-23 22:53:26 +08:00
|
|
|
|
2015-05-05 22:06:08 +08:00
|
|
|
config ZX_DMA
|
|
|
|
|
tristate "ZTE ZX296702 DMA support"
|
|
|
|
|
depends on ARCH_ZX
|
2014-12-12 06:59:17 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
2015-05-05 22:06:08 +08:00
|
|
|
Support the DMA engine for ZTE ZX296702 platform devices.
|
2014-12-12 06:59:17 +08:00
|
|
|
|
2015-03-18 21:47:34 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
# driver files
|
|
|
|
|
source "drivers/dma/bestcomm/Kconfig"
|
2006-05-24 08:18:44 +08:00
|
|
|
|
2016-02-05 12:34:32 +08:00
|
|
|
source "drivers/dma/qcom/Kconfig"
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
source "drivers/dma/dw/Kconfig"
|
2012-04-13 19:07:23 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
source "drivers/dma/hsu/Kconfig"
|
2013-04-09 19:05:43 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
source "drivers/dma/sh/Kconfig"
|
2013-02-13 01:15:02 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
# clients
|
2006-06-18 12:24:58 +08:00
|
|
|
comment "DMA Clients"
|
2007-10-16 16:27:42 +08:00
|
|
|
depends on DMA_ENGINE
|
2006-06-18 12:24:58 +08:00
|
|
|
|
2009-03-26 00:13:25 +08:00
|
|
|
config ASYNC_TX_DMA
|
|
|
|
|
bool "Async_tx: Offload support for the async_tx api"
|
2009-09-09 06:06:10 +08:00
|
|
|
depends on DMA_ENGINE
|
2009-03-26 00:13:25 +08:00
|
|
|
help
|
|
|
|
|
This allows the async_tx api to take advantage of offload engines for
|
|
|
|
|
memcpy, memset, xor, and raid6 p+q operations. If your platform has
|
|
|
|
|
a dma engine that can perform raid operations and you have enabled
|
|
|
|
|
MD_RAID456 say Y.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2008-07-09 02:58:45 +08:00
|
|
|
config DMATEST
|
|
|
|
|
tristate "DMA Test client"
|
|
|
|
|
depends on DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Simple DMA test client. Say N unless you're debugging a
|
|
|
|
|
DMA Device driver.
|
|
|
|
|
|
2013-12-10 02:33:16 +08:00
|
|
|
config DMA_ENGINE_RAID
|
|
|
|
|
bool
|
|
|
|
|
|
2007-10-16 16:27:42 +08:00
|
|
|
endif
|