2012-05-10 02:37:20 +08:00
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eugeni Dodonov <eugeni.dodonov@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "intel_drv.h"
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2014-08-27 21:27:30 +08:00
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struct ddi_buf_trans {
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u32 trans1; /* balance leg enable, de-emph level */
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u32 trans2; /* vref sel, vswing */
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};
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2012-05-10 02:37:20 +08:00
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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
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* them for both DP and FDI transports, allowing those ports to
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* automatically adapt to HDMI connections as well
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*/
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
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{ 0x00FFFFFF, 0x0006000E },
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{ 0x00D75FFF, 0x0005000A },
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{ 0x00C30FFF, 0x00040006 },
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{ 0x80AAAFFF, 0x000B0000 },
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{ 0x00FFFFFF, 0x0005000A },
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{ 0x00D75FFF, 0x000C0004 },
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{ 0x80C30FFF, 0x000B0000 },
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{ 0x00FFFFFF, 0x00040006 },
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{ 0x80D75FFF, 0x000B0000 },
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2012-05-10 02:37:20 +08:00
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};
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
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{ 0x00FFFFFF, 0x0007000E },
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{ 0x00D75FFF, 0x000F000A },
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{ 0x00C30FFF, 0x00060006 },
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{ 0x00AAAFFF, 0x001E0000 },
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{ 0x00FFFFFF, 0x000F000A },
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{ 0x00D75FFF, 0x00160004 },
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{ 0x00C30FFF, 0x001E0000 },
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{ 0x00FFFFFF, 0x00060006 },
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{ 0x00D75FFF, 0x001E0000 },
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2013-09-13 04:06:24 +08:00
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};
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
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/* Idx NT mV d T mV d db */
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{ 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
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{ 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
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{ 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
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{ 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
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{ 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
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{ 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
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{ 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
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{ 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
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{ 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
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{ 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
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{ 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
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{ 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
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2012-05-10 02:37:20 +08:00
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};
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
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{ 0x00FFFFFF, 0x00000012 },
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{ 0x00EBAFFF, 0x00020011 },
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{ 0x00C71FFF, 0x0006000F },
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{ 0x00AAAFFF, 0x000E000A },
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{ 0x00FFFFFF, 0x00020011 },
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{ 0x00DB6FFF, 0x0005000F },
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{ 0x00BEEFFF, 0x000A000C },
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{ 0x00FFFFFF, 0x0005000F },
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{ 0x00DB6FFF, 0x000A000C },
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2013-11-03 12:07:42 +08:00
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};
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
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{ 0x00FFFFFF, 0x0007000E },
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{ 0x00D75FFF, 0x000E000A },
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{ 0x00BEFFFF, 0x00140006 },
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{ 0x80B2CFFF, 0x001B0002 },
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{ 0x00FFFFFF, 0x000E000A },
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2014-09-25 08:32:43 +08:00
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{ 0x00DB6FFF, 0x00160005 },
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2014-09-26 00:28:32 +08:00
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{ 0x80C71FFF, 0x001A0002 },
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2014-08-27 21:27:30 +08:00
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{ 0x00F7DFFF, 0x00180004 },
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{ 0x80D75FFF, 0x001B0002 },
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2013-11-03 12:07:41 +08:00
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};
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
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{ 0x00FFFFFF, 0x0001000E },
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{ 0x00D75FFF, 0x0004000A },
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{ 0x00C30FFF, 0x00070006 },
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{ 0x00AAAFFF, 0x000C0000 },
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{ 0x00FFFFFF, 0x0004000A },
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{ 0x00D75FFF, 0x00090004 },
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{ 0x00C30FFF, 0x000C0000 },
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{ 0x00FFFFFF, 0x00070006 },
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{ 0x00D75FFF, 0x000C0000 },
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2013-11-03 12:07:41 +08:00
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};
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2014-08-27 21:27:30 +08:00
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static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
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/* Idx NT mV d T mV df db */
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{ 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
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{ 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
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{ 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
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{ 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
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{ 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
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{ 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
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{ 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
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{ 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
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{ 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
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{ 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
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2014-08-01 18:07:55 +08:00
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};
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2013-12-03 21:56:25 +08:00
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static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
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2014-11-26 21:37:26 +08:00
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{ 0x00000018, 0x000000a2 },
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{ 0x00004014, 0x0000009B },
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2013-12-03 21:56:25 +08:00
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{ 0x00006012, 0x00000088 },
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2014-11-26 21:37:26 +08:00
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{ 0x00008010, 0x00000087 },
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{ 0x00000018, 0x0000009B },
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2013-12-03 21:56:25 +08:00
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{ 0x00004014, 0x00000088 },
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2014-11-26 21:37:26 +08:00
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{ 0x00006012, 0x00000087 },
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2013-12-03 21:56:25 +08:00
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{ 0x00000018, 0x00000088 },
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2014-11-26 21:37:26 +08:00
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{ 0x00004014, 0x00000087 },
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2013-12-03 21:56:25 +08:00
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};
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2015-02-25 12:59:12 +08:00
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/* eDP 1.4 low vswing translation parameters */
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static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
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{ 0x00000018, 0x000000a8 },
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{ 0x00002016, 0x000000ab },
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{ 0x00006012, 0x000000a2 },
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{ 0x00008010, 0x00000088 },
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{ 0x00000018, 0x000000ab },
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{ 0x00004014, 0x000000a2 },
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{ 0x00006012, 0x000000a6 },
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{ 0x00000018, 0x000000a2 },
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{ 0x00005013, 0x0000009c },
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{ 0x00000018, 0x00000088 },
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};
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2013-12-03 21:56:25 +08:00
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static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
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2015-04-15 13:32:33 +08:00
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{ 0x00000018, 0x000000ac },
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{ 0x00005012, 0x0000009d },
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{ 0x00007011, 0x00000088 },
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{ 0x00000018, 0x000000a1 },
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{ 0x00000018, 0x00000098 },
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{ 0x00004013, 0x00000088 },
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{ 0x00006012, 0x00000087 },
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{ 0x00000018, 0x000000df },
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{ 0x00003015, 0x00000087 },
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{ 0x00003015, 0x000000c7 },
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{ 0x00000018, 0x000000c7 },
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2013-12-03 21:56:25 +08:00
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};
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2014-11-18 18:15:27 +08:00
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struct bxt_ddi_buf_trans {
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u32 margin; /* swing value */
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u32 scale; /* scale value */
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u32 enable; /* scale enable */
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u32 deemphasis;
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bool default_index; /* true if the entry represents default value */
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};
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/* BSpec does not define separate vswing/pre-emphasis values for eDP.
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* Using DP values for eDP as well.
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*/
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static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
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/* Idx NT mV diff db */
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{ 52, 0, 0, 128, true }, /* 0: 400 0 */
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{ 78, 0, 0, 85, false }, /* 1: 400 3.5 */
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{ 104, 0, 0, 64, false }, /* 2: 400 6 */
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{ 154, 0, 0, 43, false }, /* 3: 400 9.5 */
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{ 77, 0, 0, 128, false }, /* 4: 600 0 */
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{ 116, 0, 0, 85, false }, /* 5: 600 3.5 */
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{ 154, 0, 0, 64, false }, /* 6: 600 6 */
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{ 102, 0, 0, 128, false }, /* 7: 800 0 */
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{ 154, 0, 0, 85, false }, /* 8: 800 3.5 */
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{ 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
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};
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/* BSpec has 2 recommended values - entries 0 and 8.
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* Using the entry with higher vswing.
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*/
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static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
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/* Idx NT mV diff db */
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{ 52, 0, 0, 128, false }, /* 0: 400 0 */
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{ 52, 0, 0, 85, false }, /* 1: 400 3.5 */
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{ 52, 0, 0, 64, false }, /* 2: 400 6 */
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{ 42, 0, 0, 43, false }, /* 3: 400 9.5 */
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{ 77, 0, 0, 128, false }, /* 4: 600 0 */
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{ 77, 0, 0, 85, false }, /* 5: 600 3.5 */
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{ 77, 0, 0, 64, false }, /* 6: 600 6 */
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{ 102, 0, 0, 128, false }, /* 7: 800 0 */
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{ 102, 0, 0, 85, false }, /* 8: 800 3.5 */
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{ 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
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};
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2015-04-18 00:31:21 +08:00
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static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
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struct intel_digital_port **dig_port,
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enum port *port)
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2012-10-05 23:05:54 +08:00
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{
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2012-10-16 02:51:38 +08:00
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struct drm_encoder *encoder = &intel_encoder->base;
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2012-10-05 23:05:54 +08:00
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int type = intel_encoder->type;
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2014-05-02 12:02:48 +08:00
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if (type == INTEL_OUTPUT_DP_MST) {
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2015-04-18 00:31:21 +08:00
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*dig_port = enc_to_mst(encoder)->primary;
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*port = (*dig_port)->port;
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2014-05-02 12:02:48 +08:00
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} else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
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2012-10-27 05:05:52 +08:00
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type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
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2015-04-18 00:31:21 +08:00
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*dig_port = enc_to_dig_port(encoder);
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*port = (*dig_port)->port;
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2012-10-05 23:05:54 +08:00
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} else if (type == INTEL_OUTPUT_ANALOG) {
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2015-04-18 00:31:21 +08:00
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*dig_port = NULL;
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*port = PORT_E;
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2012-10-05 23:05:54 +08:00
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} else {
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DRM_ERROR("Invalid DDI encoder type %d\n", type);
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BUG();
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}
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}
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2015-04-18 00:31:21 +08:00
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enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
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{
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struct intel_digital_port *dig_port;
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enum port port;
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ddi_get_encoder_port(intel_encoder, &dig_port, &port);
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return port;
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}
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2014-08-04 22:04:43 +08:00
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static bool
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intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
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{
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return intel_dig_port->hdmi.hdmi_reg;
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}
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2013-11-03 12:07:41 +08:00
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/*
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* Starting with Haswell, DDI port buffers must be programmed with correct
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* values in advance. The buffer values are different for FDI and DP modes,
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2012-05-10 02:37:20 +08:00
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* but the HDMI/DVI fields are shared among those. So we program the DDI
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* in either FDI or DP modes only, as HDMI connections will work with both
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* of those
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*/
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2015-04-18 00:31:22 +08:00
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static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
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bool supports_hdmi)
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2012-05-10 02:37:20 +08:00
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg;
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2015-03-03 00:19:36 +08:00
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int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
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2015-02-25 12:59:12 +08:00
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size;
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2013-09-13 04:06:24 +08:00
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int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
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2014-08-27 21:27:30 +08:00
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const struct ddi_buf_trans *ddi_translations_fdi;
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const struct ddi_buf_trans *ddi_translations_dp;
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const struct ddi_buf_trans *ddi_translations_edp;
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const struct ddi_buf_trans *ddi_translations_hdmi;
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const struct ddi_buf_trans *ddi_translations;
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2013-11-03 12:07:41 +08:00
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2014-11-18 18:15:27 +08:00
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if (IS_BROXTON(dev)) {
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2015-04-18 00:31:22 +08:00
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if (!supports_hdmi)
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2014-11-18 18:15:27 +08:00
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return;
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/* Vswing programming for HDMI */
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bxt_ddi_vswing_sequence(dev, hdmi_level, port,
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INTEL_OUTPUT_HDMI);
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return;
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} else if (IS_SKYLAKE(dev)) {
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2013-12-03 21:56:25 +08:00
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ddi_translations_fdi = NULL;
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ddi_translations_dp = skl_ddi_translations_dp;
|
2015-02-25 12:59:12 +08:00
|
|
|
n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
|
2015-05-06 20:05:48 +08:00
|
|
|
if (dev_priv->edp_low_vswing) {
|
2015-02-25 12:59:12 +08:00
|
|
|
ddi_translations_edp = skl_ddi_translations_edp;
|
|
|
|
n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
|
|
|
|
} else {
|
|
|
|
ddi_translations_edp = skl_ddi_translations_dp;
|
|
|
|
n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
|
|
|
|
}
|
|
|
|
|
2013-12-03 21:56:25 +08:00
|
|
|
ddi_translations_hdmi = skl_ddi_translations_hdmi;
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
|
2015-04-15 13:32:33 +08:00
|
|
|
hdmi_default_entry = 7;
|
2013-12-03 21:56:25 +08:00
|
|
|
} else if (IS_BROADWELL(dev)) {
|
2013-11-03 12:07:41 +08:00
|
|
|
ddi_translations_fdi = bdw_ddi_translations_fdi;
|
|
|
|
ddi_translations_dp = bdw_ddi_translations_dp;
|
2013-11-03 12:07:42 +08:00
|
|
|
ddi_translations_edp = bdw_ddi_translations_edp;
|
2014-08-01 18:07:55 +08:00
|
|
|
ddi_translations_hdmi = bdw_ddi_translations_hdmi;
|
2015-02-25 12:59:12 +08:00
|
|
|
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
|
|
|
|
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
|
2014-08-27 21:27:30 +08:00
|
|
|
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
|
2015-03-03 00:19:36 +08:00
|
|
|
hdmi_default_entry = 7;
|
2013-11-03 12:07:41 +08:00
|
|
|
} else if (IS_HASWELL(dev)) {
|
|
|
|
ddi_translations_fdi = hsw_ddi_translations_fdi;
|
|
|
|
ddi_translations_dp = hsw_ddi_translations_dp;
|
2013-11-03 12:07:42 +08:00
|
|
|
ddi_translations_edp = hsw_ddi_translations_dp;
|
2014-08-01 18:07:55 +08:00
|
|
|
ddi_translations_hdmi = hsw_ddi_translations_hdmi;
|
2015-02-25 12:59:12 +08:00
|
|
|
n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
|
2014-08-27 21:27:30 +08:00
|
|
|
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
|
2015-03-03 00:19:36 +08:00
|
|
|
hdmi_default_entry = 6;
|
2013-11-03 12:07:41 +08:00
|
|
|
} else {
|
|
|
|
WARN(1, "ddi translation table missing\n");
|
2013-11-03 12:07:42 +08:00
|
|
|
ddi_translations_edp = bdw_ddi_translations_dp;
|
2013-11-03 12:07:41 +08:00
|
|
|
ddi_translations_fdi = bdw_ddi_translations_fdi;
|
|
|
|
ddi_translations_dp = bdw_ddi_translations_dp;
|
2014-08-01 18:07:55 +08:00
|
|
|
ddi_translations_hdmi = bdw_ddi_translations_hdmi;
|
2015-02-25 12:59:12 +08:00
|
|
|
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
|
|
|
|
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
|
2014-08-27 21:27:30 +08:00
|
|
|
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
|
2015-03-03 00:19:36 +08:00
|
|
|
hdmi_default_entry = 7;
|
2013-11-03 12:07:41 +08:00
|
|
|
}
|
|
|
|
|
2013-11-03 12:07:42 +08:00
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
|
|
|
ddi_translations = ddi_translations_edp;
|
2015-02-25 12:59:12 +08:00
|
|
|
size = n_edp_entries;
|
2013-11-03 12:07:42 +08:00
|
|
|
break;
|
|
|
|
case PORT_B:
|
|
|
|
case PORT_C:
|
|
|
|
ddi_translations = ddi_translations_dp;
|
2015-02-25 12:59:12 +08:00
|
|
|
size = n_dp_entries;
|
2013-11-03 12:07:42 +08:00
|
|
|
break;
|
2013-11-03 12:07:45 +08:00
|
|
|
case PORT_D:
|
2015-02-25 12:59:12 +08:00
|
|
|
if (intel_dp_is_edp(dev, PORT_D)) {
|
2013-11-03 12:07:45 +08:00
|
|
|
ddi_translations = ddi_translations_edp;
|
2015-02-25 12:59:12 +08:00
|
|
|
size = n_edp_entries;
|
|
|
|
} else {
|
2013-11-03 12:07:45 +08:00
|
|
|
ddi_translations = ddi_translations_dp;
|
2015-02-25 12:59:12 +08:00
|
|
|
size = n_dp_entries;
|
|
|
|
}
|
2013-11-03 12:07:45 +08:00
|
|
|
break;
|
2013-11-03 12:07:42 +08:00
|
|
|
case PORT_E:
|
2013-12-03 21:56:25 +08:00
|
|
|
if (ddi_translations_fdi)
|
|
|
|
ddi_translations = ddi_translations_fdi;
|
|
|
|
else
|
|
|
|
ddi_translations = ddi_translations_dp;
|
2015-02-25 12:59:12 +08:00
|
|
|
size = n_dp_entries;
|
2013-11-03 12:07:42 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
2012-05-10 02:37:20 +08:00
|
|
|
|
2015-02-25 12:59:12 +08:00
|
|
|
for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
|
2014-08-27 21:27:30 +08:00
|
|
|
I915_WRITE(reg, ddi_translations[i].trans1);
|
|
|
|
reg += 4;
|
|
|
|
I915_WRITE(reg, ddi_translations[i].trans2);
|
2012-05-10 02:37:20 +08:00
|
|
|
reg += 4;
|
|
|
|
}
|
2014-08-01 18:07:54 +08:00
|
|
|
|
2015-04-18 00:31:22 +08:00
|
|
|
if (!supports_hdmi)
|
2014-08-04 22:04:43 +08:00
|
|
|
return;
|
|
|
|
|
2014-08-01 18:07:54 +08:00
|
|
|
/* Choose a good default if VBT is badly populated */
|
|
|
|
if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
|
|
|
|
hdmi_level >= n_hdmi_entries)
|
2015-03-03 00:19:36 +08:00
|
|
|
hdmi_level = hdmi_default_entry;
|
2014-08-01 18:07:54 +08:00
|
|
|
|
2013-09-13 04:06:24 +08:00
|
|
|
/* Entry 9 is for HDMI: */
|
2014-08-27 21:27:30 +08:00
|
|
|
I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
|
|
|
|
reg += 4;
|
|
|
|
I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
|
|
|
|
reg += 4;
|
2012-05-10 02:37:20 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Program DDI buffers translations for DP. By default, program ports A-D in DP
|
|
|
|
* mode and port E for FDI.
|
|
|
|
*/
|
|
|
|
void intel_prepare_ddi(struct drm_device *dev)
|
|
|
|
{
|
2015-04-18 00:31:22 +08:00
|
|
|
struct intel_encoder *intel_encoder;
|
2014-08-05 05:01:33 +08:00
|
|
|
bool visited[I915_MAX_PORTS] = { 0, };
|
2012-05-10 02:37:20 +08:00
|
|
|
|
2012-11-24 02:46:41 +08:00
|
|
|
if (!HAS_DDI(dev))
|
|
|
|
return;
|
2012-05-10 02:37:20 +08:00
|
|
|
|
2015-04-18 00:31:22 +08:00
|
|
|
for_each_intel_encoder(dev, intel_encoder) {
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
enum port port;
|
|
|
|
bool supports_hdmi;
|
|
|
|
|
|
|
|
ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
|
|
|
|
|
|
|
|
if (visited[port])
|
2014-08-05 05:01:33 +08:00
|
|
|
continue;
|
|
|
|
|
2015-04-18 00:31:22 +08:00
|
|
|
supports_hdmi = intel_dig_port &&
|
|
|
|
intel_dig_port_supports_hdmi(intel_dig_port);
|
|
|
|
|
|
|
|
intel_prepare_ddi_buffers(dev, port, supports_hdmi);
|
|
|
|
visited[port] = true;
|
2014-08-05 05:01:33 +08:00
|
|
|
}
|
2012-05-10 02:37:20 +08:00
|
|
|
}
|
2012-05-10 02:37:21 +08:00
|
|
|
|
2012-11-29 21:29:31 +08:00
|
|
|
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
uint32_t reg = DDI_BUF_CTL(port);
|
|
|
|
int i;
|
|
|
|
|
2015-03-27 20:19:09 +08:00
|
|
|
for (i = 0; i < 16; i++) {
|
2012-11-29 21:29:31 +08:00
|
|
|
udelay(1);
|
|
|
|
if (I915_READ(reg) & DDI_BUF_IS_IDLE)
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
|
|
|
|
}
|
2012-05-10 02:37:21 +08:00
|
|
|
|
|
|
|
/* Starting with Haswell, different DDI ports can work in FDI mode for
|
|
|
|
* connection to the PCH-located connectors. For this, it is necessary to train
|
|
|
|
* both the DDI port and PCH receiver for the desired DDI buffer settings.
|
|
|
|
*
|
|
|
|
* The recommended port to work in FDI mode is DDI E, which we use here. Also,
|
|
|
|
* please note that when FDI mode is active on DDI E, it shares 2 lines with
|
|
|
|
* DDI A (which is used for eDP)
|
|
|
|
*/
|
|
|
|
|
|
|
|
void hsw_fdi_link_train(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
u32 temp, i, rx_ctl_val;
|
2012-05-10 02:37:21 +08:00
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
|
|
|
|
* mode set "sequence for CRT port" document:
|
|
|
|
* - TP1 to TP2 time with the default value
|
|
|
|
* - FDI delay to 90h
|
2013-05-04 01:48:11 +08:00
|
|
|
*
|
|
|
|
* WaFDIAutoLinkSetTimingOverrride:hsw
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
*/
|
|
|
|
I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
|
|
|
|
FDI_RX_PWRDN_LANE0_VAL(2) |
|
|
|
|
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
|
|
|
|
|
|
|
|
/* Enable the PCH Receiver FDI PLL */
|
2012-12-12 02:48:29 +08:00
|
|
|
rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
|
2013-02-14 01:04:45 +08:00
|
|
|
FDI_RX_PLL_ENABLE |
|
2015-01-15 20:55:25 +08:00
|
|
|
FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
|
|
|
|
POSTING_READ(_FDI_RXA_CTL);
|
|
|
|
udelay(220);
|
|
|
|
|
|
|
|
/* Switch from Rawclk to PCDclk */
|
|
|
|
rx_ctl_val |= FDI_PCDCLK;
|
|
|
|
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
|
|
|
|
|
|
|
|
/* Configure Port Clock Select */
|
2015-01-15 20:55:25 +08:00
|
|
|
I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
|
|
|
|
WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
|
|
|
|
/* Start the training iterating through available voltages and emphasis,
|
|
|
|
* testing each value twice. */
|
2014-08-27 21:27:30 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
|
2012-05-10 02:37:21 +08:00
|
|
|
/* Configure DP_TP_CTL with auto-training */
|
|
|
|
I915_WRITE(DP_TP_CTL(PORT_E),
|
|
|
|
DP_TP_CTL_FDI_AUTOTRAIN |
|
|
|
|
DP_TP_CTL_ENHANCED_FRAME_ENABLE |
|
|
|
|
DP_TP_CTL_LINK_TRAIN_PAT1 |
|
|
|
|
DP_TP_CTL_ENABLE);
|
|
|
|
|
2012-12-12 02:48:30 +08:00
|
|
|
/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
|
|
|
|
* DDI E does not support port reversal, the functionality is
|
|
|
|
* achieved on the PCH side in FDI_RX_CTL, so no need to set the
|
|
|
|
* port reversal bit */
|
2012-05-10 02:37:21 +08:00
|
|
|
I915_WRITE(DDI_BUF_CTL(PORT_E),
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
DDI_BUF_CTL_ENABLE |
|
2015-01-15 20:55:25 +08:00
|
|
|
((intel_crtc->config->fdi_lanes - 1) << 1) |
|
2014-08-11 11:27:36 +08:00
|
|
|
DDI_BUF_TRANS_SELECT(i / 2));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
POSTING_READ(DDI_BUF_CTL(PORT_E));
|
2012-05-10 02:37:21 +08:00
|
|
|
|
|
|
|
udelay(600);
|
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
/* Program PCH FDI Receiver TU */
|
|
|
|
I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
|
|
|
|
|
|
|
|
/* Enable PCH FDI Receiver with auto-training */
|
|
|
|
rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
|
|
|
|
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
|
|
|
|
POSTING_READ(_FDI_RXA_CTL);
|
|
|
|
|
|
|
|
/* Wait for FDI receiver lane calibration */
|
|
|
|
udelay(30);
|
|
|
|
|
|
|
|
/* Unset FDI_RX_MISC pwrdn lanes */
|
|
|
|
temp = I915_READ(_FDI_RXA_MISC);
|
|
|
|
temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
|
|
|
I915_WRITE(_FDI_RXA_MISC, temp);
|
|
|
|
POSTING_READ(_FDI_RXA_MISC);
|
|
|
|
|
|
|
|
/* Wait for FDI auto training time */
|
|
|
|
udelay(5);
|
2012-05-10 02:37:21 +08:00
|
|
|
|
|
|
|
temp = I915_READ(DP_TP_STATUS(PORT_E));
|
|
|
|
if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
|
2012-05-10 02:37:21 +08:00
|
|
|
|
|
|
|
/* Enable normal pixel sending for FDI */
|
|
|
|
I915_WRITE(DP_TP_CTL(PORT_E),
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
DP_TP_CTL_FDI_AUTOTRAIN |
|
|
|
|
DP_TP_CTL_LINK_TRAIN_NORMAL |
|
|
|
|
DP_TP_CTL_ENHANCED_FRAME_ENABLE |
|
|
|
|
DP_TP_CTL_ENABLE);
|
2012-05-10 02:37:21 +08:00
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
return;
|
2012-05-10 02:37:21 +08:00
|
|
|
}
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
|
2012-11-29 21:29:31 +08:00
|
|
|
temp = I915_READ(DDI_BUF_CTL(PORT_E));
|
|
|
|
temp &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
|
|
|
|
POSTING_READ(DDI_BUF_CTL(PORT_E));
|
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
|
2012-11-29 21:29:31 +08:00
|
|
|
temp = I915_READ(DP_TP_CTL(PORT_E));
|
|
|
|
temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
I915_WRITE(DP_TP_CTL(PORT_E), temp);
|
|
|
|
POSTING_READ(DP_TP_CTL(PORT_E));
|
|
|
|
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
|
|
|
|
rx_ctl_val &= ~FDI_RX_ENABLE;
|
|
|
|
I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
|
2012-11-29 21:29:31 +08:00
|
|
|
POSTING_READ(_FDI_RXA_CTL);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
|
|
|
|
/* Reset FDI_RX_MISC pwrdn lanes */
|
|
|
|
temp = I915_READ(_FDI_RXA_MISC);
|
|
|
|
temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
|
|
|
temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
|
|
|
|
I915_WRITE(_FDI_RXA_MISC, temp);
|
2012-11-29 21:29:31 +08:00
|
|
|
POSTING_READ(_FDI_RXA_MISC);
|
2012-05-10 02:37:21 +08:00
|
|
|
}
|
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-02 07:00:59 +08:00
|
|
|
DRM_ERROR("FDI link training failed!\n");
|
2012-05-10 02:37:21 +08:00
|
|
|
}
|
2012-05-10 02:37:27 +08:00
|
|
|
|
2014-05-02 11:36:43 +08:00
|
|
|
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
enc_to_dig_port(&encoder->base);
|
|
|
|
|
|
|
|
intel_dp->DP = intel_dig_port->saved_port_bits |
|
2014-08-11 11:27:36 +08:00
|
|
|
DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
|
2014-05-02 11:36:43 +08:00
|
|
|
intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2012-10-05 23:05:53 +08:00
|
|
|
static struct intel_encoder *
|
|
|
|
intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct intel_encoder *intel_encoder, *ret = NULL;
|
|
|
|
int num_encoders = 0;
|
|
|
|
|
|
|
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
|
|
|
|
ret = intel_encoder;
|
|
|
|
num_encoders++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (num_encoders != 1)
|
2013-04-17 22:48:49 +08:00
|
|
|
WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
|
|
|
|
pipe_name(intel_crtc->pipe));
|
2012-10-05 23:05:53 +08:00
|
|
|
|
|
|
|
BUG_ON(ret == NULL);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-08-22 12:19:10 +08:00
|
|
|
struct intel_encoder *
|
2015-03-20 22:18:12 +08:00
|
|
|
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
|
2014-10-29 17:32:30 +08:00
|
|
|
{
|
2015-03-20 22:18:12 +08:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
|
|
struct intel_encoder *ret = NULL;
|
|
|
|
struct drm_atomic_state *state;
|
2015-04-21 22:12:59 +08:00
|
|
|
struct drm_connector *connector;
|
|
|
|
struct drm_connector_state *connector_state;
|
2014-10-29 17:32:30 +08:00
|
|
|
int num_encoders = 0;
|
2015-03-20 22:18:12 +08:00
|
|
|
int i;
|
2014-10-29 17:32:30 +08:00
|
|
|
|
2015-03-20 22:18:12 +08:00
|
|
|
state = crtc_state->base.state;
|
|
|
|
|
2015-04-21 22:12:59 +08:00
|
|
|
for_each_connector_in_state(state, connector, connector_state, i) {
|
|
|
|
if (connector_state->crtc != crtc_state->base.crtc)
|
2015-03-20 22:18:12 +08:00
|
|
|
continue;
|
|
|
|
|
2015-04-21 22:12:59 +08:00
|
|
|
ret = to_intel_encoder(connector_state->best_encoder);
|
2015-03-20 22:18:12 +08:00
|
|
|
num_encoders++;
|
2014-10-29 17:32:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
|
|
|
|
pipe_name(crtc->pipe));
|
|
|
|
|
|
|
|
BUG_ON(ret == NULL);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-05-10 21:01:51 +08:00
|
|
|
#define LC_FREQ 2700
|
2014-09-04 19:27:23 +08:00
|
|
|
#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
|
2013-05-10 21:01:51 +08:00
|
|
|
|
|
|
|
#define P_MIN 2
|
|
|
|
#define P_MAX 64
|
|
|
|
#define P_INC 2
|
|
|
|
|
|
|
|
/* Constraints for PLL good behavior */
|
|
|
|
#define REF_MIN 48
|
|
|
|
#define REF_MAX 400
|
|
|
|
#define VCO_MIN 2400
|
|
|
|
#define VCO_MAX 4800
|
|
|
|
|
2014-09-04 19:27:23 +08:00
|
|
|
#define abs_diff(a, b) ({ \
|
|
|
|
typeof(a) __a = (a); \
|
|
|
|
typeof(b) __b = (b); \
|
|
|
|
(void) (&__a == &__b); \
|
|
|
|
__a > __b ? (__a - __b) : (__b - __a); })
|
2013-05-10 21:01:51 +08:00
|
|
|
|
|
|
|
struct wrpll_rnp {
|
|
|
|
unsigned p, n2, r2;
|
|
|
|
};
|
|
|
|
|
|
|
|
static unsigned wrpll_get_budget_for_freq(int clock)
|
2012-10-05 23:05:58 +08:00
|
|
|
{
|
2013-05-10 21:01:51 +08:00
|
|
|
unsigned budget;
|
|
|
|
|
|
|
|
switch (clock) {
|
|
|
|
case 25175000:
|
|
|
|
case 25200000:
|
|
|
|
case 27000000:
|
|
|
|
case 27027000:
|
|
|
|
case 37762500:
|
|
|
|
case 37800000:
|
|
|
|
case 40500000:
|
|
|
|
case 40541000:
|
|
|
|
case 54000000:
|
|
|
|
case 54054000:
|
|
|
|
case 59341000:
|
|
|
|
case 59400000:
|
|
|
|
case 72000000:
|
|
|
|
case 74176000:
|
|
|
|
case 74250000:
|
|
|
|
case 81000000:
|
|
|
|
case 81081000:
|
|
|
|
case 89012000:
|
|
|
|
case 89100000:
|
|
|
|
case 108000000:
|
|
|
|
case 108108000:
|
|
|
|
case 111264000:
|
|
|
|
case 111375000:
|
|
|
|
case 148352000:
|
|
|
|
case 148500000:
|
|
|
|
case 162000000:
|
|
|
|
case 162162000:
|
|
|
|
case 222525000:
|
|
|
|
case 222750000:
|
|
|
|
case 296703000:
|
|
|
|
case 297000000:
|
|
|
|
budget = 0;
|
|
|
|
break;
|
|
|
|
case 233500000:
|
|
|
|
case 245250000:
|
|
|
|
case 247750000:
|
|
|
|
case 253250000:
|
|
|
|
case 298000000:
|
|
|
|
budget = 1500;
|
|
|
|
break;
|
|
|
|
case 169128000:
|
|
|
|
case 169500000:
|
|
|
|
case 179500000:
|
|
|
|
case 202000000:
|
|
|
|
budget = 2000;
|
|
|
|
break;
|
|
|
|
case 256250000:
|
|
|
|
case 262500000:
|
|
|
|
case 270000000:
|
|
|
|
case 272500000:
|
|
|
|
case 273750000:
|
|
|
|
case 280750000:
|
|
|
|
case 281250000:
|
|
|
|
case 286000000:
|
|
|
|
case 291750000:
|
|
|
|
budget = 4000;
|
|
|
|
break;
|
|
|
|
case 267250000:
|
|
|
|
case 268500000:
|
|
|
|
budget = 5000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
budget = 1000;
|
|
|
|
break;
|
|
|
|
}
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2013-05-10 21:01:51 +08:00
|
|
|
return budget;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
|
|
|
|
unsigned r2, unsigned n2, unsigned p,
|
|
|
|
struct wrpll_rnp *best)
|
|
|
|
{
|
|
|
|
uint64_t a, b, c, d, diff, diff_best;
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2013-05-10 21:01:51 +08:00
|
|
|
/* No best (r,n,p) yet */
|
|
|
|
if (best->p == 0) {
|
|
|
|
best->p = p;
|
|
|
|
best->n2 = n2;
|
|
|
|
best->r2 = r2;
|
|
|
|
return;
|
|
|
|
}
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2013-05-10 21:01:51 +08:00
|
|
|
/*
|
|
|
|
* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
|
|
|
|
* freq2k.
|
|
|
|
*
|
|
|
|
* delta = 1e6 *
|
|
|
|
* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
|
|
|
|
* freq2k;
|
|
|
|
*
|
|
|
|
* and we would like delta <= budget.
|
|
|
|
*
|
|
|
|
* If the discrepancy is above the PPM-based budget, always prefer to
|
|
|
|
* improve upon the previous solution. However, if you're within the
|
|
|
|
* budget, try to maximize Ref * VCO, that is N / (P * R^2).
|
|
|
|
*/
|
|
|
|
a = freq2k * budget * p * r2;
|
|
|
|
b = freq2k * budget * best->p * best->r2;
|
2014-09-04 19:27:23 +08:00
|
|
|
diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
|
|
|
|
diff_best = abs_diff(freq2k * best->p * best->r2,
|
|
|
|
LC_FREQ_2K * best->n2);
|
2013-05-10 21:01:51 +08:00
|
|
|
c = 1000000 * diff;
|
|
|
|
d = 1000000 * diff_best;
|
|
|
|
|
|
|
|
if (a < c && b < d) {
|
|
|
|
/* If both are above the budget, pick the closer */
|
|
|
|
if (best->p * best->r2 * diff < p * r2 * diff_best) {
|
|
|
|
best->p = p;
|
|
|
|
best->n2 = n2;
|
|
|
|
best->r2 = r2;
|
|
|
|
}
|
|
|
|
} else if (a >= c && b < d) {
|
|
|
|
/* If A is below the threshold but B is above it? Update. */
|
|
|
|
best->p = p;
|
|
|
|
best->n2 = n2;
|
|
|
|
best->r2 = r2;
|
|
|
|
} else if (a >= c && b >= d) {
|
|
|
|
/* Both are below the limit, so pick the higher n2/(r2*r2) */
|
|
|
|
if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
|
|
|
|
best->p = p;
|
|
|
|
best->n2 = n2;
|
|
|
|
best->r2 = r2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Otherwise a < c && b >= d, do nothing */
|
|
|
|
}
|
|
|
|
|
2014-01-22 04:42:10 +08:00
|
|
|
static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
|
|
|
|
int reg)
|
|
|
|
{
|
|
|
|
int refclk = LC_FREQ;
|
|
|
|
int n, p, r;
|
|
|
|
u32 wrpll;
|
|
|
|
|
|
|
|
wrpll = I915_READ(reg);
|
2014-06-26 03:01:48 +08:00
|
|
|
switch (wrpll & WRPLL_PLL_REF_MASK) {
|
|
|
|
case WRPLL_PLL_SSC:
|
|
|
|
case WRPLL_PLL_NON_SSC:
|
2014-01-22 04:42:10 +08:00
|
|
|
/*
|
|
|
|
* We could calculate spread here, but our checking
|
|
|
|
* code only cares about 5% accuracy, and spread is a max of
|
|
|
|
* 0.5% downspread.
|
|
|
|
*/
|
|
|
|
refclk = 135;
|
|
|
|
break;
|
2014-06-26 03:01:48 +08:00
|
|
|
case WRPLL_PLL_LCPLL:
|
2014-01-22 04:42:10 +08:00
|
|
|
refclk = LC_FREQ;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "bad wrpll refclk\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = wrpll & WRPLL_DIVIDER_REF_MASK;
|
|
|
|
p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
|
|
|
|
n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
|
|
|
|
|
2014-01-23 04:58:04 +08:00
|
|
|
/* Convert to KHz, p & r have a fixed point portion */
|
|
|
|
return (refclk * n * 100) / (p * r);
|
2014-01-22 04:42:10 +08:00
|
|
|
}
|
|
|
|
|
2014-11-13 22:55:16 +08:00
|
|
|
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t dpll)
|
|
|
|
{
|
|
|
|
uint32_t cfgcr1_reg, cfgcr2_reg;
|
|
|
|
uint32_t cfgcr1_val, cfgcr2_val;
|
|
|
|
uint32_t p0, p1, p2, dco_freq;
|
|
|
|
|
|
|
|
cfgcr1_reg = GET_CFG_CR1_REG(dpll);
|
|
|
|
cfgcr2_reg = GET_CFG_CR2_REG(dpll);
|
|
|
|
|
|
|
|
cfgcr1_val = I915_READ(cfgcr1_reg);
|
|
|
|
cfgcr2_val = I915_READ(cfgcr2_reg);
|
|
|
|
|
|
|
|
p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
|
|
|
|
p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
|
|
|
|
|
|
|
|
if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
|
|
|
|
p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
|
|
|
|
else
|
|
|
|
p1 = 1;
|
|
|
|
|
|
|
|
|
|
|
|
switch (p0) {
|
|
|
|
case DPLL_CFGCR2_PDIV_1:
|
|
|
|
p0 = 1;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_PDIV_2:
|
|
|
|
p0 = 2;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_PDIV_3:
|
|
|
|
p0 = 3;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_PDIV_7:
|
|
|
|
p0 = 7;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (p2) {
|
|
|
|
case DPLL_CFGCR2_KDIV_5:
|
|
|
|
p2 = 5;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_KDIV_2:
|
|
|
|
p2 = 2;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_KDIV_3:
|
|
|
|
p2 = 3;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_KDIV_1:
|
|
|
|
p2 = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
|
|
|
|
|
|
|
|
dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
|
|
|
|
1000) / 0x8000;
|
|
|
|
|
|
|
|
return dco_freq / (p0 * p1 * p2 * 5);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void skl_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2014-11-13 22:55:16 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
|
|
int link_clock = 0;
|
|
|
|
uint32_t dpll_ctl1, dpll;
|
|
|
|
|
2014-11-15 01:24:34 +08:00
|
|
|
dpll = pipe_config->ddi_pll_sel;
|
2014-11-13 22:55:16 +08:00
|
|
|
|
|
|
|
dpll_ctl1 = I915_READ(DPLL_CTRL1);
|
|
|
|
|
|
|
|
if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
|
|
|
|
link_clock = skl_calc_wrpll_link(dev_priv, dpll);
|
|
|
|
} else {
|
2015-04-30 23:39:17 +08:00
|
|
|
link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
|
|
|
|
link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
|
2014-11-13 22:55:16 +08:00
|
|
|
|
|
|
|
switch (link_clock) {
|
2015-04-30 23:39:17 +08:00
|
|
|
case DPLL_CTRL1_LINK_RATE_810:
|
2014-11-13 22:55:16 +08:00
|
|
|
link_clock = 81000;
|
|
|
|
break;
|
2015-04-30 23:39:17 +08:00
|
|
|
case DPLL_CTRL1_LINK_RATE_1080:
|
2015-03-05 12:32:30 +08:00
|
|
|
link_clock = 108000;
|
|
|
|
break;
|
2015-04-30 23:39:17 +08:00
|
|
|
case DPLL_CTRL1_LINK_RATE_1350:
|
2014-11-13 22:55:16 +08:00
|
|
|
link_clock = 135000;
|
|
|
|
break;
|
2015-04-30 23:39:17 +08:00
|
|
|
case DPLL_CTRL1_LINK_RATE_1620:
|
2015-03-05 12:32:30 +08:00
|
|
|
link_clock = 162000;
|
|
|
|
break;
|
2015-04-30 23:39:17 +08:00
|
|
|
case DPLL_CTRL1_LINK_RATE_2160:
|
2015-03-05 12:32:30 +08:00
|
|
|
link_clock = 216000;
|
|
|
|
break;
|
2015-04-30 23:39:17 +08:00
|
|
|
case DPLL_CTRL1_LINK_RATE_2700:
|
2014-11-13 22:55:16 +08:00
|
|
|
link_clock = 270000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "Unsupported link rate\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
link_clock *= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
pipe_config->port_clock = link_clock;
|
|
|
|
|
|
|
|
if (pipe_config->has_dp_encoder)
|
2015-01-15 20:55:22 +08:00
|
|
|
pipe_config->base.adjusted_mode.crtc_clock =
|
2014-11-13 22:55:16 +08:00
|
|
|
intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->dp_m_n);
|
|
|
|
else
|
2015-01-15 20:55:22 +08:00
|
|
|
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
2014-11-13 22:55:16 +08:00
|
|
|
}
|
|
|
|
|
2014-07-30 02:57:08 +08:00
|
|
|
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2014-01-22 04:42:10 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
|
|
int link_clock = 0;
|
|
|
|
u32 val, pll;
|
|
|
|
|
2014-06-26 03:01:55 +08:00
|
|
|
val = pipe_config->ddi_pll_sel;
|
2014-01-22 04:42:10 +08:00
|
|
|
switch (val & PORT_CLK_SEL_MASK) {
|
|
|
|
case PORT_CLK_SEL_LCPLL_810:
|
|
|
|
link_clock = 81000;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_1350:
|
|
|
|
link_clock = 135000;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_2700:
|
|
|
|
link_clock = 270000;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_WRPLL1:
|
|
|
|
link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_WRPLL2:
|
|
|
|
link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_SPLL:
|
|
|
|
pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
|
|
|
|
if (pll == SPLL_PLL_FREQ_810MHz)
|
|
|
|
link_clock = 81000;
|
|
|
|
else if (pll == SPLL_PLL_FREQ_1350MHz)
|
|
|
|
link_clock = 135000;
|
|
|
|
else if (pll == SPLL_PLL_FREQ_2700MHz)
|
|
|
|
link_clock = 270000;
|
|
|
|
else {
|
|
|
|
WARN(1, "bad spll freq\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "bad port clock sel\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
pipe_config->port_clock = link_clock * 2;
|
|
|
|
|
|
|
|
if (pipe_config->has_pch_encoder)
|
2015-01-15 20:55:22 +08:00
|
|
|
pipe_config->base.adjusted_mode.crtc_clock =
|
2014-01-22 04:42:10 +08:00
|
|
|
intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->fdi_m_n);
|
|
|
|
else if (pipe_config->has_dp_encoder)
|
2015-01-15 20:55:22 +08:00
|
|
|
pipe_config->base.adjusted_mode.crtc_clock =
|
2014-01-22 04:42:10 +08:00
|
|
|
intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->dp_m_n);
|
|
|
|
else
|
2015-01-15 20:55:22 +08:00
|
|
|
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
2014-01-22 04:42:10 +08:00
|
|
|
}
|
|
|
|
|
2014-08-22 12:19:12 +08:00
|
|
|
static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_dpll_id dpll)
|
|
|
|
{
|
|
|
|
/* FIXME formula not available in bspec */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bxt_ddi_clock_get(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
|
|
|
uint32_t dpll = port;
|
|
|
|
|
|
|
|
pipe_config->port_clock =
|
|
|
|
bxt_calc_pll_link(dev_priv, dpll);
|
|
|
|
|
|
|
|
if (pipe_config->has_dp_encoder)
|
|
|
|
pipe_config->base.adjusted_mode.crtc_clock =
|
|
|
|
intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->dp_m_n);
|
|
|
|
else
|
|
|
|
pipe_config->base.adjusted_mode.crtc_clock =
|
|
|
|
pipe_config->port_clock;
|
|
|
|
}
|
|
|
|
|
2014-07-30 02:57:08 +08:00
|
|
|
void intel_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2014-07-30 02:57:08 +08:00
|
|
|
{
|
2014-12-12 22:26:57 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen <= 8)
|
|
|
|
hsw_ddi_clock_get(encoder, pipe_config);
|
2014-08-22 12:19:12 +08:00
|
|
|
else if (IS_SKYLAKE(dev))
|
2014-12-12 22:26:57 +08:00
|
|
|
skl_ddi_clock_get(encoder, pipe_config);
|
2014-08-22 12:19:12 +08:00
|
|
|
else if (IS_BROXTON(dev))
|
|
|
|
bxt_ddi_clock_get(encoder, pipe_config);
|
2014-07-30 02:57:08 +08:00
|
|
|
}
|
|
|
|
|
2013-05-10 21:01:51 +08:00
|
|
|
static void
|
2014-07-30 01:06:23 +08:00
|
|
|
hsw_ddi_calculate_wrpll(int clock /* in Hz */,
|
|
|
|
unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
|
2013-05-10 21:01:51 +08:00
|
|
|
{
|
|
|
|
uint64_t freq2k;
|
|
|
|
unsigned p, n2, r2;
|
|
|
|
struct wrpll_rnp best = { 0, 0, 0 };
|
|
|
|
unsigned budget;
|
|
|
|
|
|
|
|
freq2k = clock / 100;
|
|
|
|
|
|
|
|
budget = wrpll_get_budget_for_freq(clock);
|
|
|
|
|
|
|
|
/* Special case handling for 540 pixel clock: bypass WR PLL entirely
|
|
|
|
* and directly pass the LC PLL to it. */
|
|
|
|
if (freq2k == 5400000) {
|
|
|
|
*n2_out = 2;
|
|
|
|
*p_out = 1;
|
|
|
|
*r2_out = 2;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
|
|
|
|
* the WR PLL.
|
|
|
|
*
|
|
|
|
* We want R so that REF_MIN <= Ref <= REF_MAX.
|
|
|
|
* Injecting R2 = 2 * R gives:
|
|
|
|
* REF_MAX * r2 > LC_FREQ * 2 and
|
|
|
|
* REF_MIN * r2 < LC_FREQ * 2
|
|
|
|
*
|
|
|
|
* Which means the desired boundaries for r2 are:
|
|
|
|
* LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
for (r2 = LC_FREQ * 2 / REF_MAX + 1;
|
|
|
|
r2 <= LC_FREQ * 2 / REF_MIN;
|
|
|
|
r2++) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* VCO = N * Ref, that is: VCO = N * LC_FREQ / R
|
|
|
|
*
|
|
|
|
* Once again we want VCO_MIN <= VCO <= VCO_MAX.
|
|
|
|
* Injecting R2 = 2 * R and N2 = 2 * N, we get:
|
|
|
|
* VCO_MAX * r2 > n2 * LC_FREQ and
|
|
|
|
* VCO_MIN * r2 < n2 * LC_FREQ)
|
|
|
|
*
|
|
|
|
* Which means the desired boundaries for n2 are:
|
|
|
|
* VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
|
|
|
|
*/
|
|
|
|
for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
|
|
|
|
n2 <= VCO_MAX * r2 / LC_FREQ;
|
|
|
|
n2++) {
|
|
|
|
|
|
|
|
for (p = P_MIN; p <= P_MAX; p += P_INC)
|
|
|
|
wrpll_update_rnp(freq2k, budget,
|
|
|
|
r2, n2, p, &best);
|
|
|
|
}
|
|
|
|
}
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2013-05-10 21:01:51 +08:00
|
|
|
*n2_out = best.n2;
|
|
|
|
*p_out = best.p;
|
|
|
|
*r2_out = best.r2;
|
2012-10-05 23:05:58 +08:00
|
|
|
}
|
|
|
|
|
2014-07-30 01:06:22 +08:00
|
|
|
static bool
|
2014-07-30 01:06:23 +08:00
|
|
|
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
|
2015-01-15 20:55:23 +08:00
|
|
|
struct intel_crtc_state *crtc_state,
|
2014-07-30 01:06:23 +08:00
|
|
|
struct intel_encoder *intel_encoder,
|
|
|
|
int clock)
|
2012-10-05 23:05:58 +08:00
|
|
|
{
|
2014-07-30 01:06:23 +08:00
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
|
2014-06-26 03:02:01 +08:00
|
|
|
struct intel_shared_dpll *pll;
|
2014-06-26 03:02:02 +08:00
|
|
|
uint32_t val;
|
2013-05-10 21:01:51 +08:00
|
|
|
unsigned p, n2, r2;
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2014-07-30 01:06:23 +08:00
|
|
|
hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
|
2013-10-31 04:27:43 +08:00
|
|
|
|
2014-06-26 03:01:48 +08:00
|
|
|
val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
|
2013-10-31 04:27:43 +08:00
|
|
|
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
|
|
|
|
WRPLL_DIVIDER_POST(p);
|
|
|
|
|
2015-05-15 18:34:29 +08:00
|
|
|
memset(&crtc_state->dpll_hw_state, 0,
|
|
|
|
sizeof(crtc_state->dpll_hw_state));
|
|
|
|
|
2015-01-15 20:55:23 +08:00
|
|
|
crtc_state->dpll_hw_state.wrpll = val;
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2015-01-15 20:55:23 +08:00
|
|
|
pll = intel_get_shared_dpll(intel_crtc, crtc_state);
|
2014-06-26 03:02:02 +08:00
|
|
|
if (pll == NULL) {
|
|
|
|
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
|
|
|
return false;
|
2013-10-31 04:27:43 +08:00
|
|
|
}
|
2014-07-04 22:27:39 +08:00
|
|
|
|
2015-01-15 20:55:23 +08:00
|
|
|
crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
|
2012-10-05 23:05:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-11-13 22:55:20 +08:00
|
|
|
struct skl_wrpll_params {
|
|
|
|
uint32_t dco_fraction;
|
|
|
|
uint32_t dco_integer;
|
|
|
|
uint32_t qdiv_ratio;
|
|
|
|
uint32_t qdiv_mode;
|
|
|
|
uint32_t kdiv;
|
|
|
|
uint32_t pdiv;
|
|
|
|
uint32_t central_freq;
|
|
|
|
};
|
|
|
|
|
2015-05-08 01:38:40 +08:00
|
|
|
static bool
|
2014-11-13 22:55:20 +08:00
|
|
|
skl_ddi_calculate_wrpll(int clock /* in Hz */,
|
|
|
|
struct skl_wrpll_params *wrpll_params)
|
|
|
|
{
|
|
|
|
uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
|
2014-11-14 22:20:27 +08:00
|
|
|
uint64_t dco_central_freq[3] = {8400000000ULL,
|
|
|
|
9000000000ULL,
|
|
|
|
9600000000ULL};
|
2014-11-13 22:55:20 +08:00
|
|
|
uint32_t min_dco_deviation = 400;
|
|
|
|
uint32_t min_dco_index = 3;
|
|
|
|
uint32_t P0[4] = {1, 2, 3, 7};
|
|
|
|
uint32_t P2[4] = {1, 2, 3, 5};
|
|
|
|
bool found = false;
|
|
|
|
uint32_t candidate_p = 0;
|
|
|
|
uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
|
|
|
|
uint32_t candidate_p2[3] = {0};
|
|
|
|
uint32_t dco_central_freq_deviation[3];
|
|
|
|
uint32_t i, P1, k, dco_count;
|
|
|
|
bool retry_with_odd = false;
|
|
|
|
uint64_t dco_freq;
|
|
|
|
|
|
|
|
/* Determine P0, P1 or P2 */
|
|
|
|
for (dco_count = 0; dco_count < 3; dco_count++) {
|
|
|
|
found = false;
|
|
|
|
candidate_p =
|
|
|
|
div64_u64(dco_central_freq[dco_count], afe_clock);
|
|
|
|
if (retry_with_odd == false)
|
|
|
|
candidate_p = (candidate_p % 2 == 0 ?
|
|
|
|
candidate_p : candidate_p + 1);
|
|
|
|
|
|
|
|
for (P1 = 1; P1 < candidate_p; P1++) {
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (!(P0[i] != 1 || P1 == 1))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (k = 0; k < 4; k++) {
|
|
|
|
if (P1 != 1 && P2[k] != 2)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (candidate_p == P0[i] * P1 * P2[k]) {
|
|
|
|
/* Found possible P0, P1, P2 */
|
|
|
|
found = true;
|
|
|
|
candidate_p0[dco_count] = P0[i];
|
|
|
|
candidate_p1[dco_count] = P1;
|
|
|
|
candidate_p2[dco_count] = P2[k];
|
|
|
|
goto found;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
found:
|
|
|
|
if (found) {
|
|
|
|
dco_central_freq_deviation[dco_count] =
|
|
|
|
div64_u64(10000 *
|
|
|
|
abs_diff((candidate_p * afe_clock),
|
|
|
|
dco_central_freq[dco_count]),
|
|
|
|
dco_central_freq[dco_count]);
|
|
|
|
|
|
|
|
if (dco_central_freq_deviation[dco_count] <
|
|
|
|
min_dco_deviation) {
|
|
|
|
min_dco_deviation =
|
|
|
|
dco_central_freq_deviation[dco_count];
|
|
|
|
min_dco_index = dco_count;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (min_dco_index > 2 && dco_count == 2) {
|
2015-05-08 01:38:38 +08:00
|
|
|
/* oh well, we tried... */
|
|
|
|
if (retry_with_odd)
|
|
|
|
break;
|
|
|
|
|
2014-11-13 22:55:20 +08:00
|
|
|
retry_with_odd = true;
|
|
|
|
dco_count = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
if (WARN(min_dco_index > 2,
|
|
|
|
"No valid parameters found for pixel clock: %dHz\n", clock))
|
2015-05-08 01:38:40 +08:00
|
|
|
return false;
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
wrpll_params->central_freq = dco_central_freq[min_dco_index];
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
switch (dco_central_freq[min_dco_index]) {
|
|
|
|
case 9600000000ULL:
|
|
|
|
wrpll_params->central_freq = 0;
|
|
|
|
break;
|
|
|
|
case 9000000000ULL:
|
|
|
|
wrpll_params->central_freq = 1;
|
|
|
|
break;
|
|
|
|
case 8400000000ULL:
|
|
|
|
wrpll_params->central_freq = 3;
|
|
|
|
}
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
switch (candidate_p0[min_dco_index]) {
|
|
|
|
case 1:
|
|
|
|
wrpll_params->pdiv = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
wrpll_params->pdiv = 1;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
wrpll_params->pdiv = 2;
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
wrpll_params->pdiv = 4;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "Incorrect PDiv\n");
|
|
|
|
}
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
switch (candidate_p2[min_dco_index]) {
|
|
|
|
case 5:
|
|
|
|
wrpll_params->kdiv = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
wrpll_params->kdiv = 1;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
wrpll_params->kdiv = 2;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
wrpll_params->kdiv = 3;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "Incorrect KDiv\n");
|
|
|
|
}
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
|
|
|
|
wrpll_params->qdiv_mode =
|
|
|
|
(wrpll_params->qdiv_ratio == 1) ? 0 : 1;
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
dco_freq = candidate_p0[min_dco_index] *
|
|
|
|
candidate_p1[min_dco_index] *
|
|
|
|
candidate_p2[min_dco_index] * afe_clock;
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-05-08 01:38:41 +08:00
|
|
|
/*
|
|
|
|
* Intermediate values are in Hz.
|
|
|
|
* Divide by MHz to match bsepc
|
|
|
|
*/
|
|
|
|
wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
|
|
|
|
wrpll_params->dco_fraction =
|
|
|
|
div_u64(((div_u64(dco_freq, 24) -
|
|
|
|
wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
|
2015-05-08 01:38:40 +08:00
|
|
|
|
|
|
|
return true;
|
2014-11-13 22:55:20 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static bool
|
|
|
|
skl_ddi_pll_select(struct intel_crtc *intel_crtc,
|
2015-01-15 20:55:23 +08:00
|
|
|
struct intel_crtc_state *crtc_state,
|
2014-11-13 22:55:20 +08:00
|
|
|
struct intel_encoder *intel_encoder,
|
|
|
|
int clock)
|
|
|
|
{
|
|
|
|
struct intel_shared_dpll *pll;
|
|
|
|
uint32_t ctrl1, cfgcr1, cfgcr2;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* See comment in intel_dpll_hw_state to understand why we always use 0
|
|
|
|
* as the DPLL id in this function.
|
|
|
|
*/
|
|
|
|
|
|
|
|
ctrl1 = DPLL_CTRL1_OVERRIDE(0);
|
|
|
|
|
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
|
|
|
|
struct skl_wrpll_params wrpll_params = { 0, };
|
|
|
|
|
|
|
|
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
|
|
|
|
|
2015-05-08 01:38:40 +08:00
|
|
|
if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
|
|
|
|
return false;
|
2014-11-13 22:55:20 +08:00
|
|
|
|
|
|
|
cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
|
|
|
|
DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
|
|
|
|
wrpll_params.dco_integer;
|
|
|
|
|
|
|
|
cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
|
|
|
|
DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
|
|
|
|
DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
|
|
|
|
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
|
|
|
|
wrpll_params.central_freq;
|
|
|
|
} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
|
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
|
|
|
switch (intel_dp->link_bw) {
|
|
|
|
case DP_LINK_BW_1_62:
|
2015-04-30 23:39:17 +08:00
|
|
|
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
|
2014-11-13 22:55:20 +08:00
|
|
|
break;
|
|
|
|
case DP_LINK_BW_2_7:
|
2015-04-30 23:39:17 +08:00
|
|
|
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
|
2014-11-13 22:55:20 +08:00
|
|
|
break;
|
|
|
|
case DP_LINK_BW_5_4:
|
2015-04-30 23:39:17 +08:00
|
|
|
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
|
2014-11-13 22:55:20 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
cfgcr1 = cfgcr2 = 0;
|
|
|
|
} else /* eDP */
|
|
|
|
return true;
|
|
|
|
|
2015-05-15 18:34:29 +08:00
|
|
|
memset(&crtc_state->dpll_hw_state, 0,
|
|
|
|
sizeof(crtc_state->dpll_hw_state));
|
|
|
|
|
2015-01-15 20:55:23 +08:00
|
|
|
crtc_state->dpll_hw_state.ctrl1 = ctrl1;
|
|
|
|
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
|
|
|
|
crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
|
2014-11-13 22:55:20 +08:00
|
|
|
|
2015-01-15 20:55:23 +08:00
|
|
|
pll = intel_get_shared_dpll(intel_crtc, crtc_state);
|
2014-11-13 22:55:20 +08:00
|
|
|
if (pll == NULL) {
|
|
|
|
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* shared DPLL id 0 is DPLL 1 */
|
2015-01-15 20:55:23 +08:00
|
|
|
crtc_state->ddi_pll_sel = pll->id + 1;
|
2014-11-13 22:55:20 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2014-07-30 01:06:22 +08:00
|
|
|
|
2014-08-22 12:19:08 +08:00
|
|
|
/* bxt clock parameters */
|
|
|
|
struct bxt_clk_div {
|
|
|
|
uint32_t p1;
|
|
|
|
uint32_t p2;
|
|
|
|
uint32_t m2_int;
|
|
|
|
uint32_t m2_frac;
|
|
|
|
bool m2_frac_en;
|
|
|
|
uint32_t n;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* pre-calculated values for DP linkrates */
|
|
|
|
static struct bxt_clk_div bxt_dp_clk_val[7] = {
|
2015-05-13 14:50:35 +08:00
|
|
|
/* 162 */ {4, 2, 32, 1677722, 1, 1},
|
|
|
|
/* 270 */ {4, 1, 27, 0, 0, 1},
|
|
|
|
/* 540 */ {2, 1, 27, 0, 0, 1},
|
|
|
|
/* 216 */ {3, 2, 32, 1677722, 1, 1},
|
|
|
|
/* 243 */ {4, 1, 24, 1258291, 1, 1},
|
|
|
|
/* 324 */ {4, 1, 32, 1677722, 1, 1},
|
|
|
|
/* 432 */ {3, 1, 32, 1677722, 1, 1}
|
2014-08-22 12:19:08 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static bool
|
|
|
|
bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct intel_encoder *intel_encoder,
|
|
|
|
int clock)
|
|
|
|
{
|
|
|
|
struct intel_shared_dpll *pll;
|
|
|
|
struct bxt_clk_div clk_div = {0};
|
2015-05-13 14:48:52 +08:00
|
|
|
int vco = 0;
|
|
|
|
uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
|
2015-05-13 14:50:35 +08:00
|
|
|
uint32_t dcoampovr_en_h, dco_amp, lanestagger;
|
2014-08-22 12:19:08 +08:00
|
|
|
|
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
|
|
|
|
intel_clock_t best_clock;
|
|
|
|
|
|
|
|
/* Calculate HDMI div */
|
|
|
|
/*
|
|
|
|
* FIXME: tie the following calculation into
|
|
|
|
* i9xx_crtc_compute_clock
|
|
|
|
*/
|
|
|
|
if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
|
|
|
|
DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
|
|
|
|
clock, pipe_name(intel_crtc->pipe));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
clk_div.p1 = best_clock.p1;
|
|
|
|
clk_div.p2 = best_clock.p2;
|
|
|
|
WARN_ON(best_clock.m1 != 2);
|
|
|
|
clk_div.n = best_clock.n;
|
|
|
|
clk_div.m2_int = best_clock.m2 >> 22;
|
|
|
|
clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
|
|
|
|
clk_div.m2_frac_en = clk_div.m2_frac != 0;
|
|
|
|
|
2015-05-13 14:48:52 +08:00
|
|
|
vco = best_clock.vco;
|
2014-08-22 12:19:08 +08:00
|
|
|
} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
|
|
|
|
intel_encoder->type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
|
|
|
switch (intel_dp->link_bw) {
|
|
|
|
case DP_LINK_BW_1_62:
|
|
|
|
clk_div = bxt_dp_clk_val[0];
|
|
|
|
break;
|
|
|
|
case DP_LINK_BW_2_7:
|
|
|
|
clk_div = bxt_dp_clk_val[1];
|
|
|
|
break;
|
|
|
|
case DP_LINK_BW_5_4:
|
|
|
|
clk_div = bxt_dp_clk_val[2];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
clk_div = bxt_dp_clk_val[0];
|
|
|
|
DRM_ERROR("Unknown link rate\n");
|
|
|
|
}
|
2015-05-13 14:48:52 +08:00
|
|
|
vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
|
|
|
|
}
|
|
|
|
|
|
|
|
dco_amp = 15;
|
|
|
|
dcoampovr_en_h = 0;
|
|
|
|
if (vco >= 6200000 && vco <= 6480000) {
|
|
|
|
prop_coef = 4;
|
|
|
|
int_coef = 9;
|
|
|
|
gain_ctl = 3;
|
|
|
|
targ_cnt = 8;
|
|
|
|
} else if ((vco > 5400000 && vco < 6200000) ||
|
|
|
|
(vco >= 4800000 && vco < 5400000)) {
|
|
|
|
prop_coef = 5;
|
|
|
|
int_coef = 11;
|
|
|
|
gain_ctl = 3;
|
|
|
|
targ_cnt = 9;
|
|
|
|
if (vco >= 4800000 && vco < 5400000)
|
|
|
|
dcoampovr_en_h = 1;
|
|
|
|
} else if (vco == 5400000) {
|
|
|
|
prop_coef = 3;
|
|
|
|
int_coef = 8;
|
|
|
|
gain_ctl = 1;
|
|
|
|
targ_cnt = 9;
|
|
|
|
} else {
|
|
|
|
DRM_ERROR("Invalid VCO\n");
|
|
|
|
return false;
|
2014-08-22 12:19:08 +08:00
|
|
|
}
|
|
|
|
|
2015-05-15 18:34:29 +08:00
|
|
|
memset(&crtc_state->dpll_hw_state, 0,
|
|
|
|
sizeof(crtc_state->dpll_hw_state));
|
|
|
|
|
2015-05-13 14:50:35 +08:00
|
|
|
if (clock > 270000)
|
|
|
|
lanestagger = 0x18;
|
|
|
|
else if (clock > 135000)
|
|
|
|
lanestagger = 0x0d;
|
|
|
|
else if (clock > 67000)
|
|
|
|
lanestagger = 0x07;
|
|
|
|
else if (clock > 33000)
|
|
|
|
lanestagger = 0x04;
|
|
|
|
else
|
|
|
|
lanestagger = 0x02;
|
|
|
|
|
2014-08-22 12:19:08 +08:00
|
|
|
crtc_state->dpll_hw_state.ebb0 =
|
|
|
|
PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
|
|
|
|
crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
|
|
|
|
crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
|
|
|
|
crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
|
|
|
|
|
|
|
|
if (clk_div.m2_frac_en)
|
|
|
|
crtc_state->dpll_hw_state.pll3 =
|
|
|
|
PORT_PLL_M2_FRAC_ENABLE;
|
|
|
|
|
|
|
|
crtc_state->dpll_hw_state.pll6 =
|
2015-05-13 14:48:52 +08:00
|
|
|
prop_coef | PORT_PLL_INT_COEFF(int_coef);
|
2014-08-22 12:19:08 +08:00
|
|
|
crtc_state->dpll_hw_state.pll6 |=
|
2015-05-13 14:48:52 +08:00
|
|
|
PORT_PLL_GAIN_CTL(gain_ctl);
|
|
|
|
|
|
|
|
crtc_state->dpll_hw_state.pll8 = targ_cnt;
|
2014-08-22 12:19:08 +08:00
|
|
|
|
2015-05-13 14:48:52 +08:00
|
|
|
if (dcoampovr_en_h)
|
|
|
|
crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
|
|
|
|
|
|
|
|
crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
|
2014-08-22 12:19:08 +08:00
|
|
|
|
|
|
|
crtc_state->dpll_hw_state.pcsdw12 =
|
2015-05-13 14:50:35 +08:00
|
|
|
LANESTAGGER_STRAP_OVRD | lanestagger;
|
2014-08-22 12:19:08 +08:00
|
|
|
|
|
|
|
pll = intel_get_shared_dpll(intel_crtc, crtc_state);
|
|
|
|
if (pll == NULL) {
|
|
|
|
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* shared DPLL id 0 is DPLL A */
|
|
|
|
crtc_state->ddi_pll_sel = pll->id;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-07-30 01:06:22 +08:00
|
|
|
/*
|
|
|
|
* Tries to find a *shared* PLL for the CRTC and store it in
|
|
|
|
* intel_crtc->ddi_pll_sel.
|
|
|
|
*
|
|
|
|
* For private DPLLs, compute_config() should do the selection for us. This
|
|
|
|
* function should be folded into compute_config() eventually.
|
|
|
|
*/
|
2015-01-15 20:55:23 +08:00
|
|
|
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
2014-07-30 01:06:22 +08:00
|
|
|
{
|
2014-11-13 22:55:20 +08:00
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
2014-10-29 17:32:30 +08:00
|
|
|
struct intel_encoder *intel_encoder =
|
2015-03-20 22:18:12 +08:00
|
|
|
intel_ddi_get_crtc_new_encoder(crtc_state);
|
2015-01-15 20:55:23 +08:00
|
|
|
int clock = crtc_state->port_clock;
|
2014-07-30 01:06:22 +08:00
|
|
|
|
2014-11-13 22:55:20 +08:00
|
|
|
if (IS_SKYLAKE(dev))
|
2015-01-15 20:55:23 +08:00
|
|
|
return skl_ddi_pll_select(intel_crtc, crtc_state,
|
|
|
|
intel_encoder, clock);
|
2014-08-22 12:19:08 +08:00
|
|
|
else if (IS_BROXTON(dev))
|
|
|
|
return bxt_ddi_pll_select(intel_crtc, crtc_state,
|
|
|
|
intel_encoder, clock);
|
2014-11-13 22:55:20 +08:00
|
|
|
else
|
2015-01-15 20:55:23 +08:00
|
|
|
return hsw_ddi_pll_select(intel_crtc, crtc_state,
|
|
|
|
intel_encoder, clock);
|
2014-07-30 01:06:22 +08:00
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:30 +08:00
|
|
|
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
2015-01-15 20:55:25 +08:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-16 02:51:30 +08:00
|
|
|
int type = intel_encoder->type;
|
|
|
|
uint32_t temp;
|
|
|
|
|
2014-05-02 12:02:48 +08:00
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
|
2012-10-24 04:30:00 +08:00
|
|
|
temp = TRANS_MSA_SYNC_CLK;
|
2015-01-15 20:55:25 +08:00
|
|
|
switch (intel_crtc->config->pipe_bpp) {
|
2012-10-16 02:51:30 +08:00
|
|
|
case 18:
|
2012-10-24 04:30:00 +08:00
|
|
|
temp |= TRANS_MSA_6_BPC;
|
2012-10-16 02:51:30 +08:00
|
|
|
break;
|
|
|
|
case 24:
|
2012-10-24 04:30:00 +08:00
|
|
|
temp |= TRANS_MSA_8_BPC;
|
2012-10-16 02:51:30 +08:00
|
|
|
break;
|
|
|
|
case 30:
|
2012-10-24 04:30:00 +08:00
|
|
|
temp |= TRANS_MSA_10_BPC;
|
2012-10-16 02:51:30 +08:00
|
|
|
break;
|
|
|
|
case 36:
|
2012-10-24 04:30:00 +08:00
|
|
|
temp |= TRANS_MSA_12_BPC;
|
2012-10-16 02:51:30 +08:00
|
|
|
break;
|
|
|
|
default:
|
drm/i915: precompute pipe bpp before touching the hw
The procedure has now 3 steps:
1. Compute the bpp that the plane will output, this is done in
pipe_config_set_bpp and stored into pipe_config->pipe_bpp. Also,
this function clamps the pipe_bpp to whatever limit the EDID of any
connected output specifies.
2. Adjust the pipe_bpp in the encoder and crtc functions, according to
whatever constraints there are.
3. Decide whether to use dither by comparing the stored plane bpp with
computed pipe_bpp.
There are a few slight functional changes in this patch:
- LVDS connector are now also going through the EDID clamping. But in
a 2nd change we now unconditionally force the lvds bpc value - this
shouldn't matter in reality when the panel setup is consistent, but
better safe than sorry.
- HDMI now forces the pipe_bpp to the selected value - I think that's
what we actually want, since otherwise at least the pixelclock
computations are wrong (I'm not sure whether the port would accept
e.g. 10 bpc when in 12bpc mode). Contrary to the old code, we pick
the next higher bpc value, since otherwise there's no way to make
use of the 12 bpc mode (since the next patch will remove the 12bpc
plane format, it doesn't exist).
Both of these changes are due to the removal of the
pipe_bpp = min(display_bpp, plane_bpp);
statement.
Another slight change is the reworking of the dp bpc code:
- For the mode_valid callback it's sufficient to only check whether
the mode would fit at the lowest bpc.
- The bandwidth computation code is a bit restructured: It now walks
all available bpp values in an outer loop and the codeblock that
computes derived values (once a good configuration is found) has been
moved out of the for loop maze. This is prep work to allow us to
successively fall back on bpc values, and also correctly support bpc
values != 8 or 6.
v2: Rebased on top of Paulo Zanoni's little refactoring to use more
drm dp helper functions.
v3: Rebased on top of Jani's eDP bpp fix and Ville's limited color
range work.
v4: Remove the INTEL_MODE_DP_FORCE_6BPC #define, no longer needed.
v5: Remove intel_crtc->bpp, too, and fix up the 12bpc check in the
hdmi code. Also fixup the bpp check in intel_dp.c, it'll get reworked
in a later patch though again.
v6: Fix spelling in a comment.
v7: Debug output improvements for the bpp computation.
v8: Fixup 6bpc lvds check - dual-link and 8bpc mode are different
things!
v9: Reinstate the fix to properly ignore the firmware edp bpp ... this
was lost in a rebase.
v10: Both g4x and vlv lack 12bpc pipes, so don't enforce that we have
that. Still unsure whether this is the way to go, but at least 6bpc
for a 8bpc hdmi output seems to work.
v11: And g4x/vlv also lack 12bpc hdmi support, so only support high
depth on DP. Adjust the code.
v12: Rebased.
v13: Split out the introduction of pipe_config->dither|pipe_bpp, as
requested from Jesse Barnes.
v14: Split out the special 6BPC handling for DP, as requested by Jesse
Barnes.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-27 07:44:58 +08:00
|
|
|
BUG();
|
2012-10-16 02:51:30 +08:00
|
|
|
}
|
2012-10-24 04:30:00 +08:00
|
|
|
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
|
2012-10-16 02:51:30 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-02 12:02:48 +08:00
|
|
|
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
|
|
|
|
{
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2015-01-15 20:55:25 +08:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2014-05-02 12:02:48 +08:00
|
|
|
uint32_t temp;
|
|
|
|
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
if (state == true)
|
|
|
|
temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
|
|
|
|
else
|
|
|
|
temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
|
|
|
|
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
|
|
|
|
}
|
|
|
|
|
2013-03-07 23:30:27 +08:00
|
|
|
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
|
2012-10-05 23:05:53 +08:00
|
|
|
{
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
2012-10-16 02:51:29 +08:00
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2013-11-03 12:07:37 +08:00
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-05 23:05:53 +08:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2015-01-15 20:55:25 +08:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-27 05:05:50 +08:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2012-10-16 02:51:29 +08:00
|
|
|
int type = intel_encoder->type;
|
2012-10-05 23:05:53 +08:00
|
|
|
uint32_t temp;
|
|
|
|
|
2012-10-25 02:06:19 +08:00
|
|
|
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
|
|
|
|
temp = TRANS_DDI_FUNC_ENABLE;
|
2012-10-27 05:05:50 +08:00
|
|
|
temp |= TRANS_DDI_SELECT_PORT(port);
|
2012-08-09 01:15:29 +08:00
|
|
|
|
2015-01-15 20:55:25 +08:00
|
|
|
switch (intel_crtc->config->pipe_bpp) {
|
2012-08-09 01:15:29 +08:00
|
|
|
case 18:
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_BPC_6;
|
2012-08-09 01:15:29 +08:00
|
|
|
break;
|
|
|
|
case 24:
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_BPC_8;
|
2012-08-09 01:15:29 +08:00
|
|
|
break;
|
|
|
|
case 30:
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_BPC_10;
|
2012-08-09 01:15:29 +08:00
|
|
|
break;
|
|
|
|
case 36:
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_BPC_12;
|
2012-08-09 01:15:29 +08:00
|
|
|
break;
|
|
|
|
default:
|
drm/i915: precompute pipe bpp before touching the hw
The procedure has now 3 steps:
1. Compute the bpp that the plane will output, this is done in
pipe_config_set_bpp and stored into pipe_config->pipe_bpp. Also,
this function clamps the pipe_bpp to whatever limit the EDID of any
connected output specifies.
2. Adjust the pipe_bpp in the encoder and crtc functions, according to
whatever constraints there are.
3. Decide whether to use dither by comparing the stored plane bpp with
computed pipe_bpp.
There are a few slight functional changes in this patch:
- LVDS connector are now also going through the EDID clamping. But in
a 2nd change we now unconditionally force the lvds bpc value - this
shouldn't matter in reality when the panel setup is consistent, but
better safe than sorry.
- HDMI now forces the pipe_bpp to the selected value - I think that's
what we actually want, since otherwise at least the pixelclock
computations are wrong (I'm not sure whether the port would accept
e.g. 10 bpc when in 12bpc mode). Contrary to the old code, we pick
the next higher bpc value, since otherwise there's no way to make
use of the 12 bpc mode (since the next patch will remove the 12bpc
plane format, it doesn't exist).
Both of these changes are due to the removal of the
pipe_bpp = min(display_bpp, plane_bpp);
statement.
Another slight change is the reworking of the dp bpc code:
- For the mode_valid callback it's sufficient to only check whether
the mode would fit at the lowest bpc.
- The bandwidth computation code is a bit restructured: It now walks
all available bpp values in an outer loop and the codeblock that
computes derived values (once a good configuration is found) has been
moved out of the for loop maze. This is prep work to allow us to
successively fall back on bpc values, and also correctly support bpc
values != 8 or 6.
v2: Rebased on top of Paulo Zanoni's little refactoring to use more
drm dp helper functions.
v3: Rebased on top of Jani's eDP bpp fix and Ville's limited color
range work.
v4: Remove the INTEL_MODE_DP_FORCE_6BPC #define, no longer needed.
v5: Remove intel_crtc->bpp, too, and fix up the 12bpc check in the
hdmi code. Also fixup the bpp check in intel_dp.c, it'll get reworked
in a later patch though again.
v6: Fix spelling in a comment.
v7: Debug output improvements for the bpp computation.
v8: Fixup 6bpc lvds check - dual-link and 8bpc mode are different
things!
v9: Reinstate the fix to properly ignore the firmware edp bpp ... this
was lost in a rebase.
v10: Both g4x and vlv lack 12bpc pipes, so don't enforce that we have
that. Still unsure whether this is the way to go, but at least 6bpc
for a 8bpc hdmi output seems to work.
v11: And g4x/vlv also lack 12bpc hdmi support, so only support high
depth on DP. Adjust the code.
v12: Rebased.
v13: Split out the introduction of pipe_config->dither|pipe_bpp, as
requested from Jesse Barnes.
v14: Split out the special 6BPC handling for DP, as requested by Jesse
Barnes.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-27 07:44:58 +08:00
|
|
|
BUG();
|
2012-08-09 01:15:29 +08:00
|
|
|
}
|
2012-05-10 02:37:31 +08:00
|
|
|
|
2015-01-15 20:55:25 +08:00
|
|
|
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_PVSYNC;
|
2015-01-15 20:55:25 +08:00
|
|
|
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_PHSYNC;
|
2012-08-09 01:15:28 +08:00
|
|
|
|
2012-10-24 04:30:04 +08:00
|
|
|
if (cpu_transcoder == TRANSCODER_EDP) {
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
2013-11-03 12:07:37 +08:00
|
|
|
/* On Haswell, can only use the always-on power well for
|
|
|
|
* eDP when not using the panel fitter, and when not
|
|
|
|
* using motion blur mitigation (which we don't
|
|
|
|
* support). */
|
2014-05-29 20:10:22 +08:00
|
|
|
if (IS_HASWELL(dev) &&
|
2015-01-15 20:55:25 +08:00
|
|
|
(intel_crtc->config->pch_pfit.enabled ||
|
|
|
|
intel_crtc->config->pch_pfit.force_thru))
|
2013-01-30 02:35:20 +08:00
|
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
|
|
|
|
else
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ON;
|
2012-10-24 04:30:04 +08:00
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
|
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:29 +08:00
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
2015-01-15 20:55:25 +08:00
|
|
|
if (intel_crtc->config->has_hdmi_sink)
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_HDMI;
|
2012-10-05 23:05:53 +08:00
|
|
|
else
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DVI;
|
2012-10-05 23:05:53 +08:00
|
|
|
|
2012-10-16 02:51:29 +08:00
|
|
|
} else if (type == INTEL_OUTPUT_ANALOG) {
|
2012-10-25 02:06:19 +08:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_FDI;
|
2015-01-15 20:55:25 +08:00
|
|
|
temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
|
2012-10-16 02:51:29 +08:00
|
|
|
|
|
|
|
} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
|
|
|
|
type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
2014-05-02 12:02:48 +08:00
|
|
|
if (intel_dp->is_mst) {
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
|
|
|
|
} else
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
|
|
|
|
|
|
|
|
temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
|
|
|
|
} else if (type == INTEL_OUTPUT_DP_MST) {
|
|
|
|
struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
|
|
|
|
|
|
|
|
if (intel_dp->is_mst) {
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
|
|
|
|
} else
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
|
2012-10-16 02:51:29 +08:00
|
|
|
|
2013-04-30 20:01:40 +08:00
|
|
|
temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
|
2012-10-05 23:05:53 +08:00
|
|
|
} else {
|
2013-04-17 22:48:49 +08:00
|
|
|
WARN(1, "Invalid encoder type %d for pipe %c\n",
|
|
|
|
intel_encoder->type, pipe_name(pipe));
|
2012-10-05 23:05:53 +08:00
|
|
|
}
|
|
|
|
|
2012-10-25 02:06:19 +08:00
|
|
|
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
|
2012-10-05 23:05:53 +08:00
|
|
|
}
|
2012-05-10 02:37:31 +08:00
|
|
|
|
2012-10-25 02:06:19 +08:00
|
|
|
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder)
|
2012-10-05 23:05:53 +08:00
|
|
|
{
|
2012-10-25 02:06:19 +08:00
|
|
|
uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
|
2012-10-05 23:05:53 +08:00
|
|
|
uint32_t val = I915_READ(reg);
|
|
|
|
|
2014-05-02 12:02:48 +08:00
|
|
|
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
|
2012-10-25 02:06:19 +08:00
|
|
|
val |= TRANS_DDI_PORT_NONE;
|
2012-10-05 23:05:53 +08:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-10 02:37:31 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:51 +08:00
|
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_connector->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_encoder *intel_encoder = intel_connector->encoder;
|
|
|
|
int type = intel_connector->base.connector_type;
|
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
|
|
enum pipe pipe = 0;
|
|
|
|
enum transcoder cpu_transcoder;
|
2014-04-02 01:55:12 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
2012-10-27 05:05:51 +08:00
|
|
|
uint32_t tmp;
|
|
|
|
|
2014-04-02 01:55:12 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
2014-09-30 16:56:39 +08:00
|
|
|
if (!intel_display_power_is_enabled(dev_priv, power_domain))
|
2014-04-02 01:55:12 +08:00
|
|
|
return false;
|
|
|
|
|
2012-10-27 05:05:51 +08:00
|
|
|
if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (port == PORT_A)
|
|
|
|
cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
else
|
2012-11-30 05:18:51 +08:00
|
|
|
cpu_transcoder = (enum transcoder) pipe;
|
2012-10-27 05:05:51 +08:00
|
|
|
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
|
|
|
|
switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
|
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
|
|
|
return (type == DRM_MODE_CONNECTOR_HDMIA);
|
|
|
|
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
|
|
|
if (type == DRM_MODE_CONNECTOR_eDP)
|
|
|
|
return true;
|
|
|
|
return (type == DRM_MODE_CONNECTOR_DisplayPort);
|
2014-05-02 12:02:48 +08:00
|
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
|
|
|
/* if the transcoder is in MST state then
|
|
|
|
* connector isn't connected */
|
|
|
|
return false;
|
2012-10-27 05:05:51 +08:00
|
|
|
|
|
|
|
case TRANS_DDI_MODE_SELECT_FDI:
|
|
|
|
return (type == DRM_MODE_CONNECTOR_VGA);
|
|
|
|
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-02 19:27:29 +08:00
|
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-16 02:51:39 +08:00
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
2014-03-05 22:20:54 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
2012-07-02 19:27:29 +08:00
|
|
|
u32 tmp;
|
|
|
|
int i;
|
|
|
|
|
2014-03-05 22:20:54 +08:00
|
|
|
power_domain = intel_display_port_power_domain(encoder);
|
2014-09-30 16:56:39 +08:00
|
|
|
if (!intel_display_power_is_enabled(dev_priv, power_domain))
|
2014-03-05 22:20:54 +08:00
|
|
|
return false;
|
|
|
|
|
2012-10-16 02:51:39 +08:00
|
|
|
tmp = I915_READ(DDI_BUF_CTL(port));
|
2012-07-02 19:27:29 +08:00
|
|
|
|
|
|
|
if (!(tmp & DDI_BUF_CTL_ENABLE))
|
|
|
|
return false;
|
|
|
|
|
2012-10-25 02:06:19 +08:00
|
|
|
if (port == PORT_A) {
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
|
2012-07-02 19:27:29 +08:00
|
|
|
|
2012-10-25 02:06:19 +08:00
|
|
|
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
|
|
|
|
case TRANS_DDI_EDP_INPUT_A_ON:
|
|
|
|
case TRANS_DDI_EDP_INPUT_A_ONOFF:
|
|
|
|
*pipe = PIPE_A;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_EDP_INPUT_B_ONOFF:
|
|
|
|
*pipe = PIPE_B;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_EDP_INPUT_C_ONOFF:
|
|
|
|
*pipe = PIPE_C;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
|
|
|
|
|
|
|
|
if ((tmp & TRANS_DDI_PORT_MASK)
|
|
|
|
== TRANS_DDI_SELECT_PORT(port)) {
|
2014-05-02 12:02:48 +08:00
|
|
|
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
|
|
|
|
return false;
|
|
|
|
|
2012-10-25 02:06:19 +08:00
|
|
|
*pipe = i;
|
|
|
|
return true;
|
|
|
|
}
|
2012-07-02 19:27:29 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-17 22:48:49 +08:00
|
|
|
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
|
2012-07-02 19:27:29 +08:00
|
|
|
|
2013-04-03 01:03:55 +08:00
|
|
|
return false;
|
2012-07-02 19:27:29 +08:00
|
|
|
}
|
|
|
|
|
2012-10-05 23:05:54 +08:00
|
|
|
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
|
|
|
|
{
|
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2015-01-15 20:55:25 +08:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-05 23:05:54 +08:00
|
|
|
|
2012-10-24 04:29:56 +08:00
|
|
|
if (cpu_transcoder != TRANSCODER_EDP)
|
|
|
|
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
|
|
|
|
TRANS_CLK_SEL_PORT(port));
|
2012-10-05 23:05:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
|
2015-01-15 20:55:25 +08:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-05 23:05:54 +08:00
|
|
|
|
2012-10-24 04:29:56 +08:00
|
|
|
if (cpu_transcoder != TRANSCODER_EDP)
|
|
|
|
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
|
|
|
|
TRANS_CLK_SEL_DISABLED);
|
2012-10-05 23:05:54 +08:00
|
|
|
}
|
|
|
|
|
2014-11-18 18:15:27 +08:00
|
|
|
void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
|
|
|
|
enum port port, int type)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
const struct bxt_ddi_buf_trans *ddi_translations;
|
|
|
|
u32 n_entries, i;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
|
|
|
|
n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
|
|
|
|
ddi_translations = bxt_ddi_translations_dp;
|
|
|
|
} else if (type == INTEL_OUTPUT_HDMI) {
|
|
|
|
n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
|
|
|
|
ddi_translations = bxt_ddi_translations_hdmi;
|
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
|
|
|
|
type);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if default value has to be used */
|
|
|
|
if (level >= n_entries ||
|
|
|
|
(type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
|
|
|
|
for (i = 0; i < n_entries; i++) {
|
|
|
|
if (ddi_translations[i].default_index) {
|
|
|
|
level = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* While we write to the group register to program all lanes at once we
|
|
|
|
* can read only lane registers and we pick lanes 0/1 for that.
|
|
|
|
*/
|
|
|
|
val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
|
|
|
|
val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
|
|
|
|
I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
|
|
|
|
val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
|
|
|
|
val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
|
|
|
|
ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
|
|
|
|
val &= ~UNIQE_TRANGE_EN_METHOD;
|
|
|
|
if (ddi_translations[level].enable)
|
|
|
|
val |= UNIQE_TRANGE_EN_METHOD;
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
|
|
|
|
val &= ~DE_EMPHASIS;
|
|
|
|
val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
|
|
|
|
val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
|
|
|
|
I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
|
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
|
2012-10-05 23:05:58 +08:00
|
|
|
{
|
2012-10-16 02:51:41 +08:00
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2014-11-13 22:55:19 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-04-25 05:54:58 +08:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
|
2012-10-05 23:05:58 +08:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2012-10-24 04:30:07 +08:00
|
|
|
int type = intel_encoder->type;
|
2014-11-18 18:15:27 +08:00
|
|
|
int hdmi_level;
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2012-10-24 04:30:07 +08:00
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_panel_on(intel_dp);
|
2012-10-24 04:30:07 +08:00
|
|
|
}
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2014-11-13 22:55:19 +08:00
|
|
|
if (IS_SKYLAKE(dev)) {
|
2015-01-15 20:55:25 +08:00
|
|
|
uint32_t dpll = crtc->config->ddi_pll_sel;
|
2014-11-13 22:55:19 +08:00
|
|
|
uint32_t val;
|
|
|
|
|
2014-11-15 01:24:33 +08:00
|
|
|
/*
|
|
|
|
* DPLL0 is used for eDP and is the only "private" DPLL (as
|
|
|
|
* opposed to shared) on SKL
|
|
|
|
*/
|
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
|
|
WARN_ON(dpll != SKL_DPLL0);
|
|
|
|
|
|
|
|
val = I915_READ(DPLL_CTRL1);
|
|
|
|
|
|
|
|
val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
|
|
|
|
DPLL_CTRL1_SSC(dpll) |
|
2015-04-30 23:39:17 +08:00
|
|
|
DPLL_CTRL1_LINK_RATE_MASK(dpll));
|
2015-01-15 20:55:25 +08:00
|
|
|
val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
|
2014-11-15 01:24:33 +08:00
|
|
|
|
|
|
|
I915_WRITE(DPLL_CTRL1, val);
|
|
|
|
POSTING_READ(DPLL_CTRL1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* DDI -> PLL mapping */
|
2014-11-13 22:55:19 +08:00
|
|
|
val = I915_READ(DPLL_CTRL2);
|
|
|
|
|
|
|
|
val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
|
|
|
|
DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
|
|
|
|
val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
|
|
|
|
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
|
|
|
|
|
|
|
|
I915_WRITE(DPLL_CTRL2, val);
|
2014-11-15 01:24:33 +08:00
|
|
|
|
2014-08-22 12:19:06 +08:00
|
|
|
} else if (INTEL_INFO(dev)->gen < 9) {
|
2015-01-15 20:55:25 +08:00
|
|
|
WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
|
|
|
|
I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
|
2014-11-13 22:55:19 +08:00
|
|
|
}
|
2012-10-16 02:51:41 +08:00
|
|
|
|
2012-10-24 04:30:07 +08:00
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
|
2012-10-16 02:51:41 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2014-04-25 05:54:58 +08:00
|
|
|
|
2014-05-02 11:36:43 +08:00
|
|
|
intel_ddi_init_dp_buf_reg(intel_encoder);
|
2012-10-16 02:51:41 +08:00
|
|
|
|
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
|
|
|
|
intel_dp_start_link_train(intel_dp);
|
|
|
|
intel_dp_complete_link_train(intel_dp);
|
2014-11-13 22:55:22 +08:00
|
|
|
if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
2014-04-25 05:54:58 +08:00
|
|
|
} else if (type == INTEL_OUTPUT_HDMI) {
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
|
|
|
2014-11-18 18:15:27 +08:00
|
|
|
if (IS_BROXTON(dev)) {
|
|
|
|
hdmi_level = dev_priv->vbt.
|
|
|
|
ddi_port_info[port].hdmi_level_shift;
|
|
|
|
bxt_ddi_vswing_sequence(dev, hdmi_level, port,
|
|
|
|
INTEL_OUTPUT_HDMI);
|
|
|
|
}
|
2014-04-25 05:54:58 +08:00
|
|
|
intel_hdmi->set_infoframes(encoder,
|
2015-01-15 20:55:25 +08:00
|
|
|
crtc->config->has_hdmi_sink,
|
|
|
|
&crtc->config->base.adjusted_mode);
|
2012-10-16 02:51:41 +08:00
|
|
|
}
|
2012-10-05 23:05:58 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
|
2012-10-05 23:05:58 +08:00
|
|
|
{
|
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2014-11-13 22:55:19 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-05 23:05:58 +08:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2012-10-24 04:30:07 +08:00
|
|
|
int type = intel_encoder->type;
|
2012-10-05 23:06:00 +08:00
|
|
|
uint32_t val;
|
2012-10-16 02:51:32 +08:00
|
|
|
bool wait = false;
|
2012-10-05 23:06:00 +08:00
|
|
|
|
|
|
|
val = I915_READ(DDI_BUF_CTL(port));
|
|
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(port), val);
|
2012-10-16 02:51:32 +08:00
|
|
|
wait = true;
|
2012-10-05 23:06:00 +08:00
|
|
|
}
|
2012-10-05 23:05:58 +08:00
|
|
|
|
2012-10-16 02:51:32 +08:00
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
|
|
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
|
|
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
|
|
|
|
if (wait)
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
|
2013-11-15 21:29:57 +08:00
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
|
2012-10-24 04:30:07 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2013-11-15 21:29:57 +08:00
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
|
2014-03-17 22:43:36 +08:00
|
|
|
intel_edp_panel_vdd_on(intel_dp);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_panel_off(intel_dp);
|
2012-10-24 04:30:07 +08:00
|
|
|
}
|
|
|
|
|
2014-11-13 22:55:19 +08:00
|
|
|
if (IS_SKYLAKE(dev))
|
|
|
|
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
|
|
|
|
DPLL_CTRL2_DDI_CLK_OFF(port)));
|
2014-08-22 12:19:06 +08:00
|
|
|
else if (INTEL_INFO(dev)->gen < 9)
|
2014-11-13 22:55:19 +08:00
|
|
|
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
|
2012-10-05 23:05:58 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
static void intel_enable_ddi(struct intel_encoder *intel_encoder)
|
2012-05-10 02:37:31 +08:00
|
|
|
{
|
2012-10-16 02:51:40 +08:00
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2013-01-22 23:25:25 +08:00
|
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2012-10-16 02:51:40 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2012-05-10 02:37:31 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-16 02:51:40 +08:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
|
|
int type = intel_encoder->type;
|
2012-05-10 02:37:31 +08:00
|
|
|
|
2012-10-16 02:51:40 +08:00
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
2012-12-12 02:48:30 +08:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
enc_to_dig_port(encoder);
|
|
|
|
|
2012-10-16 02:51:40 +08:00
|
|
|
/* In HDMI/DVI mode, the port width, and swing/emphasis values
|
|
|
|
* are ignored so nothing special needs to be done besides
|
|
|
|
* enabling the port.
|
|
|
|
*/
|
2012-12-12 02:48:30 +08:00
|
|
|
I915_WRITE(DDI_BUF_CTL(port),
|
2013-07-13 04:54:41 +08:00
|
|
|
intel_dig_port->saved_port_bits |
|
|
|
|
DDI_BUF_CTL_ENABLE);
|
2012-10-24 04:30:06 +08:00
|
|
|
} else if (type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
2014-11-13 22:55:22 +08:00
|
|
|
if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_backlight_on(intel_dp);
|
2014-11-15 00:52:28 +08:00
|
|
|
intel_psr_enable(intel_dp);
|
2015-01-22 17:47:40 +08:00
|
|
|
intel_edp_drrs_enable(intel_dp);
|
2012-10-16 02:51:40 +08:00
|
|
|
}
|
2013-01-22 23:25:25 +08:00
|
|
|
|
2015-01-15 20:55:25 +08:00
|
|
|
if (intel_crtc->config->has_audio) {
|
2014-05-22 04:29:31 +08:00
|
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
|
2014-10-27 22:26:50 +08:00
|
|
|
intel_audio_codec_enable(intel_encoder);
|
2013-01-22 23:25:25 +08:00
|
|
|
}
|
2012-06-30 14:59:56 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
static void intel_disable_ddi(struct intel_encoder *intel_encoder)
|
2012-06-30 14:59:56 +08:00
|
|
|
{
|
2012-10-24 04:30:06 +08:00
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2013-01-22 23:25:25 +08:00
|
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2012-10-24 04:30:06 +08:00
|
|
|
int type = intel_encoder->type;
|
2013-01-22 23:25:25 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-24 04:30:06 +08:00
|
|
|
|
2015-01-15 20:55:25 +08:00
|
|
|
if (intel_crtc->config->has_audio) {
|
2014-10-27 22:26:50 +08:00
|
|
|
intel_audio_codec_disable(intel_encoder);
|
2014-05-22 04:29:31 +08:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
|
|
|
|
}
|
2013-03-07 07:03:09 +08:00
|
|
|
|
2012-10-24 04:30:06 +08:00
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
2015-01-22 17:47:40 +08:00
|
|
|
intel_edp_drrs_disable(intel_dp);
|
2014-11-15 00:52:28 +08:00
|
|
|
intel_psr_disable(intel_dp);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_backlight_off(intel_dp);
|
2012-10-24 04:30:06 +08:00
|
|
|
}
|
2012-05-10 02:37:31 +08:00
|
|
|
}
|
2012-10-05 23:05:52 +08:00
|
|
|
|
2014-06-26 03:02:01 +08:00
|
|
|
static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
2014-10-29 17:32:32 +08:00
|
|
|
I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
|
2014-06-26 03:02:01 +08:00
|
|
|
POSTING_READ(WRPLL_CTL(pll->id));
|
|
|
|
udelay(20);
|
|
|
|
}
|
|
|
|
|
2014-06-26 03:02:00 +08:00
|
|
|
static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = I915_READ(WRPLL_CTL(pll->id));
|
|
|
|
I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
|
|
|
|
POSTING_READ(WRPLL_CTL(pll->id));
|
|
|
|
}
|
|
|
|
|
2014-07-04 22:27:39 +08:00
|
|
|
static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll,
|
|
|
|
struct intel_dpll_hw_state *hw_state)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
2014-09-30 16:56:39 +08:00
|
|
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
|
2014-07-04 22:27:39 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
val = I915_READ(WRPLL_CTL(pll->id));
|
|
|
|
hw_state->wrpll = val;
|
|
|
|
|
|
|
|
return val & WRPLL_PLL_ENABLE;
|
|
|
|
}
|
|
|
|
|
2014-07-15 22:05:33 +08:00
|
|
|
static const char * const hsw_ddi_pll_names[] = {
|
2014-06-26 03:01:57 +08:00
|
|
|
"WRPLL 1",
|
|
|
|
"WRPLL 2",
|
|
|
|
};
|
|
|
|
|
2014-07-30 01:06:19 +08:00
|
|
|
static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
|
2012-10-05 23:05:52 +08:00
|
|
|
{
|
2014-06-26 03:01:57 +08:00
|
|
|
int i;
|
|
|
|
|
2014-06-26 03:02:02 +08:00
|
|
|
dev_priv->num_shared_dpll = 2;
|
2014-06-26 03:01:57 +08:00
|
|
|
|
2014-06-26 03:02:02 +08:00
|
|
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
|
2014-06-26 03:01:57 +08:00
|
|
|
dev_priv->shared_dplls[i].id = i;
|
|
|
|
dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
|
2014-06-26 03:02:00 +08:00
|
|
|
dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
|
2014-06-26 03:02:01 +08:00
|
|
|
dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
|
2014-07-04 22:27:39 +08:00
|
|
|
dev_priv->shared_dplls[i].get_hw_state =
|
|
|
|
hsw_ddi_pll_get_hw_state;
|
2014-06-26 03:01:57 +08:00
|
|
|
}
|
2014-07-30 01:06:19 +08:00
|
|
|
}
|
|
|
|
|
2014-11-13 22:55:18 +08:00
|
|
|
static const char * const skl_ddi_pll_names[] = {
|
|
|
|
"DPLL 1",
|
|
|
|
"DPLL 2",
|
|
|
|
"DPLL 3",
|
|
|
|
};
|
|
|
|
|
|
|
|
struct skl_dpll_regs {
|
|
|
|
u32 ctl, cfgcr1, cfgcr2;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* this array is indexed by the *shared* pll id */
|
|
|
|
static const struct skl_dpll_regs skl_dpll_regs[3] = {
|
|
|
|
{
|
|
|
|
/* DPLL 1 */
|
|
|
|
.ctl = LCPLL2_CTL,
|
|
|
|
.cfgcr1 = DPLL1_CFGCR1,
|
|
|
|
.cfgcr2 = DPLL1_CFGCR2,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* DPLL 2 */
|
|
|
|
.ctl = WRPLL_CTL1,
|
|
|
|
.cfgcr1 = DPLL2_CFGCR1,
|
|
|
|
.cfgcr2 = DPLL2_CFGCR2,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* DPLL 3 */
|
|
|
|
.ctl = WRPLL_CTL2,
|
|
|
|
.cfgcr1 = DPLL3_CFGCR1,
|
|
|
|
.cfgcr2 = DPLL3_CFGCR2,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
unsigned int dpll;
|
|
|
|
const struct skl_dpll_regs *regs = skl_dpll_regs;
|
|
|
|
|
|
|
|
/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
|
|
|
|
dpll = pll->id + 1;
|
|
|
|
|
|
|
|
val = I915_READ(DPLL_CTRL1);
|
|
|
|
|
|
|
|
val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
|
2015-04-30 23:39:17 +08:00
|
|
|
DPLL_CTRL1_LINK_RATE_MASK(dpll));
|
2014-11-13 22:55:18 +08:00
|
|
|
val |= pll->config.hw_state.ctrl1 << (dpll * 6);
|
|
|
|
|
|
|
|
I915_WRITE(DPLL_CTRL1, val);
|
|
|
|
POSTING_READ(DPLL_CTRL1);
|
|
|
|
|
|
|
|
I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
|
|
|
|
I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
|
|
|
|
POSTING_READ(regs[pll->id].cfgcr1);
|
|
|
|
POSTING_READ(regs[pll->id].cfgcr2);
|
|
|
|
|
|
|
|
/* the enable bit is always bit 31 */
|
|
|
|
I915_WRITE(regs[pll->id].ctl,
|
|
|
|
I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
|
|
|
|
|
|
|
|
if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
|
|
|
|
DRM_ERROR("DPLL %d not locked\n", dpll);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
const struct skl_dpll_regs *regs = skl_dpll_regs;
|
|
|
|
|
|
|
|
/* the enable bit is always bit 31 */
|
|
|
|
I915_WRITE(regs[pll->id].ctl,
|
|
|
|
I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
|
|
|
|
POSTING_READ(regs[pll->id].ctl);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll,
|
|
|
|
struct intel_dpll_hw_state *hw_state)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
unsigned int dpll;
|
|
|
|
const struct skl_dpll_regs *regs = skl_dpll_regs;
|
|
|
|
|
|
|
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
|
|
|
|
dpll = pll->id + 1;
|
|
|
|
|
|
|
|
val = I915_READ(regs[pll->id].ctl);
|
|
|
|
if (!(val & LCPLL_PLL_ENABLE))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
val = I915_READ(DPLL_CTRL1);
|
|
|
|
hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
|
|
|
|
|
|
|
|
/* avoid reading back stale values if HDMI mode is not enabled */
|
|
|
|
if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
|
|
|
|
hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
|
|
|
|
hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dev_priv->num_shared_dpll = 3;
|
|
|
|
|
|
|
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
|
|
|
|
dev_priv->shared_dplls[i].id = i;
|
|
|
|
dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
|
|
|
|
dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
|
|
|
|
dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
|
|
|
|
dev_priv->shared_dplls[i].get_hw_state =
|
|
|
|
skl_ddi_pll_get_hw_state;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 16:07:39 +08:00
|
|
|
static void broxton_phy_init(struct drm_i915_private *dev_priv,
|
|
|
|
enum dpio_phy phy)
|
|
|
|
{
|
|
|
|
enum port port;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
|
|
|
|
val |= GT_DISPLAY_POWER_ON(phy);
|
|
|
|
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
|
|
|
|
|
|
|
|
/* Considering 10ms timeout until BSpec is updated */
|
|
|
|
if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
|
|
|
|
DRM_ERROR("timeout during PHY%d power on\n", phy);
|
|
|
|
|
|
|
|
for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
|
|
|
|
port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
|
|
|
|
int lane;
|
|
|
|
|
|
|
|
for (lane = 0; lane < 4; lane++) {
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
|
|
|
|
/*
|
|
|
|
* Note that on CHV this flag is called UPAR, but has
|
|
|
|
* the same function.
|
|
|
|
*/
|
|
|
|
val &= ~LATENCY_OPTIM;
|
|
|
|
if (lane != 1)
|
|
|
|
val |= LATENCY_OPTIM;
|
|
|
|
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Program PLL Rcomp code offset */
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
|
|
|
|
val &= ~IREF0RC_OFFSET_MASK;
|
|
|
|
val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
|
|
|
|
val &= ~IREF1RC_OFFSET_MASK;
|
|
|
|
val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
|
|
|
|
|
|
|
|
/* Program power gating */
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
|
|
|
|
val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
|
|
|
|
SUS_CLK_CONFIG;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY0) {
|
|
|
|
val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
|
|
|
|
val |= DW6_OLDO_DYN_PWR_DOWN_EN;
|
|
|
|
I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
|
|
|
|
val &= ~OCL2_LDOFUSE_PWR_DIS;
|
|
|
|
/*
|
|
|
|
* On PHY1 disable power on the second channel, since no port is
|
|
|
|
* connected there. On PHY0 both channels have a port, so leave it
|
|
|
|
* enabled.
|
|
|
|
* TODO: port C is only connected on BXT-P, so on BXT0/1 we should
|
|
|
|
* power down the second channel on PHY0 as well.
|
|
|
|
*/
|
|
|
|
if (phy == DPIO_PHY1)
|
|
|
|
val |= OCL2_LDOFUSE_PWR_DIS;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY0) {
|
|
|
|
uint32_t grc_code;
|
|
|
|
/*
|
|
|
|
* PHY0 isn't connected to an RCOMP resistor so copy over
|
|
|
|
* the corresponding calibrated value from PHY1, and disable
|
|
|
|
* the automatic calibration on PHY0.
|
|
|
|
*/
|
|
|
|
if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
|
|
|
|
10))
|
|
|
|
DRM_ERROR("timeout waiting for PHY1 GRC\n");
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
|
|
|
|
val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
|
|
|
|
grc_code = val << GRC_CODE_FAST_SHIFT |
|
|
|
|
val << GRC_CODE_SLOW_SHIFT |
|
|
|
|
val;
|
|
|
|
I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
|
|
|
|
val |= GRC_DIS | GRC_RDY_OVRD;
|
|
|
|
I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
|
|
|
|
}
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
|
|
|
|
val |= COMMON_RESET_DIS;
|
|
|
|
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
|
|
|
|
}
|
|
|
|
|
|
|
|
void broxton_ddi_phy_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
/* Enable PHY1 first since it provides Rcomp for PHY0 */
|
|
|
|
broxton_phy_init(dev->dev_private, DPIO_PHY1);
|
|
|
|
broxton_phy_init(dev->dev_private, DPIO_PHY0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
|
|
|
|
enum dpio_phy phy)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
|
|
|
|
val &= ~COMMON_RESET_DIS;
|
|
|
|
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
|
|
|
|
}
|
|
|
|
|
|
|
|
void broxton_ddi_phy_uninit(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
broxton_phy_uninit(dev_priv, DPIO_PHY1);
|
|
|
|
broxton_phy_uninit(dev_priv, DPIO_PHY0);
|
|
|
|
|
|
|
|
/* FIXME: do this in broxton_phy_uninit per phy */
|
|
|
|
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
|
|
|
|
}
|
|
|
|
|
2014-08-22 12:19:09 +08:00
|
|
|
static const char * const bxt_ddi_pll_names[] = {
|
|
|
|
"PORT PLL A",
|
|
|
|
"PORT PLL B",
|
|
|
|
"PORT PLL C",
|
|
|
|
};
|
|
|
|
|
|
|
|
static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
uint32_t temp;
|
|
|
|
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
|
|
|
|
|
|
|
|
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
|
|
|
|
temp &= ~PORT_PLL_REF_SEL;
|
|
|
|
/* Non-SSC reference */
|
|
|
|
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
|
|
|
|
|
|
|
|
/* Disable 10 bit clock */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
|
|
|
|
temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
|
|
|
|
I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
|
|
|
|
|
|
|
|
/* Write P1 & P2 */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
|
|
|
|
temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
|
|
|
|
temp |= pll->config.hw_state.ebb0;
|
|
|
|
I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
|
|
|
|
|
|
|
|
/* Write M2 integer */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 0));
|
|
|
|
temp &= ~PORT_PLL_M2_MASK;
|
|
|
|
temp |= pll->config.hw_state.pll0;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 0), temp);
|
|
|
|
|
|
|
|
/* Write N */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 1));
|
|
|
|
temp &= ~PORT_PLL_N_MASK;
|
|
|
|
temp |= pll->config.hw_state.pll1;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 1), temp);
|
|
|
|
|
|
|
|
/* Write M2 fraction */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 2));
|
|
|
|
temp &= ~PORT_PLL_M2_FRAC_MASK;
|
|
|
|
temp |= pll->config.hw_state.pll2;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 2), temp);
|
|
|
|
|
|
|
|
/* Write M2 fraction enable */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 3));
|
|
|
|
temp &= ~PORT_PLL_M2_FRAC_ENABLE;
|
|
|
|
temp |= pll->config.hw_state.pll3;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 3), temp);
|
|
|
|
|
|
|
|
/* Write coeff */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 6));
|
|
|
|
temp &= ~PORT_PLL_PROP_COEFF_MASK;
|
|
|
|
temp &= ~PORT_PLL_INT_COEFF_MASK;
|
|
|
|
temp &= ~PORT_PLL_GAIN_CTL_MASK;
|
|
|
|
temp |= pll->config.hw_state.pll6;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 6), temp);
|
|
|
|
|
|
|
|
/* Write calibration val */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 8));
|
|
|
|
temp &= ~PORT_PLL_TARGET_CNT_MASK;
|
|
|
|
temp |= pll->config.hw_state.pll8;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 8), temp);
|
|
|
|
|
2015-05-13 14:48:52 +08:00
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 9));
|
|
|
|
temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
|
|
|
|
temp |= (5 << 1);
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 9), temp);
|
|
|
|
|
|
|
|
temp = I915_READ(BXT_PORT_PLL(port, 10));
|
|
|
|
temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
|
|
|
|
temp &= ~PORT_PLL_DCO_AMP_MASK;
|
|
|
|
temp |= pll->config.hw_state.pll10;
|
|
|
|
I915_WRITE(BXT_PORT_PLL(port, 10), temp);
|
2014-08-22 12:19:09 +08:00
|
|
|
|
|
|
|
/* Recalibrate with new settings */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
|
|
|
|
temp |= PORT_PLL_RECALIBRATE;
|
|
|
|
I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
|
|
|
|
/* Enable 10 bit clock */
|
|
|
|
temp |= PORT_PLL_10BIT_CLK_ENABLE;
|
|
|
|
I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
|
|
|
|
|
|
|
|
/* Enable PLL */
|
|
|
|
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
|
|
|
|
temp |= PORT_PLL_ENABLE;
|
|
|
|
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
|
|
|
|
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
|
|
|
|
|
|
|
|
if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
|
|
|
|
PORT_PLL_LOCK), 200))
|
|
|
|
DRM_ERROR("PLL %d not locked\n", port);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* While we write to the group register to program all lanes at once we
|
|
|
|
* can read only lane registers and we pick lanes 0/1 for that.
|
|
|
|
*/
|
|
|
|
temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
|
|
|
|
temp &= ~LANE_STAGGER_MASK;
|
|
|
|
temp &= ~LANESTAGGER_STRAP_OVRD;
|
|
|
|
temp |= pll->config.hw_state.pcsdw12;
|
|
|
|
I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
|
|
|
|
uint32_t temp;
|
|
|
|
|
|
|
|
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
|
|
|
|
temp &= ~PORT_PLL_ENABLE;
|
|
|
|
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
|
|
|
|
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll,
|
|
|
|
struct intel_dpll_hw_state *hw_state)
|
|
|
|
{
|
|
|
|
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_PLL_ENABLE(port));
|
|
|
|
if (!(val & PORT_PLL_ENABLE))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
|
|
|
|
hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
|
|
|
|
hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
|
|
|
|
hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
|
|
|
|
hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
|
|
|
|
hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
|
|
|
|
hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
|
2015-05-13 14:48:52 +08:00
|
|
|
hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
|
2014-08-22 12:19:09 +08:00
|
|
|
/*
|
|
|
|
* While we write to the group register to program all lanes at once we
|
|
|
|
* can read only lane registers. We configure all lanes the same way, so
|
|
|
|
* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
|
|
|
|
*/
|
|
|
|
hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
|
|
|
|
if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
|
|
|
|
DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
|
|
|
|
hw_state->pcsdw12,
|
|
|
|
I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dev_priv->num_shared_dpll = 3;
|
|
|
|
|
|
|
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
|
|
|
|
dev_priv->shared_dplls[i].id = i;
|
|
|
|
dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
|
|
|
|
dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
|
|
|
|
dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
|
|
|
|
dev_priv->shared_dplls[i].get_hw_state =
|
|
|
|
bxt_ddi_pll_get_hw_state;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-30 01:06:19 +08:00
|
|
|
void intel_ddi_pll_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t val = I915_READ(LCPLL_CTL);
|
drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-21 23:37:48 +08:00
|
|
|
int cdclk_freq;
|
2014-07-30 01:06:19 +08:00
|
|
|
|
2014-11-13 22:55:18 +08:00
|
|
|
if (IS_SKYLAKE(dev))
|
|
|
|
skl_shared_dplls_init(dev_priv);
|
2014-08-22 12:19:09 +08:00
|
|
|
else if (IS_BROXTON(dev))
|
|
|
|
bxt_shared_dplls_init(dev_priv);
|
2014-11-13 22:55:18 +08:00
|
|
|
else
|
|
|
|
hsw_shared_dplls_init(dev_priv);
|
2012-10-05 23:05:52 +08:00
|
|
|
|
drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-21 23:37:48 +08:00
|
|
|
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
|
|
|
|
DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
|
2012-10-05 23:05:52 +08:00
|
|
|
|
2014-11-13 22:55:15 +08:00
|
|
|
if (IS_SKYLAKE(dev)) {
|
drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-21 23:37:48 +08:00
|
|
|
dev_priv->skl_boot_cdclk = cdclk_freq;
|
2014-11-13 22:55:15 +08:00
|
|
|
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
|
|
|
|
DRM_ERROR("LCPLL1 is disabled\n");
|
drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-21 23:37:48 +08:00
|
|
|
else
|
|
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
|
2014-11-24 16:07:39 +08:00
|
|
|
} else if (IS_BROXTON(dev)) {
|
|
|
|
broxton_init_cdclk(dev);
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 16:07:39 +08:00
|
|
|
broxton_ddi_phy_init(dev);
|
2014-11-13 22:55:15 +08:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The LCPLL register should be turned on by the BIOS. For now
|
|
|
|
* let's just check its state and print errors in case
|
|
|
|
* something is wrong. Don't even try to turn it on.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (val & LCPLL_CD_SOURCE_FCLK)
|
|
|
|
DRM_ERROR("CDCLK source is not LCPLL\n");
|
2012-10-05 23:05:52 +08:00
|
|
|
|
2014-11-13 22:55:15 +08:00
|
|
|
if (val & LCPLL_PLL_DISABLE)
|
|
|
|
DRM_ERROR("LCPLL is disabled\n");
|
|
|
|
}
|
2012-10-05 23:05:52 +08:00
|
|
|
}
|
2012-10-16 02:51:41 +08:00
|
|
|
|
|
|
|
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
|
|
|
|
{
|
2012-10-27 05:05:50 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
2012-10-16 02:51:41 +08:00
|
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
2012-10-27 05:05:50 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2012-10-16 02:51:41 +08:00
|
|
|
uint32_t val;
|
2013-02-25 06:35:38 +08:00
|
|
|
bool wait = false;
|
2012-10-16 02:51:41 +08:00
|
|
|
|
|
|
|
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
|
|
|
|
val = I915_READ(DDI_BUF_CTL(port));
|
|
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(port), val);
|
|
|
|
wait = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
|
|
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
|
|
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
POSTING_READ(DP_TP_CTL(port));
|
|
|
|
|
|
|
|
if (wait)
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
}
|
|
|
|
|
2014-05-02 12:02:48 +08:00
|
|
|
val = DP_TP_CTL_ENABLE |
|
2012-10-16 02:51:41 +08:00
|
|
|
DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
|
2014-05-02 12:02:48 +08:00
|
|
|
if (intel_dp->is_mst)
|
|
|
|
val |= DP_TP_CTL_MODE_MST;
|
|
|
|
else {
|
|
|
|
val |= DP_TP_CTL_MODE_SST;
|
|
|
|
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
|
|
|
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
|
|
|
}
|
2012-10-16 02:51:41 +08:00
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
POSTING_READ(DP_TP_CTL(port));
|
|
|
|
|
|
|
|
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
|
|
|
|
POSTING_READ(DDI_BUF_CTL(port));
|
|
|
|
|
|
|
|
udelay(600);
|
|
|
|
}
|
2012-10-27 05:05:52 +08:00
|
|
|
|
2012-11-02 07:05:05 +08:00
|
|
|
void intel_ddi_fdi_disable(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
intel_ddi_post_disable(intel_encoder);
|
|
|
|
|
|
|
|
val = I915_READ(_FDI_RXA_CTL);
|
|
|
|
val &= ~FDI_RX_ENABLE;
|
|
|
|
I915_WRITE(_FDI_RXA_CTL, val);
|
|
|
|
|
|
|
|
val = I915_READ(_FDI_RXA_MISC);
|
|
|
|
val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
|
|
|
val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
|
|
|
|
I915_WRITE(_FDI_RXA_MISC, val);
|
|
|
|
|
|
|
|
val = I915_READ(_FDI_RXA_CTL);
|
|
|
|
val &= ~FDI_PCDCLK;
|
|
|
|
I915_WRITE(_FDI_RXA_CTL, val);
|
|
|
|
|
|
|
|
val = I915_READ(_FDI_RXA_CTL);
|
|
|
|
val &= ~FDI_RX_PLL_ENABLE;
|
|
|
|
I915_WRITE(_FDI_RXA_CTL, val);
|
|
|
|
}
|
|
|
|
|
2013-09-24 19:24:05 +08:00
|
|
|
void intel_ddi_get_config(struct intel_encoder *encoder,
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2013-05-15 08:08:26 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
2015-01-30 18:17:23 +08:00
|
|
|
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
|
2014-11-21 05:33:59 +08:00
|
|
|
struct intel_hdmi *intel_hdmi;
|
2013-05-15 08:08:26 +08:00
|
|
|
u32 temp, flags = 0;
|
|
|
|
|
|
|
|
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
if (temp & TRANS_DDI_PHSYNC)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
|
|
if (temp & TRANS_DDI_PVSYNC)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
|
2015-01-15 20:55:22 +08:00
|
|
|
pipe_config->base.adjusted_mode.flags |= flags;
|
2013-09-07 04:29:00 +08:00
|
|
|
|
|
|
|
switch (temp & TRANS_DDI_BPC_MASK) {
|
|
|
|
case TRANS_DDI_BPC_6:
|
|
|
|
pipe_config->pipe_bpp = 18;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_8:
|
|
|
|
pipe_config->pipe_bpp = 24;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_10:
|
|
|
|
pipe_config->pipe_bpp = 30;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_12:
|
|
|
|
pipe_config->pipe_bpp = 36;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-09-10 22:02:54 +08:00
|
|
|
|
|
|
|
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
2014-04-25 05:54:47 +08:00
|
|
|
pipe_config->has_hdmi_sink = true;
|
2014-11-21 05:33:59 +08:00
|
|
|
intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
|
|
|
|
if (intel_hdmi->infoframe_enabled(&encoder->base))
|
|
|
|
pipe_config->has_infoframe = true;
|
2014-11-18 05:08:47 +08:00
|
|
|
break;
|
2013-09-10 22:02:54 +08:00
|
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
|
|
|
case TRANS_DDI_MODE_SELECT_FDI:
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
|
|
|
pipe_config->has_dp_encoder = true;
|
|
|
|
intel_dp_get_m_n(intel_crtc, pipe_config);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-11-18 14:38:16 +08:00
|
|
|
|
2014-09-30 16:56:39 +08:00
|
|
|
if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
|
2014-05-22 03:23:20 +08:00
|
|
|
temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
|
2014-10-27 22:26:59 +08:00
|
|
|
if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
|
2014-05-22 03:23:20 +08:00
|
|
|
pipe_config->has_audio = true;
|
|
|
|
}
|
2014-04-25 05:54:52 +08:00
|
|
|
|
2013-11-18 14:38:16 +08:00
|
|
|
if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
|
|
|
|
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
|
|
|
|
/*
|
|
|
|
* This is a big fat ugly hack.
|
|
|
|
*
|
|
|
|
* Some machines in UEFI boot mode provide us a VBT that has 18
|
|
|
|
* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
|
|
|
|
* unknown we fail to light up. Yet the same BIOS boots up with
|
|
|
|
* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
|
|
|
|
* max, not what it tells us to use.
|
|
|
|
*
|
|
|
|
* Note: This will still be broken if the eDP panel is not lit
|
|
|
|
* up by the BIOS, and thus we can't get the mode at module
|
|
|
|
* load.
|
|
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
|
|
|
|
pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
|
|
|
|
dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
|
|
|
|
}
|
2014-01-22 04:42:10 +08:00
|
|
|
|
2014-12-12 22:26:57 +08:00
|
|
|
intel_ddi_clock_get(encoder, pipe_config);
|
2013-05-15 08:08:26 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
static void intel_ddi_destroy(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
/* HDMI has nothing special to destroy, so we can go with this. */
|
|
|
|
intel_dp_encoder_destroy(encoder);
|
|
|
|
}
|
|
|
|
|
2013-03-27 07:44:55 +08:00
|
|
|
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2012-10-27 05:05:52 +08:00
|
|
|
{
|
2013-03-27 07:44:55 +08:00
|
|
|
int type = encoder->type;
|
2013-05-22 06:50:22 +08:00
|
|
|
int port = intel_ddi_get_encoder_port(encoder);
|
2012-10-27 05:05:52 +08:00
|
|
|
|
2013-03-27 07:44:55 +08:00
|
|
|
WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
|
2012-10-27 05:05:52 +08:00
|
|
|
|
2013-05-22 06:50:22 +08:00
|
|
|
if (port == PORT_A)
|
|
|
|
pipe_config->cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
if (type == INTEL_OUTPUT_HDMI)
|
2013-03-27 07:44:55 +08:00
|
|
|
return intel_hdmi_compute_config(encoder, pipe_config);
|
2012-10-27 05:05:52 +08:00
|
|
|
else
|
2013-03-27 07:44:55 +08:00
|
|
|
return intel_dp_compute_config(encoder, pipe_config);
|
2012-10-27 05:05:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_ddi_funcs = {
|
|
|
|
.destroy = intel_ddi_destroy,
|
|
|
|
};
|
|
|
|
|
2013-10-10 00:52:36 +08:00
|
|
|
static struct intel_connector *
|
|
|
|
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
struct intel_connector *connector;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
|
2015-04-10 15:59:10 +08:00
|
|
|
connector = intel_connector_alloc();
|
2013-10-10 00:52:36 +08:00
|
|
|
if (!connector)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
|
|
|
|
if (!intel_dp_init_connector(intel_dig_port, connector)) {
|
|
|
|
kfree(connector);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct intel_connector *
|
|
|
|
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
struct intel_connector *connector;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
|
2015-04-10 15:59:10 +08:00
|
|
|
connector = intel_connector_alloc();
|
2013-10-10 00:52:36 +08:00
|
|
|
if (!connector)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
|
|
|
|
intel_hdmi_init_connector(intel_dig_port, connector);
|
|
|
|
|
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
void intel_ddi_init(struct drm_device *dev, enum port port)
|
|
|
|
{
|
2012-12-12 02:48:30 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-27 05:05:52 +08:00
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_encoder *encoder;
|
2013-09-13 04:12:18 +08:00
|
|
|
bool init_hdmi, init_dp;
|
|
|
|
|
|
|
|
init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
|
|
|
|
dev_priv->vbt.ddi_port_info[port].supports_hdmi);
|
|
|
|
init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
|
|
|
|
if (!init_dp && !init_hdmi) {
|
2014-08-04 14:15:09 +08:00
|
|
|
DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
|
2013-09-13 04:12:18 +08:00
|
|
|
port_name(port));
|
|
|
|
init_hdmi = true;
|
|
|
|
init_dp = true;
|
|
|
|
}
|
2012-10-27 05:05:52 +08:00
|
|
|
|
2013-09-19 18:18:32 +08:00
|
|
|
intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
|
2012-10-27 05:05:52 +08:00
|
|
|
if (!intel_dig_port)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
encoder = &intel_encoder->base;
|
|
|
|
|
|
|
|
drm_encoder_init(dev, encoder, &intel_ddi_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
|
2013-03-27 07:44:55 +08:00
|
|
|
intel_encoder->compute_config = intel_ddi_compute_config;
|
2012-10-27 05:05:52 +08:00
|
|
|
intel_encoder->enable = intel_enable_ddi;
|
|
|
|
intel_encoder->pre_enable = intel_ddi_pre_enable;
|
|
|
|
intel_encoder->disable = intel_disable_ddi;
|
|
|
|
intel_encoder->post_disable = intel_ddi_post_disable;
|
|
|
|
intel_encoder->get_hw_state = intel_ddi_get_hw_state;
|
2013-05-15 08:08:26 +08:00
|
|
|
intel_encoder->get_config = intel_ddi_get_config;
|
2012-10-27 05:05:52 +08:00
|
|
|
|
|
|
|
intel_dig_port->port = port;
|
2013-07-13 04:54:41 +08:00
|
|
|
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
|
|
|
|
(DDI_BUF_PORT_REVERSAL |
|
|
|
|
DDI_A_4_LANES);
|
2012-10-27 05:05:52 +08:00
|
|
|
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
|
2014-08-04 14:15:09 +08:00
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
2014-03-03 22:15:28 +08:00
|
|
|
intel_encoder->cloneable = 0;
|
2012-10-27 05:05:52 +08:00
|
|
|
|
2014-08-04 14:15:09 +08:00
|
|
|
if (init_dp) {
|
|
|
|
if (!intel_ddi_init_dp_connector(intel_dig_port))
|
|
|
|
goto err;
|
2014-06-18 09:29:35 +08:00
|
|
|
|
2014-08-04 14:15:09 +08:00
|
|
|
intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
|
2015-05-27 20:03:42 +08:00
|
|
|
dev_priv->hotplug.irq_port[port] = intel_dig_port;
|
2014-08-04 14:15:09 +08:00
|
|
|
}
|
2013-04-11 05:28:35 +08:00
|
|
|
|
2013-09-13 04:12:18 +08:00
|
|
|
/* In theory we don't need the encoder->type check, but leave it just in
|
|
|
|
* case we have some really bad VBTs... */
|
2014-08-04 14:15:09 +08:00
|
|
|
if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
|
|
|
|
if (!intel_ddi_init_hdmi_connector(intel_dig_port))
|
|
|
|
goto err;
|
2013-04-11 05:28:35 +08:00
|
|
|
}
|
2014-08-04 14:15:09 +08:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
|
|
kfree(intel_dig_port);
|
2012-10-27 05:05:52 +08:00
|
|
|
}
|