2019-06-04 16:11:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2009-04-08 01:45:21 +08:00
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/*
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* wm8988.c -- WM8988 ALSA SoC audio driver
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*
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* Copyright 2009 Wolfson Microelectronics plc
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* Copyright 2005 Openedhand Ltd.
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/spi/spi.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2009-04-08 01:45:21 +08:00
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/tlv.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include "wm8988.h"
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/*
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* wm8988 register cache
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* We can't read the WM8988 register space when we
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* are using 2 wire for device control, so we cache them instead.
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*/
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2012-02-13 02:21:57 +08:00
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static const struct reg_default wm8988_reg_defaults[] = {
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{ 0, 0x0097 },
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{ 1, 0x0097 },
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{ 2, 0x0079 },
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{ 3, 0x0079 },
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{ 5, 0x0008 },
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{ 7, 0x000a },
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{ 8, 0x0000 },
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{ 10, 0x00ff },
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{ 11, 0x00ff },
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{ 12, 0x000f },
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{ 13, 0x000f },
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{ 16, 0x0000 },
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{ 17, 0x007b },
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{ 18, 0x0000 },
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{ 19, 0x0032 },
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{ 20, 0x0000 },
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{ 21, 0x00c3 },
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{ 22, 0x00c3 },
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{ 23, 0x00c0 },
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{ 24, 0x0000 },
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{ 25, 0x0000 },
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{ 26, 0x0000 },
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{ 27, 0x0000 },
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{ 31, 0x0000 },
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{ 32, 0x0000 },
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{ 33, 0x0000 },
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{ 34, 0x0050 },
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{ 35, 0x0050 },
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{ 36, 0x0050 },
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{ 37, 0x0050 },
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{ 40, 0x0079 },
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{ 41, 0x0079 },
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{ 42, 0x0079 },
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2009-04-08 01:45:21 +08:00
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};
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2012-02-13 02:21:57 +08:00
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static bool wm8988_writeable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case WM8988_LINVOL:
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case WM8988_RINVOL:
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case WM8988_LOUT1V:
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case WM8988_ROUT1V:
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case WM8988_ADCDAC:
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case WM8988_IFACE:
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case WM8988_SRATE:
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case WM8988_LDAC:
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case WM8988_RDAC:
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case WM8988_BASS:
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case WM8988_TREBLE:
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case WM8988_RESET:
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case WM8988_3D:
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case WM8988_ALC1:
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case WM8988_ALC2:
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case WM8988_ALC3:
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case WM8988_NGATE:
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case WM8988_LADC:
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case WM8988_RADC:
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case WM8988_ADCTL1:
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case WM8988_ADCTL2:
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case WM8988_PWR1:
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case WM8988_PWR2:
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case WM8988_ADCTL3:
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case WM8988_ADCIN:
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case WM8988_LADCIN:
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case WM8988_RADCIN:
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case WM8988_LOUTM1:
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case WM8988_LOUTM2:
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case WM8988_ROUTM1:
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case WM8988_ROUTM2:
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case WM8988_LOUT2V:
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case WM8988_ROUT2V:
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case WM8988_LPPB:
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return true;
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default:
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return false;
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}
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}
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2009-04-08 01:45:21 +08:00
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/* codec private data */
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struct wm8988_priv {
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2012-02-13 02:21:57 +08:00
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struct regmap *regmap;
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2009-04-08 01:45:21 +08:00
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unsigned int sysclk;
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2014-02-06 04:54:36 +08:00
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const struct snd_pcm_hw_constraint_list *sysclk_constraints;
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2009-04-08 01:45:21 +08:00
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};
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2018-01-29 11:07:26 +08:00
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#define wm8988_reset(c) snd_soc_component_write(c, WM8988_RESET, 0)
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2009-04-08 01:45:21 +08:00
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/*
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* WM8988 Controls
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*/
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static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(bass_boost,
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WM8988_BASS, 7, bass_boost_txt);
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2009-04-08 01:45:21 +08:00
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static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(bass_filter,
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WM8988_BASS, 6, bass_filter_txt);
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2009-04-08 01:45:21 +08:00
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static const char *treble_txt[] = {"8kHz", "4kHz"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(treble,
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WM8988_TREBLE, 6, treble_txt);
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2009-04-08 01:45:21 +08:00
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static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(stereo_3d_lc,
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WM8988_3D, 5, stereo_3d_lc_txt);
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2009-04-08 01:45:21 +08:00
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static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(stereo_3d_uc,
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WM8988_3D, 6, stereo_3d_uc_txt);
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2009-04-08 01:45:21 +08:00
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static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(stereo_3d_func,
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WM8988_3D, 7, stereo_3d_func_txt);
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2009-04-08 01:45:21 +08:00
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static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(alc_func,
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WM8988_ALC1, 7, alc_func_txt);
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2009-04-08 01:45:21 +08:00
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static const char *ng_type_txt[] = {"Constant PGA Gain",
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"Mute ADC Output"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(ng_type,
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WM8988_NGATE, 1, ng_type_txt);
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2009-04-08 01:45:21 +08:00
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static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(deemph,
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WM8988_ADCDAC, 1, deemph_txt);
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2009-04-08 01:45:21 +08:00
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static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
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"L + R Invert"};
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2014-02-18 17:46:35 +08:00
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static SOC_ENUM_SINGLE_DECL(adcpol,
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WM8988_ADCDAC, 5, adcpol_txt);
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2009-04-08 01:45:21 +08:00
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static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
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static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
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static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
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static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const struct snd_kcontrol_new wm8988_snd_controls[] = {
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SOC_ENUM("Bass Boost", bass_boost),
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SOC_ENUM("Bass Filter", bass_filter),
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SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
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SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
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SOC_ENUM("Treble Cut-off", treble),
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SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
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SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
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SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
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SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
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SOC_ENUM("3D Mode", stereo_3d_func),
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SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
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SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
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SOC_ENUM("ALC Capture Function", alc_func),
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SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
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SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
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SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
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SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
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SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
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SOC_ENUM("ALC Capture NG Type", ng_type),
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SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
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SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
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SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
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0, 255, 0, adc_tlv),
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SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
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0, 63, 0, pga_tlv),
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SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
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SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
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SOC_ENUM("Playback De-emphasis", deemph),
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SOC_ENUM("Capture Polarity", adcpol),
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SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
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SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
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SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
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SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
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bypass_tlv),
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SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
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bypass_tlv),
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SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
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bypass_tlv),
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SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
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bypass_tlv),
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SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
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WM8988_ROUT1V, 7, 1, 0),
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SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
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0, 127, 0, out_tlv),
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SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
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WM8988_ROUT2V, 7, 1, 0),
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SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
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0, 127, 0, out_tlv),
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};
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/*
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* DAPM Controls
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*/
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static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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2018-01-29 11:07:26 +08:00
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struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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2020-06-16 13:21:29 +08:00
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u16 adctl2 = snd_soc_component_read(component, WM8988_ADCTL2);
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2009-04-08 01:45:21 +08:00
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/* Use the DAC to gate LRC if active, otherwise use ADC */
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2020-06-16 13:21:29 +08:00
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if (snd_soc_component_read(component, WM8988_PWR2) & 0x180)
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2009-04-08 01:45:21 +08:00
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adctl2 &= ~0x4;
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else
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adctl2 |= 0x4;
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2018-01-29 11:07:26 +08:00
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return snd_soc_component_write(component, WM8988_ADCTL2, adctl2);
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2009-04-08 01:45:21 +08:00
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}
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static const char *wm8988_line_texts[] = {
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"Line 1", "Line 2", "PGA", "Differential"};
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|
|
|
|
|
|
static const unsigned int wm8988_line_values[] = {
|
|
|
|
0, 1, 3, 4};
|
|
|
|
|
|
|
|
static const struct soc_enum wm8988_lline_enum =
|
|
|
|
SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
|
|
|
|
ARRAY_SIZE(wm8988_line_texts),
|
|
|
|
wm8988_line_texts,
|
|
|
|
wm8988_line_values);
|
|
|
|
static const struct snd_kcontrol_new wm8988_left_line_controls =
|
2014-04-15 03:31:07 +08:00
|
|
|
SOC_DAPM_ENUM("Route", wm8988_lline_enum);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
static const struct soc_enum wm8988_rline_enum =
|
|
|
|
SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
|
|
|
|
ARRAY_SIZE(wm8988_line_texts),
|
|
|
|
wm8988_line_texts,
|
|
|
|
wm8988_line_values);
|
|
|
|
static const struct snd_kcontrol_new wm8988_right_line_controls =
|
2019-08-22 22:36:08 +08:00
|
|
|
SOC_DAPM_ENUM("Route", wm8988_rline_enum);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
/* Left Mixer */
|
|
|
|
static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
|
|
|
|
SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Right Mixer */
|
|
|
|
static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
|
|
|
|
SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
|
|
|
|
SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
|
|
|
|
static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
|
|
|
|
|
|
|
|
/* Left PGA Mux */
|
|
|
|
static const struct soc_enum wm8988_lpga_enum =
|
|
|
|
SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
|
|
|
|
ARRAY_SIZE(wm8988_pga_sel),
|
|
|
|
wm8988_pga_sel,
|
|
|
|
wm8988_pga_val);
|
|
|
|
static const struct snd_kcontrol_new wm8988_left_pga_controls =
|
2014-04-15 03:31:07 +08:00
|
|
|
SOC_DAPM_ENUM("Route", wm8988_lpga_enum);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
/* Right PGA Mux */
|
|
|
|
static const struct soc_enum wm8988_rpga_enum =
|
|
|
|
SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
|
|
|
|
ARRAY_SIZE(wm8988_pga_sel),
|
|
|
|
wm8988_pga_sel,
|
|
|
|
wm8988_pga_val);
|
|
|
|
static const struct snd_kcontrol_new wm8988_right_pga_controls =
|
2014-04-15 03:31:07 +08:00
|
|
|
SOC_DAPM_ENUM("Route", wm8988_rpga_enum);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
/* Differential Mux */
|
|
|
|
static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
|
2014-02-18 17:46:35 +08:00
|
|
|
static SOC_ENUM_SINGLE_DECL(diffmux,
|
|
|
|
WM8988_ADCIN, 8, wm8988_diff_sel);
|
2009-04-08 01:45:21 +08:00
|
|
|
static const struct snd_kcontrol_new wm8988_diffmux_controls =
|
|
|
|
SOC_DAPM_ENUM("Route", diffmux);
|
|
|
|
|
|
|
|
/* Mono ADC Mux */
|
|
|
|
static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
|
|
|
|
"Mono (Right)", "Digital Mono"};
|
2014-02-18 17:46:35 +08:00
|
|
|
static SOC_ENUM_SINGLE_DECL(monomux,
|
|
|
|
WM8988_ADCIN, 6, wm8988_mono_mux);
|
2009-04-08 01:45:21 +08:00
|
|
|
static const struct snd_kcontrol_new wm8988_monomux_controls =
|
|
|
|
SOC_DAPM_ENUM("Route", monomux);
|
|
|
|
|
|
|
|
static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
|
2011-10-27 15:47:53 +08:00
|
|
|
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8988_PWR1, 1, 0, NULL, 0),
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_diffmux_controls),
|
|
|
|
SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_monomux_controls),
|
|
|
|
SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_monomux_controls),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
|
|
|
|
&wm8988_left_pga_controls),
|
|
|
|
SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
|
|
|
|
&wm8988_right_pga_controls),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_left_line_controls),
|
|
|
|
SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_right_line_controls),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
|
|
|
|
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
|
|
|
|
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_left_mixer_controls[0],
|
|
|
|
ARRAY_SIZE(wm8988_left_mixer_controls)),
|
|
|
|
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
|
|
|
|
&wm8988_right_mixer_controls[0],
|
|
|
|
ARRAY_SIZE(wm8988_right_mixer_controls)),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
|
|
|
|
SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
|
|
|
|
SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
|
|
|
|
SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("LOUT1"),
|
|
|
|
SND_SOC_DAPM_OUTPUT("ROUT1"),
|
|
|
|
SND_SOC_DAPM_OUTPUT("LOUT2"),
|
|
|
|
SND_SOC_DAPM_OUTPUT("ROUT2"),
|
|
|
|
SND_SOC_DAPM_OUTPUT("VREF"),
|
|
|
|
|
|
|
|
SND_SOC_DAPM_INPUT("LINPUT1"),
|
|
|
|
SND_SOC_DAPM_INPUT("LINPUT2"),
|
|
|
|
SND_SOC_DAPM_INPUT("RINPUT1"),
|
|
|
|
SND_SOC_DAPM_INPUT("RINPUT2"),
|
|
|
|
};
|
|
|
|
|
2012-01-22 07:24:25 +08:00
|
|
|
static const struct snd_soc_dapm_route wm8988_dapm_routes[] = {
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
{ "Left Line Mux", "Line 1", "LINPUT1" },
|
|
|
|
{ "Left Line Mux", "Line 2", "LINPUT2" },
|
|
|
|
{ "Left Line Mux", "PGA", "Left PGA Mux" },
|
|
|
|
{ "Left Line Mux", "Differential", "Differential Mux" },
|
|
|
|
|
|
|
|
{ "Right Line Mux", "Line 1", "RINPUT1" },
|
|
|
|
{ "Right Line Mux", "Line 2", "RINPUT2" },
|
|
|
|
{ "Right Line Mux", "PGA", "Right PGA Mux" },
|
|
|
|
{ "Right Line Mux", "Differential", "Differential Mux" },
|
|
|
|
|
|
|
|
{ "Left PGA Mux", "Line 1", "LINPUT1" },
|
|
|
|
{ "Left PGA Mux", "Line 2", "LINPUT2" },
|
|
|
|
{ "Left PGA Mux", "Differential", "Differential Mux" },
|
|
|
|
|
|
|
|
{ "Right PGA Mux", "Line 1", "RINPUT1" },
|
|
|
|
{ "Right PGA Mux", "Line 2", "RINPUT2" },
|
|
|
|
{ "Right PGA Mux", "Differential", "Differential Mux" },
|
|
|
|
|
|
|
|
{ "Differential Mux", "Line 1", "LINPUT1" },
|
|
|
|
{ "Differential Mux", "Line 1", "RINPUT1" },
|
|
|
|
{ "Differential Mux", "Line 2", "LINPUT2" },
|
|
|
|
{ "Differential Mux", "Line 2", "RINPUT2" },
|
|
|
|
|
|
|
|
{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
|
|
|
|
{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
|
|
|
|
{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
|
|
|
|
|
|
|
|
{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
|
|
|
|
{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
|
|
|
|
{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
|
|
|
|
|
|
|
|
{ "Left ADC", NULL, "Left ADC Mux" },
|
|
|
|
{ "Right ADC", NULL, "Right ADC Mux" },
|
|
|
|
|
|
|
|
{ "Left Line Mux", "Line 1", "LINPUT1" },
|
|
|
|
{ "Left Line Mux", "Line 2", "LINPUT2" },
|
|
|
|
{ "Left Line Mux", "PGA", "Left PGA Mux" },
|
|
|
|
{ "Left Line Mux", "Differential", "Differential Mux" },
|
|
|
|
|
|
|
|
{ "Right Line Mux", "Line 1", "RINPUT1" },
|
|
|
|
{ "Right Line Mux", "Line 2", "RINPUT2" },
|
|
|
|
{ "Right Line Mux", "PGA", "Right PGA Mux" },
|
|
|
|
{ "Right Line Mux", "Differential", "Differential Mux" },
|
|
|
|
|
|
|
|
{ "Left Mixer", "Playback Switch", "Left DAC" },
|
|
|
|
{ "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
|
|
|
|
{ "Left Mixer", "Right Playback Switch", "Right DAC" },
|
|
|
|
{ "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
|
|
|
|
|
|
|
|
{ "Right Mixer", "Left Playback Switch", "Left DAC" },
|
|
|
|
{ "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
|
|
|
|
{ "Right Mixer", "Playback Switch", "Right DAC" },
|
|
|
|
{ "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
|
|
|
|
|
|
|
|
{ "Left Out 1", NULL, "Left Mixer" },
|
|
|
|
{ "LOUT1", NULL, "Left Out 1" },
|
|
|
|
{ "Right Out 1", NULL, "Right Mixer" },
|
|
|
|
{ "ROUT1", NULL, "Right Out 1" },
|
|
|
|
|
|
|
|
{ "Left Out 2", NULL, "Left Mixer" },
|
|
|
|
{ "LOUT2", NULL, "Left Out 2" },
|
|
|
|
{ "Right Out 2", NULL, "Right Mixer" },
|
|
|
|
{ "ROUT2", NULL, "Right Out 2" },
|
|
|
|
};
|
|
|
|
|
|
|
|
struct _coeff_div {
|
|
|
|
u32 mclk;
|
|
|
|
u32 rate;
|
|
|
|
u16 fs;
|
|
|
|
u8 sr:5;
|
|
|
|
u8 usb:1;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* codec hifi mclk clock divider coefficients */
|
|
|
|
static const struct _coeff_div coeff_div[] = {
|
|
|
|
/* 8k */
|
|
|
|
{12288000, 8000, 1536, 0x6, 0x0},
|
|
|
|
{11289600, 8000, 1408, 0x16, 0x0},
|
|
|
|
{18432000, 8000, 2304, 0x7, 0x0},
|
|
|
|
{16934400, 8000, 2112, 0x17, 0x0},
|
|
|
|
{12000000, 8000, 1500, 0x6, 0x1},
|
|
|
|
|
|
|
|
/* 11.025k */
|
|
|
|
{11289600, 11025, 1024, 0x18, 0x0},
|
|
|
|
{16934400, 11025, 1536, 0x19, 0x0},
|
|
|
|
{12000000, 11025, 1088, 0x19, 0x1},
|
|
|
|
|
|
|
|
/* 16k */
|
|
|
|
{12288000, 16000, 768, 0xa, 0x0},
|
|
|
|
{18432000, 16000, 1152, 0xb, 0x0},
|
|
|
|
{12000000, 16000, 750, 0xa, 0x1},
|
|
|
|
|
|
|
|
/* 22.05k */
|
|
|
|
{11289600, 22050, 512, 0x1a, 0x0},
|
|
|
|
{16934400, 22050, 768, 0x1b, 0x0},
|
|
|
|
{12000000, 22050, 544, 0x1b, 0x1},
|
|
|
|
|
|
|
|
/* 32k */
|
|
|
|
{12288000, 32000, 384, 0xc, 0x0},
|
|
|
|
{18432000, 32000, 576, 0xd, 0x0},
|
|
|
|
{12000000, 32000, 375, 0xa, 0x1},
|
|
|
|
|
|
|
|
/* 44.1k */
|
|
|
|
{11289600, 44100, 256, 0x10, 0x0},
|
|
|
|
{16934400, 44100, 384, 0x11, 0x0},
|
|
|
|
{12000000, 44100, 272, 0x11, 0x1},
|
|
|
|
|
|
|
|
/* 48k */
|
|
|
|
{12288000, 48000, 256, 0x0, 0x0},
|
|
|
|
{18432000, 48000, 384, 0x1, 0x0},
|
|
|
|
{12000000, 48000, 250, 0x0, 0x1},
|
|
|
|
|
|
|
|
/* 88.2k */
|
|
|
|
{11289600, 88200, 128, 0x1e, 0x0},
|
|
|
|
{16934400, 88200, 192, 0x1f, 0x0},
|
|
|
|
{12000000, 88200, 136, 0x1f, 0x1},
|
|
|
|
|
|
|
|
/* 96k */
|
|
|
|
{12288000, 96000, 128, 0xe, 0x0},
|
|
|
|
{18432000, 96000, 192, 0xf, 0x0},
|
|
|
|
{12000000, 96000, 125, 0xe, 0x1},
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline int get_coeff(int mclk, int rate)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
|
|
|
|
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The set of rates we can generate from the above for each SYSCLK */
|
|
|
|
|
2014-02-06 04:54:36 +08:00
|
|
|
static const unsigned int rates_12288[] = {
|
2018-07-28 20:30:17 +08:00
|
|
|
8000, 12000, 16000, 24000, 32000, 48000, 96000,
|
2009-04-08 01:45:21 +08:00
|
|
|
};
|
|
|
|
|
2014-02-06 04:54:36 +08:00
|
|
|
static const struct snd_pcm_hw_constraint_list constraints_12288 = {
|
2009-04-08 01:45:21 +08:00
|
|
|
.count = ARRAY_SIZE(rates_12288),
|
|
|
|
.list = rates_12288,
|
|
|
|
};
|
|
|
|
|
2014-02-06 04:54:36 +08:00
|
|
|
static const unsigned int rates_112896[] = {
|
2009-04-08 01:45:21 +08:00
|
|
|
8000, 11025, 22050, 44100,
|
|
|
|
};
|
|
|
|
|
2014-02-06 04:54:36 +08:00
|
|
|
static const struct snd_pcm_hw_constraint_list constraints_112896 = {
|
2009-04-08 01:45:21 +08:00
|
|
|
.count = ARRAY_SIZE(rates_112896),
|
|
|
|
.list = rates_112896,
|
|
|
|
};
|
|
|
|
|
2014-02-06 04:54:36 +08:00
|
|
|
static const unsigned int rates_12[] = {
|
2018-07-28 20:30:17 +08:00
|
|
|
8000, 11025, 12000, 16000, 22050, 24000, 32000, 41100, 48000,
|
2009-04-08 01:45:21 +08:00
|
|
|
48000, 88235, 96000,
|
|
|
|
};
|
|
|
|
|
2014-02-06 04:54:36 +08:00
|
|
|
static const struct snd_pcm_hw_constraint_list constraints_12 = {
|
2009-04-08 01:45:21 +08:00
|
|
|
.count = ARRAY_SIZE(rates_12),
|
|
|
|
.list = rates_12,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that this should be called from init rather than from hw_params.
|
|
|
|
*/
|
|
|
|
static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
|
|
|
|
int clk_id, unsigned int freq, int dir)
|
|
|
|
{
|
2018-01-29 11:07:26 +08:00
|
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
|
|
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
switch (freq) {
|
|
|
|
case 11289600:
|
|
|
|
case 18432000:
|
|
|
|
case 22579200:
|
|
|
|
case 36864000:
|
|
|
|
wm8988->sysclk_constraints = &constraints_112896;
|
|
|
|
wm8988->sysclk = freq;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case 12288000:
|
|
|
|
case 16934400:
|
|
|
|
case 24576000:
|
|
|
|
case 33868800:
|
|
|
|
wm8988->sysclk_constraints = &constraints_12288;
|
|
|
|
wm8988->sysclk = freq;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case 12000000:
|
|
|
|
case 24000000:
|
|
|
|
wm8988->sysclk_constraints = &constraints_12;
|
|
|
|
wm8988->sysclk = freq;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
|
|
|
|
unsigned int fmt)
|
|
|
|
{
|
2018-01-29 11:07:26 +08:00
|
|
|
struct snd_soc_component *component = codec_dai->component;
|
2009-04-08 01:45:21 +08:00
|
|
|
u16 iface = 0;
|
|
|
|
|
|
|
|
/* set master/slave audio interface */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
iface = 0x0040;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* interface format */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
iface |= 0x0002;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_RIGHT_J:
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
iface |= 0x0001;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
|
iface |= 0x0003;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
|
iface |= 0x0013;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clock inversion */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
iface |= 0x0090;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
iface |= 0x0080;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
iface |= 0x0010;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_IFACE, iface);
|
2009-04-08 01:45:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2018-01-29 11:07:26 +08:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
/* The set of sample rates that can be supported depends on the
|
|
|
|
* MCLK supplied to the CODEC - enforce this.
|
|
|
|
*/
|
|
|
|
if (!wm8988->sysclk) {
|
2018-01-29 11:07:26 +08:00
|
|
|
dev_err(component->dev,
|
2009-04-08 01:45:21 +08:00
|
|
|
"No MCLK configured, call set_sysclk() on init\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_pcm_hw_constraint_list(substream->runtime, 0,
|
|
|
|
SNDRV_PCM_HW_PARAM_RATE,
|
|
|
|
wm8988->sysclk_constraints);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2018-01-29 11:07:26 +08:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
|
2020-06-16 13:21:29 +08:00
|
|
|
u16 iface = snd_soc_component_read(component, WM8988_IFACE) & 0x1f3;
|
|
|
|
u16 srate = snd_soc_component_read(component, WM8988_SRATE) & 0x180;
|
2009-04-08 01:45:21 +08:00
|
|
|
int coeff;
|
|
|
|
|
|
|
|
coeff = get_coeff(wm8988->sysclk, params_rate(params));
|
|
|
|
if (coeff < 0) {
|
|
|
|
coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
|
|
|
|
srate |= 0x40;
|
|
|
|
}
|
|
|
|
if (coeff < 0) {
|
2018-01-29 11:07:26 +08:00
|
|
|
dev_err(component->dev,
|
2009-04-08 01:45:21 +08:00
|
|
|
"Unable to configure sample rate %dHz with %dHz MCLK\n",
|
|
|
|
params_rate(params), wm8988->sysclk);
|
|
|
|
return coeff;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* bit size */
|
2014-07-31 19:54:23 +08:00
|
|
|
switch (params_width(params)) {
|
|
|
|
case 16:
|
2009-04-08 01:45:21 +08:00
|
|
|
break;
|
2014-07-31 19:54:23 +08:00
|
|
|
case 20:
|
2009-04-08 01:45:21 +08:00
|
|
|
iface |= 0x0004;
|
|
|
|
break;
|
2014-07-31 19:54:23 +08:00
|
|
|
case 24:
|
2009-04-08 01:45:21 +08:00
|
|
|
iface |= 0x0008;
|
|
|
|
break;
|
2014-07-31 19:54:23 +08:00
|
|
|
case 32:
|
2009-04-08 01:45:21 +08:00
|
|
|
iface |= 0x000c;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set iface & srate */
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_IFACE, iface);
|
2009-04-08 01:45:21 +08:00
|
|
|
if (coeff >= 0)
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_SRATE, srate |
|
2009-04-08 01:45:21 +08:00
|
|
|
(coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-07-09 09:56:53 +08:00
|
|
|
static int wm8988_mute(struct snd_soc_dai *dai, int mute, int direction)
|
2009-04-08 01:45:21 +08:00
|
|
|
{
|
2018-01-29 11:07:26 +08:00
|
|
|
struct snd_soc_component *component = dai->component;
|
2020-06-16 13:21:29 +08:00
|
|
|
u16 mute_reg = snd_soc_component_read(component, WM8988_ADCDAC) & 0xfff7;
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
if (mute)
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_ADCDAC, mute_reg | 0x8);
|
2009-04-08 01:45:21 +08:00
|
|
|
else
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_ADCDAC, mute_reg);
|
2009-04-08 01:45:21 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
static int wm8988_set_bias_level(struct snd_soc_component *component,
|
2009-04-08 01:45:21 +08:00
|
|
|
enum snd_soc_bias_level level)
|
|
|
|
{
|
2018-01-29 11:07:26 +08:00
|
|
|
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
|
2020-06-16 13:21:29 +08:00
|
|
|
u16 pwr_reg = snd_soc_component_read(component, WM8988_PWR1) & ~0x1c1;
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
switch (level) {
|
|
|
|
case SND_SOC_BIAS_ON:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_BIAS_PREPARE:
|
|
|
|
/* VREF, VMID=2x50k, digital enabled */
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x00c0);
|
2009-04-08 01:45:21 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_BIAS_STANDBY:
|
2018-01-29 11:07:26 +08:00
|
|
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
|
2012-02-13 02:21:57 +08:00
|
|
|
regcache_sync(wm8988->regmap);
|
2011-10-07 21:53:39 +08:00
|
|
|
|
2009-04-08 01:45:21 +08:00
|
|
|
/* VREF, VMID=2x5k */
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x1c1);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
|
|
|
/* Charge caps */
|
|
|
|
msleep(100);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* VREF, VMID=2*500k, digital stopped */
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x0141);
|
2009-04-08 01:45:21 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_BIAS_OFF:
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_write(component, WM8988_PWR1, 0x0000);
|
2009-04-08 01:45:21 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
|
|
|
|
|
|
|
|
#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
|
|
|
|
SNDRV_PCM_FMTBIT_S24_LE)
|
|
|
|
|
2011-11-23 18:40:40 +08:00
|
|
|
static const struct snd_soc_dai_ops wm8988_ops = {
|
2009-04-08 01:45:21 +08:00
|
|
|
.startup = wm8988_pcm_startup,
|
|
|
|
.hw_params = wm8988_pcm_hw_params,
|
|
|
|
.set_fmt = wm8988_set_dai_fmt,
|
|
|
|
.set_sysclk = wm8988_set_dai_sysclk,
|
2020-07-09 09:56:53 +08:00
|
|
|
.mute_stream = wm8988_mute,
|
|
|
|
.no_capture_mute = 1,
|
2009-04-08 01:45:21 +08:00
|
|
|
};
|
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
static struct snd_soc_dai_driver wm8988_dai = {
|
|
|
|
.name = "wm8988-hifi",
|
2009-04-08 01:45:21 +08:00
|
|
|
.playback = {
|
|
|
|
.stream_name = "Playback",
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = WM8988_RATES,
|
|
|
|
.formats = WM8988_FORMATS,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "Capture",
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = WM8988_RATES,
|
|
|
|
.formats = WM8988_FORMATS,
|
|
|
|
},
|
|
|
|
.ops = &wm8988_ops,
|
2021-01-15 12:54:13 +08:00
|
|
|
.symmetric_rate = 1,
|
2009-04-08 01:45:21 +08:00
|
|
|
};
|
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
static int wm8988_probe(struct snd_soc_component *component)
|
2009-04-08 01:45:21 +08:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
ret = wm8988_reset(component);
|
2009-04-08 01:45:21 +08:00
|
|
|
if (ret < 0) {
|
2018-01-29 11:07:26 +08:00
|
|
|
dev_err(component->dev, "Failed to issue reset\n");
|
2010-03-18 04:15:21 +08:00
|
|
|
return ret;
|
2009-04-08 01:45:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* set the update bits (we always update left then right) */
|
2018-01-29 11:07:26 +08:00
|
|
|
snd_soc_component_update_bits(component, WM8988_RADC, 0x0100, 0x0100);
|
|
|
|
snd_soc_component_update_bits(component, WM8988_RDAC, 0x0100, 0x0100);
|
|
|
|
snd_soc_component_update_bits(component, WM8988_ROUT1V, 0x0100, 0x0100);
|
|
|
|
snd_soc_component_update_bits(component, WM8988_ROUT2V, 0x0100, 0x0100);
|
|
|
|
snd_soc_component_update_bits(component, WM8988_RINVOL, 0x0100, 0x0100);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
return 0;
|
2009-04-08 01:45:21 +08:00
|
|
|
}
|
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
static const struct snd_soc_component_driver soc_component_dev_wm8988 = {
|
|
|
|
.probe = wm8988_probe,
|
|
|
|
.set_bias_level = wm8988_set_bias_level,
|
|
|
|
.controls = wm8988_snd_controls,
|
|
|
|
.num_controls = ARRAY_SIZE(wm8988_snd_controls),
|
|
|
|
.dapm_widgets = wm8988_dapm_widgets,
|
|
|
|
.num_dapm_widgets = ARRAY_SIZE(wm8988_dapm_widgets),
|
|
|
|
.dapm_routes = wm8988_dapm_routes,
|
|
|
|
.num_dapm_routes = ARRAY_SIZE(wm8988_dapm_routes),
|
|
|
|
.suspend_bias_off = 1,
|
|
|
|
.idle_bias_on = 1,
|
|
|
|
.use_pmdown_time = 1,
|
|
|
|
.endianness = 1,
|
|
|
|
.non_legacy_dai_naming = 1,
|
2010-03-18 04:15:21 +08:00
|
|
|
};
|
|
|
|
|
2015-01-05 17:18:27 +08:00
|
|
|
static const struct regmap_config wm8988_regmap = {
|
2012-02-13 02:21:57 +08:00
|
|
|
.reg_bits = 7,
|
|
|
|
.val_bits = 9,
|
|
|
|
|
|
|
|
.max_register = WM8988_LPPB,
|
|
|
|
.writeable_reg = wm8988_writeable,
|
|
|
|
|
|
|
|
.cache_type = REGCACHE_RBTREE,
|
|
|
|
.reg_defaults = wm8988_reg_defaults,
|
|
|
|
.num_reg_defaults = ARRAY_SIZE(wm8988_reg_defaults),
|
|
|
|
};
|
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
#if defined(CONFIG_SPI_MASTER)
|
2012-12-07 22:26:37 +08:00
|
|
|
static int wm8988_spi_probe(struct spi_device *spi)
|
2009-04-08 01:45:21 +08:00
|
|
|
{
|
|
|
|
struct wm8988_priv *wm8988;
|
2010-03-18 04:15:21 +08:00
|
|
|
int ret;
|
2009-04-08 01:45:21 +08:00
|
|
|
|
2012-01-22 07:25:16 +08:00
|
|
|
wm8988 = devm_kzalloc(&spi->dev, sizeof(struct wm8988_priv),
|
|
|
|
GFP_KERNEL);
|
2009-04-08 01:45:21 +08:00
|
|
|
if (wm8988 == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2012-11-22 12:08:41 +08:00
|
|
|
wm8988->regmap = devm_regmap_init_spi(spi, &wm8988_regmap);
|
2012-02-13 02:21:57 +08:00
|
|
|
if (IS_ERR(wm8988->regmap)) {
|
|
|
|
ret = PTR_ERR(wm8988->regmap);
|
|
|
|
dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
spi_set_drvdata(spi, wm8988);
|
2009-04-08 01:45:21 +08:00
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
ret = devm_snd_soc_register_component(&spi->dev,
|
|
|
|
&soc_component_dev_wm8988, &wm8988_dai, 1);
|
2010-03-18 04:15:21 +08:00
|
|
|
return ret;
|
2009-04-08 01:45:21 +08:00
|
|
|
}
|
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
static struct spi_driver wm8988_spi_driver = {
|
2009-04-08 01:45:21 +08:00
|
|
|
.driver = {
|
2011-12-03 06:08:49 +08:00
|
|
|
.name = "wm8988",
|
2009-04-08 01:45:21 +08:00
|
|
|
},
|
2010-03-18 04:15:21 +08:00
|
|
|
.probe = wm8988_spi_probe,
|
2009-04-08 01:45:21 +08:00
|
|
|
};
|
2010-03-18 04:15:21 +08:00
|
|
|
#endif /* CONFIG_SPI_MASTER */
|
2009-04-08 01:45:21 +08:00
|
|
|
|
2013-11-21 22:38:53 +08:00
|
|
|
#if IS_ENABLED(CONFIG_I2C)
|
2012-12-07 22:26:37 +08:00
|
|
|
static int wm8988_i2c_probe(struct i2c_client *i2c,
|
|
|
|
const struct i2c_device_id *id)
|
2009-04-08 01:45:21 +08:00
|
|
|
{
|
|
|
|
struct wm8988_priv *wm8988;
|
2010-03-18 04:15:21 +08:00
|
|
|
int ret;
|
2009-04-08 01:45:21 +08:00
|
|
|
|
2012-01-22 07:25:16 +08:00
|
|
|
wm8988 = devm_kzalloc(&i2c->dev, sizeof(struct wm8988_priv),
|
|
|
|
GFP_KERNEL);
|
2009-04-08 01:45:21 +08:00
|
|
|
if (wm8988 == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
i2c_set_clientdata(i2c, wm8988);
|
2012-02-13 02:21:57 +08:00
|
|
|
|
2012-11-22 12:08:41 +08:00
|
|
|
wm8988->regmap = devm_regmap_init_i2c(i2c, &wm8988_regmap);
|
2012-02-13 02:21:57 +08:00
|
|
|
if (IS_ERR(wm8988->regmap)) {
|
|
|
|
ret = PTR_ERR(wm8988->regmap);
|
|
|
|
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2009-04-08 01:45:21 +08:00
|
|
|
|
2018-01-29 11:07:26 +08:00
|
|
|
ret = devm_snd_soc_register_component(&i2c->dev,
|
|
|
|
&soc_component_dev_wm8988, &wm8988_dai, 1);
|
2010-03-18 04:15:21 +08:00
|
|
|
return ret;
|
2009-04-08 01:45:21 +08:00
|
|
|
}
|
|
|
|
|
2010-03-18 04:15:21 +08:00
|
|
|
static const struct i2c_device_id wm8988_i2c_id[] = {
|
|
|
|
{ "wm8988", 0 },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
|
|
|
|
|
|
|
|
static struct i2c_driver wm8988_i2c_driver = {
|
2009-04-08 01:45:21 +08:00
|
|
|
.driver = {
|
2012-02-13 02:22:15 +08:00
|
|
|
.name = "wm8988",
|
2009-04-08 01:45:21 +08:00
|
|
|
},
|
2010-03-18 04:15:21 +08:00
|
|
|
.probe = wm8988_i2c_probe,
|
|
|
|
.id_table = wm8988_i2c_id,
|
2009-04-08 01:45:21 +08:00
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int __init wm8988_modinit(void)
|
|
|
|
{
|
2010-03-18 04:15:21 +08:00
|
|
|
int ret = 0;
|
2013-11-21 22:38:53 +08:00
|
|
|
#if IS_ENABLED(CONFIG_I2C)
|
2009-04-08 01:45:21 +08:00
|
|
|
ret = i2c_add_driver(&wm8988_i2c_driver);
|
2010-03-18 04:15:21 +08:00
|
|
|
if (ret != 0) {
|
|
|
|
printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
|
|
|
|
ret);
|
|
|
|
}
|
2009-04-08 01:45:21 +08:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_SPI_MASTER)
|
|
|
|
ret = spi_register_driver(&wm8988_spi_driver);
|
2010-03-18 04:15:21 +08:00
|
|
|
if (ret != 0) {
|
|
|
|
printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
|
|
|
|
ret);
|
|
|
|
}
|
2009-04-08 01:45:21 +08:00
|
|
|
#endif
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
module_init(wm8988_modinit);
|
|
|
|
|
|
|
|
static void __exit wm8988_exit(void)
|
|
|
|
{
|
2013-11-21 22:38:53 +08:00
|
|
|
#if IS_ENABLED(CONFIG_I2C)
|
2009-04-08 01:45:21 +08:00
|
|
|
i2c_del_driver(&wm8988_i2c_driver);
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_SPI_MASTER)
|
|
|
|
spi_unregister_driver(&wm8988_spi_driver);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
module_exit(wm8988_exit);
|
|
|
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("ASoC WM8988 driver");
|
|
|
|
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|