UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenCloudOS-Kernel/drivers/crypto/Makefile

36 lines
1.6 KiB
Makefile
Raw Normal View History

crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
[PATCH] crypto: Add support for the Geode LX AES hardware Add a driver to support the AES hardware on the Geode LX processor. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2006-10-04 16:48:57 +08:00
obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
[CRYPTO] hifn_795x: HIFN 795x driver This is a driver for HIFN 795x crypto accelerator chips. It passed all tests for AES, DES and DES3_EDE except weak test for DES, since hardware can not determine weak keys. Signed-off-by: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-26 21:31:14 +08:00
obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
crypto: img-hash - Add Imagination Technologies hw hash accelerator This adds support for the Imagination Technologies hash accelerator which provides hardware acceleration for SHA1 SHA224 SHA256 and MD5 hashes. Signed-off-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-03-13 07:17:26 +08:00
obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
crypto: ixp4xx - Hardware crypto support for IXP4xx CPUs Add support for the hardware crypto engine provided by the NPE C of the Intel IXP4xx networking processor series. Supported ciphers: des, des3, aes and a combination of them with md5 and sha1 hmac Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2008-06-25 14:38:47 +08:00
obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
crypto: marvell/cesa - add a new driver for Marvell's CESA The existing mv_cesa driver supports some features of the CESA IP but is quite limited, and reworking it to support new features (like involving the TDMA engine to offload the CPU) is almost impossible. This driver has been rewritten from scratch to take those new features into account. This commit introduce the base infrastructure allowing us to add support for DMA optimization. It also includes support for one hash (SHA1) and one cipher (AES) algorithm, and enable those features on the Armada 370 SoC. Other algorithms and platforms will be added later on. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-18 21:46:20 +08:00
obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o
n2_crypto-y := n2_core.o n2_asm.o
obj-$(CONFIG_CRYPTO_DEV_NX) += nx/
crypto: omap-aes - OMAP2/3 AES hw accelerator driver Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2010-09-03 19:16:02 +08:00
obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
crypto: omap-des - Add config and build options Add config and build options for the omap-des driver. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-02-15 00:49:47 +08:00
obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o
crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
crypto: picoxcell - add support for the picoxcell crypto engines Picochip picoXcell devices have two crypto engines, one targeted at IPSEC offload and the other at WCDMA layer 2 ciphering. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2011-02-21 13:43:21 +08:00
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
crypto: s5p-sss - add S5PV210 advanced crypto engine support This change adds support for AES encrypting and decrypting using advanced crypto engine found on Samsung S5PV210 and S5PC110 SoCs. Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2011-04-08 20:40:51 +08:00
obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
crypto: mxc-scc - add basic driver for the MXC SCC According to the Freescale GPL driver code, there are two different Security Controller (SCC) versions: SCC and SCC2. The SCC is found on older i.MX SoCs, e.g. the i.MX25. This is the version implemented and tested here. As there is no publicly available documentation for this IP core, all information about this unit is gathered from the GPL'ed driver from Freescale. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-04-12 17:04:26 +08:00
obj-$(CONFIG_CRYPTO_DEV_MXC_SCC) += mxc-scc.o
crypto: drivers - Sort drivers/crypto/Makefile The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-12-11 03:26:23 +08:00
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
crypto: bfin_crc - CRC hardware driver for BF60x family processors. The CRC peripheral is a hardware block used to compute the CRC of the block of data. This is based on a CRC32 engine which computes the CRC value of 32b data words presented to it. For data words of < 32b in size, this driver pack 0 automatically into 32b data units. This driver implements the async hash crypto framework API. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-06-04 12:24:47 +08:00
obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
crypto: qat - Update to makefiles Update to makefiles etc. Don't update the firmware/Makefile yet since there is no FW binary in the crypto repo yet. This will be added later. v3 - removed change to ./firmware/Makefile Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-06-06 04:44:39 +08:00
obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
crypto: qce - Build Qualcomm crypto driver Modify crypto Kconfig and Makefile in order to build the qce driver and adds qce Makefile as well. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-06-26 00:28:58 +08:00
obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
crypto: vmx - Enabling VMX module for PPC64 This patch enables VMX module in PPC64. Signed-off-by: Leonidas S. Barbosa <leosilva@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-02-07 00:59:48 +08:00
obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
crypto: sunxi-ss - Add Allwinner Security System crypto accelerator Add support for the Security System included in Allwinner SoC A20. The Security System is a hardware cryptographic accelerator that support: - MD5 and SHA1 hash algorithms - AES block cipher in CBC/ECB mode with 128/196/256bits keys. - DES and 3DES block cipher in CBC/ECB mode Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-07-17 22:39:41 +08:00
obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
crypto: rockchip - add crypto driver for rk3288 Crypto driver support: ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede) You can alloc tags above in your case. And other algorithms and platforms will be added later on. Signed-off-by: Zain Wang <zain.wang@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-11-25 13:43:32 +08:00
obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
crypto: Added Chelsio Menu to the Kconfig file Adds the config entry for the Chelsio Crypto Driver, Makefile changes for the same. Signed-off-by: Atul Gupta <atul.gupta@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 15:03:06 +08:00
obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
crypto: add virtio-crypto driver This patch introduces virtio-crypto driver for Linux Kernel. The virtio crypto device is a virtual cryptography device as well as a kind of virtual hardware accelerator for virtual machines. The encryption anddecryption requests are placed in the data queue and are ultimately handled by thebackend crypto accelerators. The second queue is the control queue used to create or destroy sessions for symmetric algorithms and will control some advanced features in the future. The virtio crypto device provides the following cryptoservices: CIPHER, MAC, HASH, and AEAD. For more information about virtio-crypto device, please see: http://qemu-project.org/Features/VirtioCrypto CC: Michael S. Tsirkin <mst@redhat.com> CC: Cornelia Huck <cornelia.huck@de.ibm.com> CC: Stefan Hajnoczi <stefanha@redhat.com> CC: Herbert Xu <herbert@gondor.apana.org.au> CC: Halil Pasic <pasic@linux.vnet.ibm.com> CC: David S. Miller <davem@davemloft.net> CC: Zeng Xin <xin.zeng@intel.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-12-15 10:03:16 +08:00
obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/