2017-12-14 13:49:34 +08:00
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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// Copyright(c) 2015-17 Intel Corporation.
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#include <linux/acpi.h>
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2020-01-15 08:08:43 +08:00
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#include <linux/delay.h>
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2017-12-14 13:49:34 +08:00
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#include <linux/mod_devicetable.h>
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2017-12-14 13:49:37 +08:00
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#include <linux/pm_runtime.h>
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#include <linux/soundwire/sdw_registers.h>
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2017-12-14 13:49:34 +08:00
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#include <linux/soundwire/sdw.h>
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#include "bus.h"
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2020-05-19 04:35:51 +08:00
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#include "sysfs_local.h"
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2017-12-14 13:49:34 +08:00
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2020-05-19 01:43:20 +08:00
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static DEFINE_IDA(sdw_ida);
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static int sdw_get_id(struct sdw_bus *bus)
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{
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int rc = ida_alloc(&sdw_ida, GFP_KERNEL);
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if (rc < 0)
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return rc;
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bus->id = rc;
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return 0;
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}
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2017-12-14 13:49:34 +08:00
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/**
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2020-05-19 01:43:18 +08:00
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* sdw_bus_master_add() - add a bus Master instance
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2017-12-14 13:49:34 +08:00
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* @bus: bus instance
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2020-05-19 01:43:18 +08:00
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* @parent: parent device
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* @fwnode: firmware node handle
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2017-12-14 13:49:34 +08:00
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*
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* Initializes the bus instance, read properties and create child
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* devices.
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*/
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2020-05-19 01:43:18 +08:00
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int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
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struct fwnode_handle *fwnode)
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2017-12-14 13:49:34 +08:00
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{
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2018-04-26 21:08:33 +08:00
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struct sdw_master_prop *prop = NULL;
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2017-12-14 13:49:34 +08:00
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int ret;
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2020-05-19 01:43:21 +08:00
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if (!parent) {
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pr_err("SoundWire parent device is not set\n");
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2017-12-14 13:49:34 +08:00
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return -ENODEV;
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}
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2020-05-19 01:43:20 +08:00
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ret = sdw_get_id(bus);
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if (ret) {
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2020-05-19 01:43:21 +08:00
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dev_err(parent, "Failed to get bus id\n");
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return ret;
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}
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ret = sdw_master_device_add(bus, parent, fwnode);
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if (ret) {
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dev_err(parent, "Failed to add master device at link %d\n",
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bus->link_id);
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2020-05-19 01:43:20 +08:00
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return ret;
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}
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2017-12-14 13:49:37 +08:00
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if (!bus->ops) {
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2019-05-01 23:57:45 +08:00
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dev_err(bus->dev, "SoundWire Bus ops are not set\n");
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2017-12-14 13:49:37 +08:00
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return -EINVAL;
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}
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2020-09-08 21:15:20 +08:00
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if (!bus->compute_params) {
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dev_err(bus->dev,
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"Bandwidth allocation not configured, compute_params no set\n");
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return -EINVAL;
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}
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2017-12-14 13:49:37 +08:00
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mutex_init(&bus->msg_lock);
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2017-12-14 13:49:34 +08:00
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mutex_init(&bus->bus_lock);
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INIT_LIST_HEAD(&bus->slaves);
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2018-04-26 21:08:08 +08:00
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INIT_LIST_HEAD(&bus->m_rt_list);
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2017-12-14 13:49:34 +08:00
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2018-07-27 17:14:16 +08:00
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/*
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* Initialize multi_link flag
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* TODO: populate this flag by reading property from FW node
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*/
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bus->multi_link = false;
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2017-12-14 13:49:35 +08:00
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if (bus->ops->read_prop) {
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ret = bus->ops->read_prop(bus);
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if (ret < 0) {
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2019-05-02 18:59:24 +08:00
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dev_err(bus->dev,
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"Bus read properties failed:%d\n", ret);
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2017-12-14 13:49:35 +08:00
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return ret;
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}
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}
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2019-08-22 02:58:18 +08:00
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sdw_bus_debugfs_init(bus);
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2017-12-14 13:49:34 +08:00
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/*
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2019-05-01 23:57:28 +08:00
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* Device numbers in SoundWire are 0 through 15. Enumeration device
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2017-12-14 13:49:34 +08:00
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* number (0), Broadcast device number (15), Group numbers (12 and
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* 13) and Master device number (14) are not used for assignment so
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* mask these and other higher bits.
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*/
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/* Set higher order bits */
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*bus->assigned = ~GENMASK(SDW_BROADCAST_DEV_NUM, SDW_ENUM_DEV_NUM);
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/* Set enumuration device number and broadcast device number */
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set_bit(SDW_ENUM_DEV_NUM, bus->assigned);
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set_bit(SDW_BROADCAST_DEV_NUM, bus->assigned);
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/* Set group device numbers and master device number */
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set_bit(SDW_GROUP12_DEV_NUM, bus->assigned);
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set_bit(SDW_GROUP13_DEV_NUM, bus->assigned);
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set_bit(SDW_MASTER_DEV_NUM, bus->assigned);
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/*
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* SDW is an enumerable bus, but devices can be powered off. So,
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* they won't be able to report as present.
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*
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* Create Slave devices based on Slaves described in
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* the respective firmware (ACPI/DT)
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*/
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if (IS_ENABLED(CONFIG_ACPI) && ACPI_HANDLE(bus->dev))
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ret = sdw_acpi_find_slaves(bus);
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2019-08-30 00:35:12 +08:00
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else if (IS_ENABLED(CONFIG_OF) && bus->dev->of_node)
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ret = sdw_of_find_slaves(bus);
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2017-12-14 13:49:34 +08:00
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else
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ret = -ENOTSUPP; /* No ACPI/DT so error out */
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if (ret) {
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dev_err(bus->dev, "Finding slaves failed:%d\n", ret);
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return ret;
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}
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2018-04-26 21:08:28 +08:00
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/*
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2018-04-26 21:08:33 +08:00
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* Initialize clock values based on Master properties. The max
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2019-05-23 03:47:22 +08:00
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* frequency is read from max_clk_freq property. Current assumption
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2018-04-26 21:08:33 +08:00
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* is that the bus will start at highest clock frequency when
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* powered on.
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*
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2018-04-26 21:08:28 +08:00
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* Default active bank will be 0 as out of reset the Slaves have
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* to start with bank 0 (Table 40 of Spec)
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*/
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2018-04-26 21:08:33 +08:00
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prop = &bus->prop;
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2019-05-23 03:47:22 +08:00
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bus->params.max_dr_freq = prop->max_clk_freq * SDW_DOUBLE_RATE_FACTOR;
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2018-04-26 21:08:33 +08:00
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bus->params.curr_dr_freq = bus->params.max_dr_freq;
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2018-04-26 21:08:28 +08:00
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bus->params.curr_bank = SDW_BANK0;
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bus->params.next_bank = SDW_BANK1;
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2017-12-14 13:49:34 +08:00
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return 0;
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}
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2020-05-19 01:43:18 +08:00
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EXPORT_SYMBOL(sdw_bus_master_add);
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2017-12-14 13:49:34 +08:00
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static int sdw_delete_slave(struct device *dev, void *data)
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{
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struct sdw_slave *slave = dev_to_sdw_dev(dev);
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struct sdw_bus *bus = slave->bus;
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2020-01-15 08:08:41 +08:00
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pm_runtime_disable(dev);
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2019-08-22 02:58:18 +08:00
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sdw_slave_debugfs_exit(slave);
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2017-12-14 13:49:34 +08:00
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mutex_lock(&bus->bus_lock);
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if (slave->dev_num) /* clear dev_num if assigned */
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clear_bit(slave->dev_num, bus->assigned);
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list_del_init(&slave->node);
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mutex_unlock(&bus->bus_lock);
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device_unregister(dev);
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return 0;
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}
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/**
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2020-05-19 01:43:18 +08:00
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* sdw_bus_master_delete() - delete the bus master instance
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2017-12-14 13:49:34 +08:00
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* @bus: bus to be deleted
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*
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* Remove the instance, delete the child devices.
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*/
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2020-05-19 01:43:18 +08:00
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void sdw_bus_master_delete(struct sdw_bus *bus)
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2017-12-14 13:49:34 +08:00
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{
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device_for_each_child(bus->dev, NULL, sdw_delete_slave);
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2020-05-19 01:43:21 +08:00
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sdw_master_device_del(bus);
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2019-08-22 02:58:18 +08:00
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sdw_bus_debugfs_exit(bus);
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2020-05-19 01:43:20 +08:00
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ida_free(&sdw_ida, bus->id);
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2017-12-14 13:49:34 +08:00
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}
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2020-05-19 01:43:18 +08:00
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EXPORT_SYMBOL(sdw_bus_master_delete);
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2017-12-14 13:49:34 +08:00
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2017-12-14 13:49:37 +08:00
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/*
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* SDW IO Calls
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*/
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static inline int find_response_code(enum sdw_command_response resp)
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{
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switch (resp) {
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case SDW_CMD_OK:
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return 0;
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case SDW_CMD_IGNORED:
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return -ENODATA;
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case SDW_CMD_TIMEOUT:
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return -ETIMEDOUT;
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default:
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return -EIO;
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}
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}
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static inline int do_transfer(struct sdw_bus *bus, struct sdw_msg *msg)
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{
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int retry = bus->prop.err_threshold;
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enum sdw_command_response resp;
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int ret = 0, i;
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for (i = 0; i <= retry; i++) {
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resp = bus->ops->xfer_msg(bus, msg);
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ret = find_response_code(resp);
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/* if cmd is ok or ignored return */
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if (ret == 0 || ret == -ENODATA)
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return ret;
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}
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return ret;
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}
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static inline int do_transfer_defer(struct sdw_bus *bus,
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2019-05-01 23:57:27 +08:00
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struct sdw_msg *msg,
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struct sdw_defer *defer)
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2017-12-14 13:49:37 +08:00
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{
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int retry = bus->prop.err_threshold;
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enum sdw_command_response resp;
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int ret = 0, i;
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defer->msg = msg;
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defer->length = msg->len;
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2018-07-27 17:14:12 +08:00
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init_completion(&defer->complete);
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2017-12-14 13:49:37 +08:00
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for (i = 0; i <= retry; i++) {
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resp = bus->ops->xfer_msg_defer(bus, msg, defer);
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ret = find_response_code(resp);
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/* if cmd is ok or ignored return */
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if (ret == 0 || ret == -ENODATA)
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return ret;
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}
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return ret;
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}
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static int sdw_reset_page(struct sdw_bus *bus, u16 dev_num)
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{
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int retry = bus->prop.err_threshold;
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enum sdw_command_response resp;
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int ret = 0, i;
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for (i = 0; i <= retry; i++) {
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resp = bus->ops->reset_page_addr(bus, dev_num);
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ret = find_response_code(resp);
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/* if cmd is ok or ignored return */
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if (ret == 0 || ret == -ENODATA)
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return ret;
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}
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return ret;
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}
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2020-09-08 21:45:20 +08:00
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static int sdw_transfer_unlocked(struct sdw_bus *bus, struct sdw_msg *msg)
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{
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int ret;
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ret = do_transfer(bus, msg);
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if (ret != 0 && ret != -ENODATA)
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2021-01-15 13:37:36 +08:00
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dev_err(bus->dev, "trf on Slave %d failed:%d %s addr %x count %d\n",
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msg->dev_num, ret,
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(msg->flags & SDW_MSG_FLAG_WRITE) ? "write" : "read",
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msg->addr, msg->len);
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2020-09-08 21:45:20 +08:00
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if (msg->page)
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sdw_reset_page(bus, msg->dev_num);
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return ret;
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}
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2017-12-14 13:49:37 +08:00
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/**
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* sdw_transfer() - Synchronous transfer message to a SDW Slave device
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* @bus: SDW bus
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* @msg: SDW message to be xfered
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*/
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int sdw_transfer(struct sdw_bus *bus, struct sdw_msg *msg)
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{
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int ret;
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mutex_lock(&bus->msg_lock);
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2020-09-08 21:45:20 +08:00
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ret = sdw_transfer_unlocked(bus, msg);
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2017-12-14 13:49:37 +08:00
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mutex_unlock(&bus->msg_lock);
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return ret;
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}
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/**
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* sdw_transfer_defer() - Asynchronously transfer message to a SDW Slave device
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* @bus: SDW bus
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* @msg: SDW message to be xfered
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* @defer: Defer block for signal completion
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*
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* Caller needs to hold the msg_lock lock while calling this
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*/
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int sdw_transfer_defer(struct sdw_bus *bus, struct sdw_msg *msg,
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2019-05-01 23:57:27 +08:00
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struct sdw_defer *defer)
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2017-12-14 13:49:37 +08:00
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{
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int ret;
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if (!bus->ops->xfer_msg_defer)
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return -ENOTSUPP;
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ret = do_transfer_defer(bus, msg, defer);
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if (ret != 0 && ret != -ENODATA)
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dev_err(bus->dev, "Defer trf on Slave %d failed:%d\n",
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2019-05-01 23:57:27 +08:00
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msg->dev_num, ret);
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2017-12-14 13:49:37 +08:00
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if (msg->page)
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sdw_reset_page(bus, msg->dev_num);
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return ret;
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}
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int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave,
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2019-05-01 23:57:27 +08:00
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u32 addr, size_t count, u16 dev_num, u8 flags, u8 *buf)
|
2017-12-14 13:49:37 +08:00
|
|
|
{
|
|
|
|
memset(msg, 0, sizeof(*msg));
|
|
|
|
msg->addr = addr; /* addr is 16 bit and truncated here */
|
|
|
|
msg->len = count;
|
|
|
|
msg->dev_num = dev_num;
|
|
|
|
msg->flags = flags;
|
|
|
|
msg->buf = buf;
|
|
|
|
|
2020-05-08 08:30:45 +08:00
|
|
|
if (addr < SDW_REG_NO_PAGE) /* no paging area */
|
2017-12-14 13:49:37 +08:00
|
|
|
return 0;
|
2020-05-08 08:30:45 +08:00
|
|
|
|
|
|
|
if (addr >= SDW_REG_MAX) { /* illegal addr */
|
2017-12-14 13:49:37 +08:00
|
|
|
pr_err("SDW: Invalid address %x passed\n", addr);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr < SDW_REG_OPTIONAL_PAGE) { /* 32k but no page */
|
|
|
|
if (slave && !slave->prop.paging_support)
|
|
|
|
return 0;
|
2019-05-01 23:57:28 +08:00
|
|
|
/* no need for else as that will fall-through to paging */
|
2017-12-14 13:49:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* paging mandatory */
|
|
|
|
if (dev_num == SDW_ENUM_DEV_NUM || dev_num == SDW_BROADCAST_DEV_NUM) {
|
|
|
|
pr_err("SDW: Invalid device for paging :%d\n", dev_num);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!slave) {
|
|
|
|
pr_err("SDW: No slave for paging addr\n");
|
|
|
|
return -EINVAL;
|
2020-05-08 08:30:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!slave->prop.paging_support) {
|
2017-12-14 13:49:37 +08:00
|
|
|
dev_err(&slave->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"address %x needs paging but no support\n", addr);
|
2017-12-14 13:49:37 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-09-03 19:44:57 +08:00
|
|
|
msg->addr_page1 = FIELD_GET(SDW_SCP_ADDRPAGE1_MASK, addr);
|
|
|
|
msg->addr_page2 = FIELD_GET(SDW_SCP_ADDRPAGE2_MASK, addr);
|
2017-12-14 13:49:37 +08:00
|
|
|
msg->addr |= BIT(15);
|
|
|
|
msg->page = true;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-15 08:08:38 +08:00
|
|
|
/*
|
|
|
|
* Read/Write IO functions.
|
|
|
|
* no_pm versions can only be called by the bus, e.g. while enumerating or
|
|
|
|
* handling suspend-resume sequences.
|
|
|
|
* all clients need to use the pm versions
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int
|
|
|
|
sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
|
|
|
|
{
|
|
|
|
struct sdw_msg msg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_fill_msg(&msg, slave, addr, count,
|
|
|
|
slave->dev_num, SDW_MSG_FLAG_READ, val);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return sdw_transfer(slave->bus, &msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
|
|
|
|
{
|
|
|
|
struct sdw_msg msg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_fill_msg(&msg, slave, addr, count,
|
|
|
|
slave->dev_num, SDW_MSG_FLAG_WRITE, val);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return sdw_transfer(slave->bus, &msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value)
|
|
|
|
{
|
|
|
|
return sdw_nwrite_no_pm(slave, addr, 1, &value);
|
|
|
|
}
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
static int
|
|
|
|
sdw_bread_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr)
|
|
|
|
{
|
|
|
|
struct sdw_msg msg;
|
|
|
|
u8 buf;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
|
|
|
|
SDW_MSG_FLAG_READ, &buf);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sdw_transfer(bus, &msg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2020-05-08 08:30:45 +08:00
|
|
|
|
|
|
|
return buf;
|
2020-01-15 08:08:43 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
sdw_bwrite_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr, u8 value)
|
|
|
|
{
|
|
|
|
struct sdw_msg msg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
|
|
|
|
SDW_MSG_FLAG_WRITE, &value);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return sdw_transfer(bus, &msg);
|
|
|
|
}
|
|
|
|
|
2020-09-08 21:45:20 +08:00
|
|
|
int sdw_bread_no_pm_unlocked(struct sdw_bus *bus, u16 dev_num, u32 addr)
|
|
|
|
{
|
|
|
|
struct sdw_msg msg;
|
|
|
|
u8 buf;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
|
|
|
|
SDW_MSG_FLAG_READ, &buf);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sdw_transfer_unlocked(bus, &msg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return buf;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_bread_no_pm_unlocked);
|
|
|
|
|
|
|
|
int sdw_bwrite_no_pm_unlocked(struct sdw_bus *bus, u16 dev_num, u32 addr, u8 value)
|
|
|
|
{
|
|
|
|
struct sdw_msg msg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
|
|
|
|
SDW_MSG_FLAG_WRITE, &value);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return sdw_transfer_unlocked(bus, &msg);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_bwrite_no_pm_unlocked);
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
static int
|
|
|
|
sdw_read_no_pm(struct sdw_slave *slave, u32 addr)
|
|
|
|
{
|
|
|
|
u8 buf;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_nread_no_pm(slave, addr, 1, &buf);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
else
|
|
|
|
return buf;
|
|
|
|
}
|
|
|
|
|
2017-12-14 13:49:37 +08:00
|
|
|
/**
|
|
|
|
* sdw_nread() - Read "n" contiguous SDW Slave registers
|
|
|
|
* @slave: SDW Slave
|
|
|
|
* @addr: Register address
|
|
|
|
* @count: length
|
|
|
|
* @val: Buffer for values to be read
|
|
|
|
*/
|
|
|
|
int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pm_runtime_get_sync(slave->bus->dev);
|
2020-01-15 08:08:38 +08:00
|
|
|
if (ret < 0 && ret != -EACCES) {
|
|
|
|
pm_runtime_put_noidle(slave->bus->dev);
|
2017-12-14 13:49:37 +08:00
|
|
|
return ret;
|
2020-01-15 08:08:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_nread_no_pm(slave, addr, count, val);
|
2017-12-14 13:49:37 +08:00
|
|
|
|
2020-01-15 08:08:38 +08:00
|
|
|
pm_runtime_mark_last_busy(slave->bus->dev);
|
2017-12-14 13:49:37 +08:00
|
|
|
pm_runtime_put(slave->bus->dev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_nread);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_nwrite() - Write "n" contiguous SDW Slave registers
|
|
|
|
* @slave: SDW Slave
|
|
|
|
* @addr: Register address
|
|
|
|
* @count: length
|
|
|
|
* @val: Buffer for values to be read
|
|
|
|
*/
|
|
|
|
int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pm_runtime_get_sync(slave->bus->dev);
|
2020-01-15 08:08:38 +08:00
|
|
|
if (ret < 0 && ret != -EACCES) {
|
|
|
|
pm_runtime_put_noidle(slave->bus->dev);
|
2017-12-14 13:49:37 +08:00
|
|
|
return ret;
|
2020-01-15 08:08:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_nwrite_no_pm(slave, addr, count, val);
|
2017-12-14 13:49:37 +08:00
|
|
|
|
2020-01-15 08:08:38 +08:00
|
|
|
pm_runtime_mark_last_busy(slave->bus->dev);
|
2017-12-14 13:49:37 +08:00
|
|
|
pm_runtime_put(slave->bus->dev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_nwrite);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_read() - Read a SDW Slave register
|
|
|
|
* @slave: SDW Slave
|
|
|
|
* @addr: Register address
|
|
|
|
*/
|
|
|
|
int sdw_read(struct sdw_slave *slave, u32 addr)
|
|
|
|
{
|
|
|
|
u8 buf;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdw_nread(slave, addr, 1, &buf);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2020-05-08 08:30:45 +08:00
|
|
|
|
|
|
|
return buf;
|
2017-12-14 13:49:37 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_read);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_write() - Write a SDW Slave register
|
|
|
|
* @slave: SDW Slave
|
|
|
|
* @addr: Register address
|
|
|
|
* @value: Register value
|
|
|
|
*/
|
|
|
|
int sdw_write(struct sdw_slave *slave, u32 addr, u8 value)
|
|
|
|
{
|
|
|
|
return sdw_nwrite(slave, addr, 1, &value);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_write);
|
|
|
|
|
2017-12-14 13:49:39 +08:00
|
|
|
/*
|
|
|
|
* SDW alert handling
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* called with bus_lock held */
|
|
|
|
static struct sdw_slave *sdw_get_slave(struct sdw_bus *bus, int i)
|
|
|
|
{
|
|
|
|
struct sdw_slave *slave = NULL;
|
|
|
|
|
|
|
|
list_for_each_entry(slave, &bus->slaves, node) {
|
|
|
|
if (slave->dev_num == i)
|
|
|
|
return slave;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id)
|
|
|
|
{
|
2019-10-23 07:48:08 +08:00
|
|
|
if (slave->id.mfg_id != id.mfg_id ||
|
2019-05-01 23:57:29 +08:00
|
|
|
slave->id.part_id != id.part_id ||
|
2019-10-23 07:48:08 +08:00
|
|
|
slave->id.class_id != id.class_id ||
|
|
|
|
(slave->id.unique_id != SDW_IGNORED_UNIQUE_ID &&
|
|
|
|
slave->id.unique_id != id.unique_id))
|
2017-12-14 13:49:39 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called with bus_lock held */
|
|
|
|
static int sdw_get_device_num(struct sdw_slave *slave)
|
|
|
|
{
|
|
|
|
int bit;
|
|
|
|
|
|
|
|
bit = find_first_zero_bit(slave->bus->assigned, SDW_MAX_DEVICES);
|
|
|
|
if (bit == SDW_MAX_DEVICES) {
|
|
|
|
bit = -ENODEV;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do not update dev_num in Slave data structure here,
|
|
|
|
* Update once program dev_num is successful
|
|
|
|
*/
|
|
|
|
set_bit(bit, slave->bus->assigned);
|
|
|
|
|
|
|
|
err:
|
|
|
|
return bit;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_assign_device_num(struct sdw_slave *slave)
|
|
|
|
{
|
|
|
|
int ret, dev_num;
|
2020-01-14 06:56:37 +08:00
|
|
|
bool new_device = false;
|
2017-12-14 13:49:39 +08:00
|
|
|
|
|
|
|
/* check first if device number is assigned, if so reuse that */
|
|
|
|
if (!slave->dev_num) {
|
2020-01-14 06:56:37 +08:00
|
|
|
if (!slave->dev_num_sticky) {
|
|
|
|
mutex_lock(&slave->bus->bus_lock);
|
|
|
|
dev_num = sdw_get_device_num(slave);
|
|
|
|
mutex_unlock(&slave->bus->bus_lock);
|
|
|
|
if (dev_num < 0) {
|
|
|
|
dev_err(slave->bus->dev, "Get dev_num failed: %d\n",
|
|
|
|
dev_num);
|
|
|
|
return dev_num;
|
|
|
|
}
|
|
|
|
slave->dev_num = dev_num;
|
|
|
|
slave->dev_num_sticky = dev_num;
|
|
|
|
new_device = true;
|
|
|
|
} else {
|
|
|
|
slave->dev_num = slave->dev_num_sticky;
|
2017-12-14 13:49:39 +08:00
|
|
|
}
|
2020-01-14 06:56:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!new_device)
|
2020-04-20 02:51:17 +08:00
|
|
|
dev_dbg(slave->bus->dev,
|
|
|
|
"Slave already registered, reusing dev_num:%d\n",
|
|
|
|
slave->dev_num);
|
2017-12-14 13:49:39 +08:00
|
|
|
|
2020-01-14 06:56:37 +08:00
|
|
|
/* Clear the slave->dev_num to transfer message on device 0 */
|
|
|
|
dev_num = slave->dev_num;
|
|
|
|
slave->dev_num = 0;
|
2017-12-14 13:49:39 +08:00
|
|
|
|
2020-01-15 08:08:39 +08:00
|
|
|
ret = sdw_write_no_pm(slave, SDW_SCP_DEVNUMBER, dev_num);
|
2017-12-14 13:49:39 +08:00
|
|
|
if (ret < 0) {
|
2019-08-06 08:55:09 +08:00
|
|
|
dev_err(&slave->dev, "Program device_num %d failed: %d\n",
|
|
|
|
dev_num, ret);
|
2017-12-14 13:49:39 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* After xfer of msg, restore dev_num */
|
2020-01-14 06:56:37 +08:00
|
|
|
slave->dev_num = slave->dev_num_sticky;
|
2017-12-14 13:49:39 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-12-14 13:49:34 +08:00
|
|
|
void sdw_extract_slave_id(struct sdw_bus *bus,
|
2019-05-01 23:57:27 +08:00
|
|
|
u64 addr, struct sdw_slave_id *id)
|
2017-12-14 13:49:34 +08:00
|
|
|
{
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_dbg(bus->dev, "SDW Slave Addr: %llx\n", addr);
|
2017-12-14 13:49:34 +08:00
|
|
|
|
2020-02-26 01:00:41 +08:00
|
|
|
id->sdw_version = SDW_VERSION(addr);
|
|
|
|
id->unique_id = SDW_UNIQUE_ID(addr);
|
|
|
|
id->mfg_id = SDW_MFG_ID(addr);
|
|
|
|
id->part_id = SDW_PART_ID(addr);
|
|
|
|
id->class_id = SDW_CLASS_ID(addr);
|
2017-12-14 13:49:34 +08:00
|
|
|
|
|
|
|
dev_dbg(bus->dev,
|
2021-01-15 13:37:34 +08:00
|
|
|
"SDW Slave class_id 0x%02x, mfg_id 0x%04x, part_id 0x%04x, unique_id 0x%x, version 0x%x\n",
|
|
|
|
id->class_id, id->mfg_id, id->part_id, id->unique_id, id->sdw_version);
|
2017-12-14 13:49:34 +08:00
|
|
|
}
|
2017-12-14 13:49:39 +08:00
|
|
|
|
|
|
|
static int sdw_program_device_num(struct sdw_bus *bus)
|
|
|
|
{
|
|
|
|
u8 buf[SDW_NUM_DEV_ID_REGISTERS] = {0};
|
|
|
|
struct sdw_slave *slave, *_s;
|
|
|
|
struct sdw_slave_id id;
|
|
|
|
struct sdw_msg msg;
|
|
|
|
bool found = false;
|
|
|
|
int count = 0, ret;
|
|
|
|
u64 addr;
|
|
|
|
|
|
|
|
/* No Slave, so use raw xfer api */
|
|
|
|
ret = sdw_fill_msg(&msg, NULL, SDW_SCP_DEVID_0,
|
2019-05-01 23:57:27 +08:00
|
|
|
SDW_NUM_DEV_ID_REGISTERS, 0, SDW_MSG_FLAG_READ, buf);
|
2017-12-14 13:49:39 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
do {
|
|
|
|
ret = sdw_transfer(bus, &msg);
|
|
|
|
if (ret == -ENODATA) { /* end of device id reads */
|
2019-08-06 08:55:09 +08:00
|
|
|
dev_dbg(bus->dev, "No more devices to enumerate\n");
|
2017-12-14 13:49:39 +08:00
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(bus->dev, "DEVID read fail:%d\n", ret);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Construct the addr and extract. Cast the higher shift
|
|
|
|
* bits to avoid truncation due to size limit.
|
|
|
|
*/
|
|
|
|
addr = buf[5] | (buf[4] << 8) | (buf[3] << 16) |
|
2018-01-09 00:52:42 +08:00
|
|
|
((u64)buf[2] << 24) | ((u64)buf[1] << 32) |
|
|
|
|
((u64)buf[0] << 40);
|
2017-12-14 13:49:39 +08:00
|
|
|
|
|
|
|
sdw_extract_slave_id(bus, addr, &id);
|
|
|
|
|
|
|
|
/* Now compare with entries */
|
|
|
|
list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
|
|
|
|
if (sdw_compare_devid(slave, id) == 0) {
|
|
|
|
found = true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assign a new dev_num to this Slave and
|
|
|
|
* not mark it present. It will be marked
|
|
|
|
* present after it reports ATTACHED on new
|
|
|
|
* dev_num
|
|
|
|
*/
|
|
|
|
ret = sdw_assign_device_num(slave);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"Assign dev_num failed:%d\n",
|
2017-12-14 13:49:39 +08:00
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-05-01 23:57:30 +08:00
|
|
|
if (!found) {
|
2017-12-14 13:49:39 +08:00
|
|
|
/* TODO: Park this device in Group 13 */
|
2020-09-25 03:44:29 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* add Slave device even if there is no platform
|
|
|
|
* firmware description. There will be no driver probe
|
|
|
|
* but the user/integration will be able to see the
|
|
|
|
* device, enumeration status and device number in sysfs
|
|
|
|
*/
|
|
|
|
sdw_slave_add(bus, &id, NULL);
|
|
|
|
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_err(bus->dev, "Slave Entry not found\n");
|
2017-12-14 13:49:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
count++;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check till error out or retry (count) exhausts.
|
|
|
|
* Device can drop off and rejoin during enumeration
|
|
|
|
* so count till twice the bound.
|
|
|
|
*/
|
|
|
|
|
|
|
|
} while (ret == 0 && count < (SDW_MAX_DEVICES * 2));
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdw_modify_slave_status(struct sdw_slave *slave,
|
2019-05-01 23:57:27 +08:00
|
|
|
enum sdw_slave_status status)
|
2017-12-14 13:49:39 +08:00
|
|
|
{
|
|
|
|
mutex_lock(&slave->bus->bus_lock);
|
2020-01-15 08:08:36 +08:00
|
|
|
|
|
|
|
dev_vdbg(&slave->dev,
|
|
|
|
"%s: changing status slave %d status %d new status %d\n",
|
|
|
|
__func__, slave->dev_num, slave->status, status);
|
|
|
|
|
|
|
|
if (status == SDW_SLAVE_UNATTACHED) {
|
|
|
|
dev_dbg(&slave->dev,
|
|
|
|
"%s: initializing completion for Slave %d\n",
|
|
|
|
__func__, slave->dev_num);
|
|
|
|
|
|
|
|
init_completion(&slave->enumeration_complete);
|
2020-01-15 08:08:37 +08:00
|
|
|
init_completion(&slave->initialization_complete);
|
2020-01-15 08:08:36 +08:00
|
|
|
|
|
|
|
} else if ((status == SDW_SLAVE_ATTACHED) &&
|
|
|
|
(slave->status == SDW_SLAVE_UNATTACHED)) {
|
|
|
|
dev_dbg(&slave->dev,
|
|
|
|
"%s: signaling completion for Slave %d\n",
|
|
|
|
__func__, slave->dev_num);
|
|
|
|
|
|
|
|
complete(&slave->enumeration_complete);
|
|
|
|
}
|
2017-12-14 13:49:39 +08:00
|
|
|
slave->status = status;
|
|
|
|
mutex_unlock(&slave->bus->bus_lock);
|
|
|
|
}
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
static enum sdw_clk_stop_mode sdw_get_clk_stop_mode(struct sdw_slave *slave)
|
|
|
|
{
|
|
|
|
enum sdw_clk_stop_mode mode;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Query for clock stop mode if Slave implements
|
|
|
|
* ops->get_clk_stop_mode, else read from property.
|
|
|
|
*/
|
|
|
|
if (slave->ops && slave->ops->get_clk_stop_mode) {
|
|
|
|
mode = slave->ops->get_clk_stop_mode(slave);
|
|
|
|
} else {
|
|
|
|
if (slave->prop.clk_stop_mode1)
|
|
|
|
mode = SDW_CLK_STOP_MODE1;
|
|
|
|
else
|
|
|
|
mode = SDW_CLK_STOP_MODE0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return mode;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_slave_clk_stop_callback(struct sdw_slave *slave,
|
|
|
|
enum sdw_clk_stop_mode mode,
|
|
|
|
enum sdw_clk_stop_type type)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (slave->ops && slave->ops->clk_stop) {
|
|
|
|
ret = slave->ops->clk_stop(slave, mode, type);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"Clk Stop type =%d failed: %d\n", type, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_slave_clk_stop_prepare(struct sdw_slave *slave,
|
|
|
|
enum sdw_clk_stop_mode mode,
|
|
|
|
bool prepare)
|
|
|
|
{
|
|
|
|
bool wake_en;
|
|
|
|
u32 val = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
wake_en = slave->prop.wake_capable;
|
|
|
|
|
|
|
|
if (prepare) {
|
|
|
|
val = SDW_SCP_SYSTEMCTRL_CLK_STP_PREP;
|
|
|
|
|
|
|
|
if (mode == SDW_CLK_STOP_MODE1)
|
|
|
|
val |= SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1;
|
|
|
|
|
|
|
|
if (wake_en)
|
|
|
|
val |= SDW_SCP_SYSTEMCTRL_WAKE_UP_EN;
|
|
|
|
} else {
|
|
|
|
val = sdw_read_no_pm(slave, SDW_SCP_SYSTEMCTRL);
|
|
|
|
|
|
|
|
val &= ~(SDW_SCP_SYSTEMCTRL_CLK_STP_PREP);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_write_no_pm(slave, SDW_SCP_SYSTEMCTRL, val);
|
|
|
|
|
|
|
|
if (ret != 0)
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"Clock Stop prepare failed for slave: %d", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_bus_wait_for_clk_prep_deprep(struct sdw_bus *bus, u16 dev_num)
|
|
|
|
{
|
|
|
|
int retry = bus->clk_stop_timeout;
|
|
|
|
int val;
|
|
|
|
|
|
|
|
do {
|
|
|
|
val = sdw_bread_no_pm(bus, dev_num, SDW_SCP_STAT) &
|
|
|
|
SDW_SCP_STAT_CLK_STP_NF;
|
|
|
|
if (!val) {
|
|
|
|
dev_info(bus->dev, "clock stop prep/de-prep done slave:%d",
|
|
|
|
dev_num);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
usleep_range(1000, 1500);
|
|
|
|
retry--;
|
|
|
|
} while (retry);
|
|
|
|
|
|
|
|
dev_err(bus->dev, "clock stop prep/de-prep failed slave:%d",
|
|
|
|
dev_num);
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_bus_prep_clk_stop: prepare Slave(s) for clock stop
|
|
|
|
*
|
|
|
|
* @bus: SDW bus instance
|
|
|
|
*
|
|
|
|
* Query Slave for clock stop mode and prepare for that mode.
|
|
|
|
*/
|
|
|
|
int sdw_bus_prep_clk_stop(struct sdw_bus *bus)
|
|
|
|
{
|
|
|
|
enum sdw_clk_stop_mode slave_mode;
|
|
|
|
bool simple_clk_stop = true;
|
|
|
|
struct sdw_slave *slave;
|
|
|
|
bool is_slave = false;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In order to save on transition time, prepare
|
|
|
|
* each Slave and then wait for all Slave(s) to be
|
|
|
|
* prepared for clock stop.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(slave, &bus->slaves, node) {
|
|
|
|
if (!slave->dev_num)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (slave->status != SDW_SLAVE_ATTACHED &&
|
|
|
|
slave->status != SDW_SLAVE_ALERT)
|
|
|
|
continue;
|
|
|
|
|
2020-05-31 23:18:06 +08:00
|
|
|
/* Identify if Slave(s) are available on Bus */
|
|
|
|
is_slave = true;
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
slave_mode = sdw_get_clk_stop_mode(slave);
|
|
|
|
slave->curr_clk_stop_mode = slave_mode;
|
|
|
|
|
|
|
|
ret = sdw_slave_clk_stop_callback(slave, slave_mode,
|
|
|
|
SDW_CLK_PRE_PREPARE);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"pre-prepare failed:%d", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_slave_clk_stop_prepare(slave,
|
|
|
|
slave_mode, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"pre-prepare failed:%d", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (slave_mode == SDW_CLK_STOP_MODE1)
|
|
|
|
simple_clk_stop = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_slave && !simple_clk_stop) {
|
|
|
|
ret = sdw_bus_wait_for_clk_prep_deprep(bus,
|
|
|
|
SDW_BROADCAST_DEV_NUM);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-05-31 23:18:06 +08:00
|
|
|
/* Don't need to inform slaves if there is no slave attached */
|
|
|
|
if (!is_slave)
|
|
|
|
return ret;
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
/* Inform slaves that prep is done */
|
|
|
|
list_for_each_entry(slave, &bus->slaves, node) {
|
|
|
|
if (!slave->dev_num)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (slave->status != SDW_SLAVE_ATTACHED &&
|
|
|
|
slave->status != SDW_SLAVE_ALERT)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
slave_mode = slave->curr_clk_stop_mode;
|
|
|
|
|
|
|
|
if (slave_mode == SDW_CLK_STOP_MODE1) {
|
|
|
|
ret = sdw_slave_clk_stop_callback(slave,
|
|
|
|
slave_mode,
|
|
|
|
SDW_CLK_POST_PREPARE);
|
|
|
|
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"post-prepare failed:%d", ret);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_bus_prep_clk_stop);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_bus_clk_stop: stop bus clock
|
|
|
|
*
|
|
|
|
* @bus: SDW bus instance
|
|
|
|
*
|
|
|
|
* After preparing the Slaves for clock stop, stop the clock by broadcasting
|
|
|
|
* write to SCP_CTRL register.
|
|
|
|
*/
|
|
|
|
int sdw_bus_clk_stop(struct sdw_bus *bus)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* broadcast clock stop now, attached Slaves will ACK this,
|
|
|
|
* unattached will ignore
|
|
|
|
*/
|
|
|
|
ret = sdw_bwrite_no_pm(bus, SDW_BROADCAST_DEV_NUM,
|
|
|
|
SDW_SCP_CTRL, SDW_SCP_CTRL_CLK_STP_NOW);
|
|
|
|
if (ret < 0) {
|
2020-01-15 08:08:44 +08:00
|
|
|
if (ret == -ENODATA)
|
|
|
|
dev_dbg(bus->dev,
|
|
|
|
"ClockStopNow Broadcast msg ignored %d", ret);
|
|
|
|
else
|
|
|
|
dev_err(bus->dev,
|
|
|
|
"ClockStopNow Broadcast msg failed %d", ret);
|
2020-01-15 08:08:43 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_bus_clk_stop);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_bus_exit_clk_stop: Exit clock stop mode
|
|
|
|
*
|
|
|
|
* @bus: SDW bus instance
|
|
|
|
*
|
|
|
|
* This De-prepares the Slaves by exiting Clock Stop Mode 0. For the Slaves
|
|
|
|
* exiting Clock Stop Mode 1, they will be de-prepared after they enumerate
|
|
|
|
* back.
|
|
|
|
*/
|
|
|
|
int sdw_bus_exit_clk_stop(struct sdw_bus *bus)
|
|
|
|
{
|
|
|
|
enum sdw_clk_stop_mode mode;
|
|
|
|
bool simple_clk_stop = true;
|
|
|
|
struct sdw_slave *slave;
|
|
|
|
bool is_slave = false;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In order to save on transition time, de-prepare
|
|
|
|
* each Slave and then wait for all Slave(s) to be
|
|
|
|
* de-prepared after clock resume.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(slave, &bus->slaves, node) {
|
|
|
|
if (!slave->dev_num)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (slave->status != SDW_SLAVE_ATTACHED &&
|
|
|
|
slave->status != SDW_SLAVE_ALERT)
|
|
|
|
continue;
|
|
|
|
|
2020-05-31 23:18:06 +08:00
|
|
|
/* Identify if Slave(s) are available on Bus */
|
|
|
|
is_slave = true;
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
mode = slave->curr_clk_stop_mode;
|
|
|
|
|
|
|
|
if (mode == SDW_CLK_STOP_MODE1) {
|
|
|
|
simple_clk_stop = false;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_slave_clk_stop_callback(slave, mode,
|
|
|
|
SDW_CLK_PRE_DEPREPARE);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_warn(&slave->dev,
|
|
|
|
"clk stop deprep failed:%d", ret);
|
|
|
|
|
|
|
|
ret = sdw_slave_clk_stop_prepare(slave, mode,
|
|
|
|
false);
|
|
|
|
|
|
|
|
if (ret < 0)
|
|
|
|
dev_warn(&slave->dev,
|
|
|
|
"clk stop deprep failed:%d", ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_slave && !simple_clk_stop)
|
|
|
|
sdw_bus_wait_for_clk_prep_deprep(bus, SDW_BROADCAST_DEV_NUM);
|
|
|
|
|
2020-05-31 23:18:06 +08:00
|
|
|
/*
|
|
|
|
* Don't need to call slave callback function if there is no slave
|
|
|
|
* attached
|
|
|
|
*/
|
|
|
|
if (!is_slave)
|
|
|
|
return 0;
|
|
|
|
|
2020-01-15 08:08:43 +08:00
|
|
|
list_for_each_entry(slave, &bus->slaves, node) {
|
|
|
|
if (!slave->dev_num)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (slave->status != SDW_SLAVE_ATTACHED &&
|
|
|
|
slave->status != SDW_SLAVE_ALERT)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
mode = slave->curr_clk_stop_mode;
|
|
|
|
sdw_slave_clk_stop_callback(slave, mode,
|
|
|
|
SDW_CLK_POST_DEPREPARE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_bus_exit_clk_stop);
|
|
|
|
|
2018-04-26 21:08:23 +08:00
|
|
|
int sdw_configure_dpn_intr(struct sdw_slave *slave,
|
2019-05-01 23:57:27 +08:00
|
|
|
int port, bool enable, int mask)
|
2018-04-26 21:08:23 +08:00
|
|
|
{
|
|
|
|
u32 addr;
|
|
|
|
int ret;
|
|
|
|
u8 val = 0;
|
|
|
|
|
2020-09-21 03:32:05 +08:00
|
|
|
if (slave->bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL) {
|
|
|
|
dev_dbg(&slave->dev, "TEST FAIL interrupt %s\n",
|
|
|
|
enable ? "on" : "off");
|
|
|
|
mask |= SDW_DPN_INT_TEST_FAIL;
|
|
|
|
}
|
|
|
|
|
2018-04-26 21:08:23 +08:00
|
|
|
addr = SDW_DPN_INTMASK(port);
|
|
|
|
|
|
|
|
/* Set/Clear port ready interrupt mask */
|
|
|
|
if (enable) {
|
|
|
|
val |= mask;
|
|
|
|
val |= SDW_DPN_INT_PORT_READY;
|
|
|
|
} else {
|
|
|
|
val &= ~(mask);
|
|
|
|
val &= ~SDW_DPN_INT_PORT_READY;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_update(slave, addr, (mask | SDW_DPN_INT_PORT_READY), val);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DPN_INTMASK write failed:%d\n", val);
|
2018-04-26 21:08:23 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-06-09 04:54:36 +08:00
|
|
|
static int sdw_slave_set_frequency(struct sdw_slave *slave)
|
|
|
|
{
|
|
|
|
u32 mclk_freq = slave->bus->prop.mclk_freq;
|
|
|
|
u32 curr_freq = slave->bus->params.curr_dr_freq >> 1;
|
|
|
|
unsigned int scale;
|
|
|
|
u8 scale_index;
|
|
|
|
u8 base;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* frequency base and scale registers are required for SDCA
|
|
|
|
* devices. They may also be used for 1.2+/non-SDCA devices,
|
|
|
|
* but we will need a DisCo property to cover this case
|
|
|
|
*/
|
|
|
|
if (!slave->id.class_id)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!mclk_freq) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"no bus MCLK, cannot set SDW_SCP_BUS_CLOCK_BASE\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* map base frequency using Table 89 of SoundWire 1.2 spec.
|
|
|
|
* The order of the tests just follows the specification, this
|
|
|
|
* is not a selection between possible values or a search for
|
|
|
|
* the best value but just a mapping. Only one case per platform
|
|
|
|
* is relevant.
|
|
|
|
* Some BIOS have inconsistent values for mclk_freq but a
|
|
|
|
* correct root so we force the mclk_freq to avoid variations.
|
|
|
|
*/
|
|
|
|
if (!(19200000 % mclk_freq)) {
|
|
|
|
mclk_freq = 19200000;
|
|
|
|
base = SDW_SCP_BASE_CLOCK_19200000_HZ;
|
|
|
|
} else if (!(24000000 % mclk_freq)) {
|
|
|
|
mclk_freq = 24000000;
|
|
|
|
base = SDW_SCP_BASE_CLOCK_24000000_HZ;
|
|
|
|
} else if (!(24576000 % mclk_freq)) {
|
|
|
|
mclk_freq = 24576000;
|
|
|
|
base = SDW_SCP_BASE_CLOCK_24576000_HZ;
|
|
|
|
} else if (!(22579200 % mclk_freq)) {
|
|
|
|
mclk_freq = 22579200;
|
|
|
|
base = SDW_SCP_BASE_CLOCK_22579200_HZ;
|
|
|
|
} else if (!(32000000 % mclk_freq)) {
|
|
|
|
mclk_freq = 32000000;
|
|
|
|
base = SDW_SCP_BASE_CLOCK_32000000_HZ;
|
|
|
|
} else {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"Unsupported clock base, mclk %d\n",
|
|
|
|
mclk_freq);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mclk_freq % curr_freq) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"mclk %d is not multiple of bus curr_freq %d\n",
|
|
|
|
mclk_freq, curr_freq);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
scale = mclk_freq / curr_freq;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* map scale to Table 90 of SoundWire 1.2 spec - and check
|
|
|
|
* that the scale is a power of two and maximum 64
|
|
|
|
*/
|
|
|
|
scale_index = ilog2(scale);
|
|
|
|
|
|
|
|
if (BIT(scale_index) != scale || scale_index > 6) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"No match found for scale %d, bus mclk %d curr_freq %d\n",
|
|
|
|
scale, mclk_freq, curr_freq);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
scale_index++;
|
|
|
|
|
|
|
|
ret = sdw_write(slave, SDW_SCP_BUS_CLOCK_BASE, base);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"SDW_SCP_BUS_CLOCK_BASE write failed:%d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* initialize scale for both banks */
|
|
|
|
ret = sdw_write(slave, SDW_SCP_BUSCLOCK_SCALE_B0, scale_index);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"SDW_SCP_BUSCLOCK_SCALE_B0 write failed:%d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = sdw_write(slave, SDW_SCP_BUSCLOCK_SCALE_B1, scale_index);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_err(&slave->dev,
|
|
|
|
"SDW_SCP_BUSCLOCK_SCALE_B1 write failed:%d\n", ret);
|
|
|
|
|
|
|
|
dev_dbg(&slave->dev,
|
|
|
|
"Configured bus base %d, scale %d, mclk %d, curr_freq %d\n",
|
|
|
|
base, scale_index, mclk_freq, curr_freq);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-12-14 13:49:39 +08:00
|
|
|
static int sdw_initialize_slave(struct sdw_slave *slave)
|
|
|
|
{
|
|
|
|
struct sdw_slave_prop *prop = &slave->prop;
|
|
|
|
int ret;
|
|
|
|
u8 val;
|
|
|
|
|
2020-06-09 04:54:36 +08:00
|
|
|
ret = sdw_slave_set_frequency(slave);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2017-12-14 13:49:39 +08:00
|
|
|
/*
|
2020-09-08 21:45:15 +08:00
|
|
|
* Set SCP_INT1_MASK register, typically bus clash and
|
|
|
|
* implementation-defined interrupt mask. The Parity detection
|
|
|
|
* may not always be correct on startup so its use is
|
|
|
|
* device-dependent, it might e.g. only be enabled in
|
|
|
|
* steady-state after a couple of frames.
|
2017-12-14 13:49:39 +08:00
|
|
|
*/
|
2020-09-08 21:45:15 +08:00
|
|
|
val = slave->prop.scp_int1_mask;
|
2017-12-14 13:49:39 +08:00
|
|
|
|
|
|
|
/* Enable SCP interrupts */
|
|
|
|
ret = sdw_update(slave, SDW_SCP_INTMASK1, val, val);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_SCP_INTMASK1 write failed:%d\n", ret);
|
2017-12-14 13:49:39 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No need to continue if DP0 is not present */
|
|
|
|
if (!slave->prop.dp0_prop)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Enable DP0 interrupts */
|
2019-05-23 03:47:25 +08:00
|
|
|
val = prop->dp0_prop->imp_def_interrupts;
|
2017-12-14 13:49:39 +08:00
|
|
|
val |= SDW_DP0_INT_PORT_READY | SDW_DP0_INT_BRA_FAILURE;
|
|
|
|
|
|
|
|
ret = sdw_update(slave, SDW_DP0_INTMASK, val, val);
|
2020-02-28 06:09:49 +08:00
|
|
|
if (ret < 0)
|
2017-12-14 13:49:39 +08:00
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DP0_INTMASK read failed:%d\n", ret);
|
2020-02-28 06:09:49 +08:00
|
|
|
return ret;
|
2017-12-14 13:49:39 +08:00
|
|
|
}
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
static int sdw_handle_dp0_interrupt(struct sdw_slave *slave, u8 *slave_status)
|
|
|
|
{
|
2020-11-24 09:33:17 +08:00
|
|
|
u8 clear, impl_int_mask;
|
2017-12-14 13:49:40 +08:00
|
|
|
int status, status2, ret, count = 0;
|
|
|
|
|
|
|
|
status = sdw_read(slave, SDW_DP0_INT);
|
|
|
|
if (status < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DP0_INT read failed:%d\n", status);
|
2017-12-14 13:49:40 +08:00
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
do {
|
2020-11-24 09:33:17 +08:00
|
|
|
clear = status & ~SDW_DP0_INTERRUPTS;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
if (status & SDW_DP0_INT_TEST_FAIL) {
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_err(&slave->dev, "Test fail for port 0\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
clear |= SDW_DP0_INT_TEST_FAIL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assumption: PORT_READY interrupt will be received only for
|
|
|
|
* ports implementing Channel Prepare state machine (CP_SM)
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (status & SDW_DP0_INT_PORT_READY) {
|
|
|
|
complete(&slave->port_ready[0]);
|
|
|
|
clear |= SDW_DP0_INT_PORT_READY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & SDW_DP0_INT_BRA_FAILURE) {
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_err(&slave->dev, "BRA failed\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
clear |= SDW_DP0_INT_BRA_FAILURE;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl_int_mask = SDW_DP0_INT_IMPDEF1 |
|
|
|
|
SDW_DP0_INT_IMPDEF2 | SDW_DP0_INT_IMPDEF3;
|
|
|
|
|
|
|
|
if (status & impl_int_mask) {
|
|
|
|
clear |= impl_int_mask;
|
|
|
|
*slave_status = clear;
|
|
|
|
}
|
|
|
|
|
2020-11-24 09:33:17 +08:00
|
|
|
/* clear the interrupts but don't touch reserved and SDCA_CASCADE fields */
|
2017-12-14 13:49:40 +08:00
|
|
|
ret = sdw_write(slave, SDW_DP0_INT, clear);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DP0_INT write failed:%d\n", ret);
|
2017-12-14 13:49:40 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read DP0 interrupt again */
|
|
|
|
status2 = sdw_read(slave, SDW_DP0_INT);
|
|
|
|
if (status2 < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DP0_INT read failed:%d\n", status2);
|
2018-01-09 00:52:44 +08:00
|
|
|
return status2;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
2020-11-24 09:33:14 +08:00
|
|
|
/* filter to limit loop to interrupts identified in the first status read */
|
2017-12-14 13:49:40 +08:00
|
|
|
status &= status2;
|
|
|
|
|
|
|
|
count++;
|
|
|
|
|
|
|
|
/* we can get alerts while processing so keep retrying */
|
2020-11-24 09:33:17 +08:00
|
|
|
} while ((status & SDW_DP0_INTERRUPTS) && (count < SDW_READ_INTR_CLEAR_RETRY));
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
if (count == SDW_READ_INTR_CLEAR_RETRY)
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_warn(slave->bus->dev, "Reached MAX_RETRY on DP0 read\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_handle_port_interrupt(struct sdw_slave *slave,
|
2019-05-01 23:57:27 +08:00
|
|
|
int port, u8 *slave_status)
|
2017-12-14 13:49:40 +08:00
|
|
|
{
|
2020-11-24 09:33:18 +08:00
|
|
|
u8 clear, impl_int_mask;
|
2017-12-14 13:49:40 +08:00
|
|
|
int status, status2, ret, count = 0;
|
|
|
|
u32 addr;
|
|
|
|
|
|
|
|
if (port == 0)
|
|
|
|
return sdw_handle_dp0_interrupt(slave, slave_status);
|
|
|
|
|
|
|
|
addr = SDW_DPN_INT(port);
|
|
|
|
status = sdw_read(slave, addr);
|
|
|
|
if (status < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DPN_INT read failed:%d\n", status);
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
do {
|
2020-11-24 09:33:18 +08:00
|
|
|
clear = status & ~SDW_DPN_INTERRUPTS;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
if (status & SDW_DPN_INT_TEST_FAIL) {
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_err(&slave->dev, "Test fail for port:%d\n", port);
|
2017-12-14 13:49:40 +08:00
|
|
|
clear |= SDW_DPN_INT_TEST_FAIL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assumption: PORT_READY interrupt will be received only
|
|
|
|
* for ports implementing CP_SM.
|
|
|
|
*/
|
|
|
|
if (status & SDW_DPN_INT_PORT_READY) {
|
|
|
|
complete(&slave->port_ready[port]);
|
|
|
|
clear |= SDW_DPN_INT_PORT_READY;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl_int_mask = SDW_DPN_INT_IMPDEF1 |
|
|
|
|
SDW_DPN_INT_IMPDEF2 | SDW_DPN_INT_IMPDEF3;
|
|
|
|
|
|
|
|
if (status & impl_int_mask) {
|
|
|
|
clear |= impl_int_mask;
|
|
|
|
*slave_status = clear;
|
|
|
|
}
|
|
|
|
|
2020-11-24 09:33:18 +08:00
|
|
|
/* clear the interrupt but don't touch reserved fields */
|
2017-12-14 13:49:40 +08:00
|
|
|
ret = sdw_write(slave, addr, clear);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DPN_INT write failed:%d\n", ret);
|
2017-12-14 13:49:40 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read DPN interrupt again */
|
|
|
|
status2 = sdw_read(slave, addr);
|
2018-01-09 00:52:44 +08:00
|
|
|
if (status2 < 0) {
|
2017-12-14 13:49:40 +08:00
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_DPN_INT read failed:%d\n", status2);
|
2018-01-09 00:52:44 +08:00
|
|
|
return status2;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
2020-11-24 09:33:14 +08:00
|
|
|
/* filter to limit loop to interrupts identified in the first status read */
|
2017-12-14 13:49:40 +08:00
|
|
|
status &= status2;
|
|
|
|
|
|
|
|
count++;
|
|
|
|
|
|
|
|
/* we can get alerts while processing so keep retrying */
|
2020-11-24 09:33:18 +08:00
|
|
|
} while ((status & SDW_DPN_INTERRUPTS) && (count < SDW_READ_INTR_CLEAR_RETRY));
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
if (count == SDW_READ_INTR_CLEAR_RETRY)
|
|
|
|
dev_warn(slave->bus->dev, "Reached MAX_RETRY on port read");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_handle_slave_alerts(struct sdw_slave *slave)
|
|
|
|
{
|
|
|
|
struct sdw_slave_intr_status slave_intr;
|
2019-08-30 02:11:35 +08:00
|
|
|
u8 clear = 0, bit, port_status[15] = {0};
|
2017-12-14 13:49:40 +08:00
|
|
|
int port_num, stat, ret, count = 0;
|
|
|
|
unsigned long port;
|
2020-11-24 09:33:15 +08:00
|
|
|
bool slave_notify;
|
2020-11-04 23:23:58 +08:00
|
|
|
u8 sdca_cascade = 0;
|
2017-12-14 13:49:40 +08:00
|
|
|
u8 buf, buf2[2], _buf, _buf2[2];
|
2020-09-08 21:45:18 +08:00
|
|
|
bool parity_check;
|
|
|
|
bool parity_quirk;
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
sdw_modify_slave_status(slave, SDW_SLAVE_ALERT);
|
|
|
|
|
2020-01-15 08:08:42 +08:00
|
|
|
ret = pm_runtime_get_sync(&slave->dev);
|
|
|
|
if (ret < 0 && ret != -EACCES) {
|
|
|
|
dev_err(&slave->dev, "Failed to resume device: %d\n", ret);
|
|
|
|
pm_runtime_put_noidle(slave->bus->dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-08-18 06:09:33 +08:00
|
|
|
/* Read Intstat 1, Intstat 2 and Intstat 3 registers */
|
2019-05-02 18:59:26 +08:00
|
|
|
ret = sdw_read(slave, SDW_SCP_INT1);
|
2017-12-14 13:49:40 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_SCP_INT1 read failed:%d\n", ret);
|
2020-01-15 08:08:42 +08:00
|
|
|
goto io_err;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
2019-05-02 18:59:26 +08:00
|
|
|
buf = ret;
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
ret = sdw_nread(slave, SDW_SCP_INTSTAT2, 2, buf2);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_SCP_INT2/3 read failed:%d\n", ret);
|
2020-01-15 08:08:42 +08:00
|
|
|
goto io_err;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
2020-11-04 23:23:58 +08:00
|
|
|
if (slave->prop.is_sdca) {
|
|
|
|
ret = sdw_read(slave, SDW_DP0_INT);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
|
|
|
"SDW_DP0_INT read failed:%d\n", ret);
|
|
|
|
goto io_err;
|
|
|
|
}
|
|
|
|
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
|
|
|
|
}
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
do {
|
2020-11-24 09:33:15 +08:00
|
|
|
slave_notify = false;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
/*
|
|
|
|
* Check parity, bus clash and Slave (impl defined)
|
|
|
|
* interrupt
|
|
|
|
*/
|
|
|
|
if (buf & SDW_SCP_INT1_PARITY) {
|
2020-09-08 21:45:18 +08:00
|
|
|
parity_check = slave->prop.scp_int1_mask & SDW_SCP_INT1_PARITY;
|
|
|
|
parity_quirk = !slave->first_interrupt_done &&
|
|
|
|
(slave->prop.quirks & SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY);
|
|
|
|
|
|
|
|
if (parity_check && !parity_quirk)
|
2020-09-08 21:45:16 +08:00
|
|
|
dev_err(&slave->dev, "Parity error detected\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
clear |= SDW_SCP_INT1_PARITY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (buf & SDW_SCP_INT1_BUS_CLASH) {
|
2020-09-08 21:45:16 +08:00
|
|
|
if (slave->prop.scp_int1_mask & SDW_SCP_INT1_BUS_CLASH)
|
|
|
|
dev_err(&slave->dev, "Bus clash detected\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
clear |= SDW_SCP_INT1_BUS_CLASH;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When bus clash or parity errors are detected, such errors
|
|
|
|
* are unlikely to be recoverable errors.
|
|
|
|
* TODO: In such scenario, reset bus. Make this configurable
|
|
|
|
* via sysfs property with bus reset being the default.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (buf & SDW_SCP_INT1_IMPL_DEF) {
|
2020-09-08 21:45:16 +08:00
|
|
|
if (slave->prop.scp_int1_mask & SDW_SCP_INT1_IMPL_DEF) {
|
|
|
|
dev_dbg(&slave->dev, "Slave impl defined interrupt\n");
|
|
|
|
slave_notify = true;
|
|
|
|
}
|
2017-12-14 13:49:40 +08:00
|
|
|
clear |= SDW_SCP_INT1_IMPL_DEF;
|
|
|
|
}
|
|
|
|
|
2020-11-04 23:23:58 +08:00
|
|
|
/* the SDCA interrupts are cleared in the codec driver .interrupt_callback() */
|
|
|
|
if (sdca_cascade)
|
|
|
|
slave_notify = true;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
/* Check port 0 - 3 interrupts */
|
|
|
|
port = buf & SDW_SCP_INT1_PORT0_3;
|
|
|
|
|
|
|
|
/* To get port number corresponding to bits, shift it */
|
2020-09-03 19:44:57 +08:00
|
|
|
port = FIELD_GET(SDW_SCP_INT1_PORT0_3, port);
|
2017-12-14 13:49:40 +08:00
|
|
|
for_each_set_bit(bit, &port, 8) {
|
|
|
|
sdw_handle_port_interrupt(slave, bit,
|
2019-05-01 23:57:27 +08:00
|
|
|
&port_status[bit]);
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if cascade 2 interrupt is present */
|
|
|
|
if (buf & SDW_SCP_INT1_SCP2_CASCADE) {
|
|
|
|
port = buf2[0] & SDW_SCP_INTSTAT2_PORT4_10;
|
|
|
|
for_each_set_bit(bit, &port, 8) {
|
|
|
|
/* scp2 ports start from 4 */
|
|
|
|
port_num = bit + 3;
|
|
|
|
sdw_handle_port_interrupt(slave,
|
|
|
|
port_num,
|
|
|
|
&port_status[port_num]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* now check last cascade */
|
|
|
|
if (buf2[0] & SDW_SCP_INTSTAT2_SCP3_CASCADE) {
|
|
|
|
port = buf2[1] & SDW_SCP_INTSTAT3_PORT11_14;
|
|
|
|
for_each_set_bit(bit, &port, 8) {
|
|
|
|
/* scp3 ports start from 11 */
|
|
|
|
port_num = bit + 10;
|
|
|
|
sdw_handle_port_interrupt(slave,
|
|
|
|
port_num,
|
|
|
|
&port_status[port_num]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update the Slave driver */
|
2019-05-01 23:57:29 +08:00
|
|
|
if (slave_notify && slave->ops &&
|
|
|
|
slave->ops->interrupt_callback) {
|
2020-11-04 23:23:58 +08:00
|
|
|
slave_intr.sdca_cascade = sdca_cascade;
|
2017-12-14 13:49:40 +08:00
|
|
|
slave_intr.control_port = clear;
|
|
|
|
memcpy(slave_intr.port, &port_status,
|
2019-05-01 23:57:27 +08:00
|
|
|
sizeof(slave_intr.port));
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
slave->ops->interrupt_callback(slave, &slave_intr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Ack interrupt */
|
|
|
|
ret = sdw_write(slave, SDW_SCP_INT1, clear);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_SCP_INT1 write failed:%d\n", ret);
|
2020-01-15 08:08:42 +08:00
|
|
|
goto io_err;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
2020-09-08 21:45:17 +08:00
|
|
|
/* at this point all initial interrupt sources were handled */
|
|
|
|
slave->first_interrupt_done = true;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
/*
|
|
|
|
* Read status again to ensure no new interrupts arrived
|
|
|
|
* while servicing interrupts.
|
|
|
|
*/
|
2019-05-02 18:59:26 +08:00
|
|
|
ret = sdw_read(slave, SDW_SCP_INT1);
|
2017-12-14 13:49:40 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_SCP_INT1 read failed:%d\n", ret);
|
2020-01-15 08:08:42 +08:00
|
|
|
goto io_err;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
2019-05-02 18:59:26 +08:00
|
|
|
_buf = ret;
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
ret = sdw_nread(slave, SDW_SCP_INTSTAT2, 2, _buf2);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"SDW_SCP_INT2/3 read failed:%d\n", ret);
|
2020-01-15 08:08:42 +08:00
|
|
|
goto io_err;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
2020-11-04 23:23:58 +08:00
|
|
|
if (slave->prop.is_sdca) {
|
|
|
|
ret = sdw_read(slave, SDW_DP0_INT);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(slave->bus->dev,
|
|
|
|
"SDW_DP0_INT read failed:%d\n", ret);
|
|
|
|
goto io_err;
|
|
|
|
}
|
|
|
|
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
|
|
|
|
}
|
|
|
|
|
2020-11-24 09:33:14 +08:00
|
|
|
/*
|
|
|
|
* Make sure no interrupts are pending, but filter to limit loop
|
|
|
|
* to interrupts identified in the first status read
|
|
|
|
*/
|
2017-12-14 13:49:40 +08:00
|
|
|
buf &= _buf;
|
|
|
|
buf2[0] &= _buf2[0];
|
|
|
|
buf2[1] &= _buf2[1];
|
2020-11-04 23:23:58 +08:00
|
|
|
stat = buf || buf2[0] || buf2[1] || sdca_cascade;
|
2017-12-14 13:49:40 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Exit loop if Slave is continuously in ALERT state even
|
|
|
|
* after servicing the interrupt multiple times.
|
|
|
|
*/
|
|
|
|
count++;
|
|
|
|
|
|
|
|
/* we can get alerts while processing so keep retrying */
|
|
|
|
} while (stat != 0 && count < SDW_READ_INTR_CLEAR_RETRY);
|
|
|
|
|
|
|
|
if (count == SDW_READ_INTR_CLEAR_RETRY)
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_warn(slave->bus->dev, "Reached MAX_RETRY on alert read\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
|
2020-01-15 08:08:42 +08:00
|
|
|
io_err:
|
|
|
|
pm_runtime_mark_last_busy(&slave->dev);
|
|
|
|
pm_runtime_put_autosuspend(&slave->dev);
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdw_update_slave_status(struct sdw_slave *slave,
|
2019-05-01 23:57:27 +08:00
|
|
|
enum sdw_slave_status status)
|
2017-12-14 13:49:40 +08:00
|
|
|
{
|
2020-01-15 08:08:35 +08:00
|
|
|
unsigned long time;
|
2017-12-14 13:49:40 +08:00
|
|
|
|
2020-01-15 08:08:35 +08:00
|
|
|
if (!slave->probed) {
|
|
|
|
/*
|
|
|
|
* the slave status update is typically handled in an
|
|
|
|
* interrupt thread, which can race with the driver
|
|
|
|
* probe, e.g. when a module needs to be loaded.
|
|
|
|
*
|
|
|
|
* make sure the probe is complete before updating
|
|
|
|
* status.
|
|
|
|
*/
|
|
|
|
time = wait_for_completion_timeout(&slave->probe_complete,
|
|
|
|
msecs_to_jiffies(DEFAULT_PROBE_TIMEOUT));
|
|
|
|
if (!time) {
|
|
|
|
dev_err(&slave->dev, "Probe not complete, timed out\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!slave->ops || !slave->ops->update_status)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return slave->ops->update_status(slave, status);
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_handle_slave_status() - Handle Slave status
|
|
|
|
* @bus: SDW bus instance
|
|
|
|
* @status: Status for all Slave(s)
|
|
|
|
*/
|
|
|
|
int sdw_handle_slave_status(struct sdw_bus *bus,
|
2019-05-01 23:57:27 +08:00
|
|
|
enum sdw_slave_status status[])
|
2017-12-14 13:49:40 +08:00
|
|
|
{
|
|
|
|
enum sdw_slave_status prev_status;
|
|
|
|
struct sdw_slave *slave;
|
2020-01-15 08:08:37 +08:00
|
|
|
bool attached_initializing;
|
2017-12-14 13:49:40 +08:00
|
|
|
int i, ret = 0;
|
|
|
|
|
2020-01-11 05:57:31 +08:00
|
|
|
/* first check if any Slaves fell off the bus */
|
|
|
|
for (i = 1; i <= SDW_MAX_DEVICES; i++) {
|
|
|
|
mutex_lock(&bus->bus_lock);
|
|
|
|
if (test_bit(i, bus->assigned) == false) {
|
|
|
|
mutex_unlock(&bus->bus_lock);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
mutex_unlock(&bus->bus_lock);
|
|
|
|
|
|
|
|
slave = sdw_get_slave(bus, i);
|
|
|
|
if (!slave)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (status[i] == SDW_SLAVE_UNATTACHED &&
|
|
|
|
slave->status != SDW_SLAVE_UNATTACHED)
|
|
|
|
sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
|
|
|
|
}
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
if (status[0] == SDW_SLAVE_ATTACHED) {
|
2019-08-06 08:55:09 +08:00
|
|
|
dev_dbg(bus->dev, "Slave attached, programming device number\n");
|
2017-12-14 13:49:40 +08:00
|
|
|
ret = sdw_program_device_num(bus);
|
|
|
|
if (ret)
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_err(bus->dev, "Slave attach failed: %d\n", ret);
|
2019-07-26 07:40:10 +08:00
|
|
|
/*
|
|
|
|
* programming a device number will have side effects,
|
|
|
|
* so we deal with other devices at a later time
|
|
|
|
*/
|
|
|
|
return ret;
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Continue to check other slave statuses */
|
|
|
|
for (i = 1; i <= SDW_MAX_DEVICES; i++) {
|
|
|
|
mutex_lock(&bus->bus_lock);
|
|
|
|
if (test_bit(i, bus->assigned) == false) {
|
|
|
|
mutex_unlock(&bus->bus_lock);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
mutex_unlock(&bus->bus_lock);
|
|
|
|
|
|
|
|
slave = sdw_get_slave(bus, i);
|
|
|
|
if (!slave)
|
|
|
|
continue;
|
|
|
|
|
2020-01-15 08:08:37 +08:00
|
|
|
attached_initializing = false;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
switch (status[i]) {
|
|
|
|
case SDW_SLAVE_UNATTACHED:
|
|
|
|
if (slave->status == SDW_SLAVE_UNATTACHED)
|
|
|
|
break;
|
|
|
|
|
|
|
|
sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SDW_SLAVE_ALERT:
|
|
|
|
ret = sdw_handle_slave_alerts(slave);
|
|
|
|
if (ret)
|
|
|
|
dev_err(bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"Slave %d alert handling failed: %d\n",
|
2017-12-14 13:49:40 +08:00
|
|
|
i, ret);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SDW_SLAVE_ATTACHED:
|
|
|
|
if (slave->status == SDW_SLAVE_ATTACHED)
|
|
|
|
break;
|
|
|
|
|
|
|
|
prev_status = slave->status;
|
|
|
|
sdw_modify_slave_status(slave, SDW_SLAVE_ATTACHED);
|
|
|
|
|
|
|
|
if (prev_status == SDW_SLAVE_ALERT)
|
|
|
|
break;
|
|
|
|
|
2020-01-15 08:08:37 +08:00
|
|
|
attached_initializing = true;
|
|
|
|
|
2017-12-14 13:49:40 +08:00
|
|
|
ret = sdw_initialize_slave(slave);
|
|
|
|
if (ret)
|
|
|
|
dev_err(bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"Slave %d initialization failed: %d\n",
|
2017-12-14 13:49:40 +08:00
|
|
|
i, ret);
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2019-05-01 23:57:45 +08:00
|
|
|
dev_err(bus->dev, "Invalid slave %d status:%d\n",
|
2019-05-01 23:57:27 +08:00
|
|
|
i, status[i]);
|
2017-12-14 13:49:40 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sdw_update_slave_status(slave, status[i]);
|
|
|
|
if (ret)
|
|
|
|
dev_err(slave->bus->dev,
|
2019-05-01 23:57:45 +08:00
|
|
|
"Update Slave status failed:%d\n", ret);
|
2020-01-15 08:08:37 +08:00
|
|
|
if (attached_initializing)
|
|
|
|
complete(&slave->initialization_complete);
|
2017-12-14 13:49:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_handle_slave_status);
|
2020-01-15 08:08:40 +08:00
|
|
|
|
|
|
|
void sdw_clear_slave_status(struct sdw_bus *bus, u32 request)
|
|
|
|
{
|
|
|
|
struct sdw_slave *slave;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Check all non-zero devices */
|
|
|
|
for (i = 1; i <= SDW_MAX_DEVICES; i++) {
|
|
|
|
mutex_lock(&bus->bus_lock);
|
|
|
|
if (test_bit(i, bus->assigned) == false) {
|
|
|
|
mutex_unlock(&bus->bus_lock);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
mutex_unlock(&bus->bus_lock);
|
|
|
|
|
|
|
|
slave = sdw_get_slave(bus, i);
|
|
|
|
if (!slave)
|
|
|
|
continue;
|
|
|
|
|
2020-09-08 21:45:17 +08:00
|
|
|
if (slave->status != SDW_SLAVE_UNATTACHED) {
|
2020-01-15 08:08:40 +08:00
|
|
|
sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
|
2020-09-08 21:45:17 +08:00
|
|
|
slave->first_interrupt_done = false;
|
|
|
|
}
|
2020-01-15 08:08:40 +08:00
|
|
|
|
|
|
|
/* keep track of request, used in pm_runtime resume */
|
|
|
|
slave->unattach_request = request;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_clear_slave_status);
|