2015-10-30 09:02:51 +08:00
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/*
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2015-11-27 01:17:05 +08:00
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* PCIe host controller driver for HiSilicon SoCs
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2015-10-30 09:02:51 +08:00
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*
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* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
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*
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2015-11-27 01:17:05 +08:00
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* Authors: Zhou Wang <wangzhou1@hisilicon.com>
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* Dacai Zhu <zhudacai@hisilicon.com>
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* Gabriele Paoloni <gabriele.paoloni@huawei.com>
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2015-10-30 09:02:51 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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2015-11-27 01:17:05 +08:00
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#include <linux/of_device.h>
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2015-10-30 09:02:51 +08:00
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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2015-11-27 01:17:05 +08:00
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#define PCIE_LTSSM_LINKUP_STATE 0x11
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#define PCIE_LTSSM_STATE_MASK 0x3F
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#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
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#define PCIE_SYS_STATE4 0x31c
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#define PCIE_HIP06_CTRL_OFF 0x1000
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2015-10-30 09:02:51 +08:00
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#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
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2015-11-27 01:17:05 +08:00
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struct hisi_pcie;
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struct pcie_soc_ops {
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int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
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};
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2015-10-30 09:02:51 +08:00
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struct hisi_pcie {
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struct regmap *subctrl;
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void __iomem *reg_base;
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u32 port_id;
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struct pcie_port pp;
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2015-11-27 01:17:05 +08:00
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struct pcie_soc_ops *soc_ops;
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2015-10-30 09:02:51 +08:00
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};
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static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
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u32 val, u32 reg)
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{
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writel(val, pcie->reg_base + reg);
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}
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static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
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{
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return readl(pcie->reg_base + reg);
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}
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2015-11-27 01:17:05 +08:00
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/* HipXX PCIe host only supports 32-bit config access */
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2015-10-30 09:02:51 +08:00
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static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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u32 reg;
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u32 reg_val;
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struct hisi_pcie *pcie = to_hisi_pcie(pp);
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void *walker = ®_val;
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walker += (where & 0x3);
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reg = where & ~0x3;
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reg_val = hisi_pcie_apb_readl(pcie, reg);
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if (size == 1)
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*val = *(u8 __force *) walker;
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else if (size == 2)
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*val = *(u16 __force *) walker;
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2015-12-05 06:32:25 +08:00
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else if (size == 4)
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*val = reg_val;
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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2015-11-27 01:17:05 +08:00
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/* HipXX PCIe host only supports 32-bit config access */
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static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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u32 reg_val;
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u32 reg;
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struct hisi_pcie *pcie = to_hisi_pcie(pp);
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void *walker = ®_val;
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walker += (where & 0x3);
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reg = where & ~0x3;
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if (size == 4)
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hisi_pcie_apb_writel(pcie, val, reg);
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else if (size == 2) {
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reg_val = hisi_pcie_apb_readl(pcie, reg);
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*(u16 __force *) walker = val;
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hisi_pcie_apb_writel(pcie, reg_val, reg);
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} else if (size == 1) {
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reg_val = hisi_pcie_apb_readl(pcie, reg);
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*(u8 __force *) walker = val;
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hisi_pcie_apb_writel(pcie, reg_val, reg);
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} else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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2015-11-27 01:17:05 +08:00
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static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
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{
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u32 val;
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regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
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0x100 * hisi_pcie->port_id, &val);
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return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
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}
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2015-11-27 01:17:05 +08:00
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static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
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{
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u32 val;
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val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF +
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PCIE_SYS_STATE4);
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return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
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}
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static int hisi_pcie_link_up(struct pcie_port *pp)
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{
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
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return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
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}
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2015-10-30 09:02:51 +08:00
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static struct pcie_host_ops hisi_pcie_host_ops = {
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.rd_own_conf = hisi_pcie_cfg_read,
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.wr_own_conf = hisi_pcie_cfg_write,
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.link_up = hisi_pcie_link_up,
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};
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2015-11-25 05:38:07 +08:00
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static int hisi_add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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{
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int ret;
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u32 port_id;
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
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if (of_property_read_u32(pdev->dev.of_node, "port-id", &port_id)) {
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dev_err(&pdev->dev, "failed to read port-id\n");
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return -EINVAL;
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}
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if (port_id > 3) {
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dev_err(&pdev->dev, "Invalid port-id: %d\n", port_id);
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return -EINVAL;
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}
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hisi_pcie->port_id = port_id;
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pp->ops = &hisi_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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2015-11-25 05:38:07 +08:00
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static int hisi_pcie_probe(struct platform_device *pdev)
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{
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struct hisi_pcie *hisi_pcie;
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struct pcie_port *pp;
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const struct of_device_id *match;
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struct resource *reg;
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struct device_driver *driver;
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2015-10-30 09:02:51 +08:00
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int ret;
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hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL);
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if (!hisi_pcie)
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return -ENOMEM;
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pp = &hisi_pcie->pp;
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pp->dev = &pdev->dev;
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driver = (pdev->dev).driver;
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match = of_match_device(driver->of_match_table, &pdev->dev);
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hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
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hisi_pcie->subctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
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if (IS_ERR(hisi_pcie->subctrl)) {
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dev_err(pp->dev, "cannot get subctrl base\n");
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return PTR_ERR(hisi_pcie->subctrl);
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}
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reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
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hisi_pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg);
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if (IS_ERR(hisi_pcie->reg_base)) {
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dev_err(pp->dev, "cannot get rc_dbi base\n");
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return PTR_ERR(hisi_pcie->reg_base);
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}
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hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
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ret = hisi_add_pcie_port(pp, pdev);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, hisi_pcie);
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dev_warn(pp->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
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return 0;
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}
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2015-11-27 01:17:05 +08:00
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static struct pcie_soc_ops hip05_ops = {
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&hisi_pcie_link_up_hip05
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};
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static struct pcie_soc_ops hip06_ops = {
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&hisi_pcie_link_up_hip06
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};
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2015-10-30 09:02:51 +08:00
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static const struct of_device_id hisi_pcie_of_match[] = {
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{
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.compatible = "hisilicon,hip05-pcie",
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.data = (void *) &hip05_ops,
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},
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{
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.compatible = "hisilicon,hip06-pcie",
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.data = (void *) &hip06_ops,
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},
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2015-10-30 09:02:51 +08:00
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{},
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};
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2015-11-27 01:17:05 +08:00
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2015-10-30 09:02:51 +08:00
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MODULE_DEVICE_TABLE(of, hisi_pcie_of_match);
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static struct platform_driver hisi_pcie_driver = {
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.probe = hisi_pcie_probe,
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.driver = {
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.name = "hisi-pcie",
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.of_match_table = hisi_pcie_of_match,
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},
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};
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module_platform_driver(hisi_pcie_driver);
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2015-11-27 01:17:05 +08:00
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MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
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MODULE_AUTHOR("Dacai Zhu <zhudacai@hisilicon.com>");
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MODULE_AUTHOR("Gabriele Paoloni <gabriele.paoloni@huawei.com>");
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MODULE_LICENSE("GPL v2");
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