2010-05-21 09:08:55 +08:00
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#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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2010-12-04 19:30:53 +08:00
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enum {
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RCS = 0x0,
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VCS,
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BCS,
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I915_NUM_RINGS,
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};
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2010-05-21 09:08:55 +08:00
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struct intel_hw_status_page {
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2010-10-27 19:18:21 +08:00
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u32 __iomem *page_addr;
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2010-05-21 09:08:55 +08:00
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unsigned int gfx_addr;
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2010-11-09 03:18:58 +08:00
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struct drm_i915_gem_object *obj;
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2010-05-21 09:08:55 +08:00
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};
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2010-11-09 17:17:32 +08:00
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#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
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2011-01-05 06:22:17 +08:00
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#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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2010-11-09 17:17:32 +08:00
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2011-01-05 06:22:17 +08:00
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#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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2010-11-09 17:17:32 +08:00
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2011-01-05 06:22:17 +08:00
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#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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2010-11-09 17:17:32 +08:00
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2011-01-05 06:22:17 +08:00
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#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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2010-08-02 22:29:44 +08:00
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2011-01-05 06:22:17 +08:00
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
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2011-01-05 01:35:21 +08:00
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2011-01-05 06:22:17 +08:00
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#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
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#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
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#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
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2010-12-04 19:30:53 +08:00
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2010-05-21 09:08:55 +08:00
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struct intel_ring_buffer {
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const char *name;
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2010-09-18 18:02:01 +08:00
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enum intel_ring_id {
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RING_RENDER = 0x1,
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RING_BSD = 0x2,
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2010-10-19 18:19:32 +08:00
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RING_BLT = 0x4,
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2010-09-18 18:02:01 +08:00
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} id;
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2010-08-02 22:24:01 +08:00
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u32 mmio_base;
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2010-05-21 09:08:55 +08:00
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void *virtual_start;
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struct drm_device *dev;
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2010-11-09 03:18:58 +08:00
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struct drm_i915_gem_object *obj;
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2010-05-21 09:08:55 +08:00
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2010-12-09 20:56:37 +08:00
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u32 actual_head;
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u32 head;
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u32 tail;
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2010-09-24 00:45:39 +08:00
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int space;
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2010-10-27 22:11:53 +08:00
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int size;
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2010-12-22 22:04:47 +08:00
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int effective_size;
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2010-05-21 09:08:55 +08:00
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struct intel_hw_status_page status_page;
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2011-01-05 01:35:21 +08:00
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u32 irq_mask;
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2010-10-27 22:27:33 +08:00
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u32 irq_seqno; /* last seq seem at irq time */
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u32 waiting_seqno;
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2010-12-04 19:30:53 +08:00
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u32 sync_seqno[I915_NUM_RINGS-1];
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2010-12-14 00:54:50 +08:00
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atomic_t irq_refcount;
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bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
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2010-12-04 19:30:53 +08:00
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void (*irq_put)(struct intel_ring_buffer *ring);
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2010-05-21 09:08:55 +08:00
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2010-10-27 19:18:21 +08:00
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int (*init)(struct intel_ring_buffer *ring);
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2010-05-21 09:08:55 +08:00
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2010-10-27 19:18:21 +08:00
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void (*write_tail)(struct intel_ring_buffer *ring,
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2010-10-23 00:02:41 +08:00
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u32 value);
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2011-01-05 01:34:02 +08:00
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int __must_check (*flush)(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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2010-10-27 23:11:02 +08:00
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int (*add_request)(struct intel_ring_buffer *ring,
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u32 *seqno);
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2010-10-27 19:18:21 +08:00
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u32 (*get_seqno)(struct intel_ring_buffer *ring);
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int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
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2010-11-30 22:10:25 +08:00
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u32 offset, u32 length);
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2010-11-02 16:31:01 +08:00
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void (*cleanup)(struct intel_ring_buffer *ring);
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2010-05-21 09:08:55 +08:00
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_rendering_seqno
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* List of breadcrumbs associated with GPU requests currently
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* outstanding.
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*/
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struct list_head request_list;
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2010-10-24 19:38:05 +08:00
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/**
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* List of objects currently pending a GPU write flush.
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*
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* All elements on this list will belong to either the
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* active_list or flushing_list, last_rendering_seqno can
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* be used to differentiate between the two elements.
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*/
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struct list_head gpu_write_list;
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2010-09-28 17:07:56 +08:00
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/**
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* Do we have some not yet emitted requests outstanding?
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*/
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2010-11-11 04:40:02 +08:00
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u32 outstanding_lazy_request;
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2010-09-28 17:07:56 +08:00
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2010-05-21 09:08:55 +08:00
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wait_queue_head_t irq_queue;
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drm_local_map_t map;
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2010-11-02 16:31:01 +08:00
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void *private;
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2010-05-21 09:08:55 +08:00
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};
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2010-12-04 19:30:53 +08:00
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static inline u32
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intel_ring_sync_index(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *other)
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{
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int idx;
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/*
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* cs -> 0 = vcs, 1 = bcs
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* vcs -> 0 = bcs, 1 = cs,
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* bcs -> 0 = cs, 1 = vcs.
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*/
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idx = (other - ring) - 1;
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if (idx < 0)
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idx += I915_NUM_RINGS;
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return idx;
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}
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2010-05-21 09:08:55 +08:00
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static inline u32
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intel_read_status_page(struct intel_ring_buffer *ring,
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2010-10-27 19:18:21 +08:00
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int reg)
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2010-05-21 09:08:55 +08:00
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{
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2010-10-27 19:18:21 +08:00
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return ioread32(ring->status_page.page_addr + reg);
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2010-05-21 09:08:55 +08:00
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}
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2010-10-27 19:18:21 +08:00
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void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
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2010-10-27 19:45:26 +08:00
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int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
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int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
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2010-10-27 19:18:21 +08:00
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static inline void intel_ring_emit(struct intel_ring_buffer *ring,
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u32 data)
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2010-08-04 22:18:14 +08:00
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{
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2010-10-27 19:18:21 +08:00
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iowrite32(data, ring->virtual_start + ring->tail);
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2010-08-04 22:18:14 +08:00
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ring->tail += 4;
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}
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2010-10-27 19:18:21 +08:00
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void intel_ring_advance(struct intel_ring_buffer *ring);
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2010-05-21 09:08:55 +08:00
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2010-10-27 19:18:21 +08:00
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u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
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2010-12-04 19:30:53 +08:00
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int intel_ring_sync(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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u32 seqno);
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2010-05-21 09:08:55 +08:00
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2010-09-16 10:43:11 +08:00
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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2010-10-19 18:19:32 +08:00
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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2010-05-21 09:08:55 +08:00
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2010-10-27 19:18:21 +08:00
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
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void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
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2010-09-25 03:20:10 +08:00
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2010-05-21 09:08:55 +08:00
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#endif /* _INTEL_RINGBUFFER_H_ */
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