2018-11-06 20:11:42 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2010-03-02 17:48:55 +08:00
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/*
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2011-06-05 08:38:28 +08:00
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* GPIO interface for Intel Poulsbo SCH
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2010-03-02 17:48:55 +08:00
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*
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* Copyright (c) 2010 CompuLab Ltd
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* Author: Denis Turischev <denis@compulab.co.il>
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*/
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2018-09-04 19:26:25 +08:00
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#include <linux/acpi.h>
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2021-03-17 23:19:28 +08:00
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#include <linux/bitops.h>
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2018-09-04 19:26:25 +08:00
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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2021-03-17 23:19:27 +08:00
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#include <linux/irq.h>
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2010-03-02 17:48:55 +08:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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2011-03-14 18:53:05 +08:00
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#include <linux/pci_ids.h>
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2018-09-04 19:26:25 +08:00
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#include <linux/platform_device.h>
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2021-03-17 23:19:27 +08:00
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#include <linux/types.h>
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2010-03-02 17:48:55 +08:00
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2014-10-21 19:33:56 +08:00
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#define GEN 0x00
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#define GIO 0x04
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#define GLV 0x08
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2021-03-17 23:19:27 +08:00
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#define GTPE 0x0c
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#define GTNE 0x10
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#define GGPE 0x14
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#define GSMI 0x18
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#define GTS 0x1c
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#define CORE_BANK_OFFSET 0x00
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#define RESUME_BANK_OFFSET 0x20
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2014-10-21 19:33:56 +08:00
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2021-03-17 23:19:28 +08:00
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/*
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* iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
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* Document Number: 328195-001
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*/
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#define GPE0E_GPIO 14
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2014-10-21 19:33:56 +08:00
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struct sch_gpio {
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struct gpio_chip chip;
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spinlock_t lock;
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unsigned short iobase;
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unsigned short resume_base;
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2021-03-17 23:19:28 +08:00
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/* GPE handling */
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u32 gpe;
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acpi_gpe_handler gpe_handler;
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2014-10-21 19:33:56 +08:00
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};
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2010-03-02 17:48:55 +08:00
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2020-07-21 22:51:03 +08:00
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static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
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unsigned int reg)
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2010-03-02 17:48:55 +08:00
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{
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2021-03-17 23:19:27 +08:00
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unsigned int base = CORE_BANK_OFFSET;
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2010-03-02 17:48:55 +08:00
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2014-10-21 19:33:56 +08:00
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if (gpio >= sch->resume_base) {
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gpio -= sch->resume_base;
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2021-03-17 23:19:27 +08:00
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base = RESUME_BANK_OFFSET;
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2014-10-21 19:33:56 +08:00
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}
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2010-03-02 17:48:55 +08:00
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2014-10-21 19:33:56 +08:00
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return base + reg + gpio / 8;
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2010-03-02 17:48:55 +08:00
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}
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2020-07-21 22:51:03 +08:00
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static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
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2010-03-02 17:48:55 +08:00
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{
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2014-10-21 19:33:56 +08:00
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if (gpio >= sch->resume_base)
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gpio -= sch->resume_base;
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return gpio % 8;
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2010-03-02 17:48:55 +08:00
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}
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2020-07-21 22:51:03 +08:00
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static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
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2010-03-02 17:48:55 +08:00
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{
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unsigned short offset, bit;
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2015-01-21 18:32:21 +08:00
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u8 reg_val;
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2010-03-02 17:48:55 +08:00
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2015-01-21 18:32:21 +08:00
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offset = sch_gpio_offset(sch, gpio, reg);
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2014-10-21 19:33:56 +08:00
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bit = sch_gpio_bit(sch, gpio);
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2010-03-02 17:48:55 +08:00
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2015-01-21 18:32:21 +08:00
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reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
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2014-04-07 20:20:32 +08:00
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2015-01-21 18:32:21 +08:00
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return reg_val;
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2010-03-02 17:48:55 +08:00
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}
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2020-07-21 22:51:03 +08:00
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static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
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2015-01-21 18:32:21 +08:00
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int val)
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2010-03-02 17:48:55 +08:00
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{
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2013-03-07 05:49:36 +08:00
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unsigned short offset, bit;
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2015-01-21 18:32:21 +08:00
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u8 reg_val;
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2010-03-02 17:48:55 +08:00
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2015-01-21 18:32:21 +08:00
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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2010-03-02 17:48:55 +08:00
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2015-01-21 18:32:21 +08:00
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reg_val = inb(sch->iobase + offset);
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2013-03-07 05:49:36 +08:00
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2015-01-21 18:32:21 +08:00
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if (val)
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outb(reg_val | BIT(bit), sch->iobase + offset);
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else
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outb((reg_val & ~BIT(bit)), sch->iobase + offset);
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}
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2010-03-02 17:48:55 +08:00
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2020-07-21 22:51:03 +08:00
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static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
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2015-01-21 18:32:21 +08:00
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{
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2015-12-07 21:21:49 +08:00
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struct sch_gpio *sch = gpiochip_get_data(gc);
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2021-03-17 23:19:27 +08:00
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unsigned long flags;
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2010-03-02 17:48:55 +08:00
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2021-03-17 23:19:27 +08:00
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spin_lock_irqsave(&sch->lock, flags);
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2016-06-19 02:05:04 +08:00
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sch_gpio_reg_set(sch, gpio_num, GIO, 1);
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2021-03-17 23:19:27 +08:00
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spin_unlock_irqrestore(&sch->lock, flags);
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2010-03-02 17:48:55 +08:00
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return 0;
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}
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2020-07-21 22:51:03 +08:00
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static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
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2010-03-02 17:48:55 +08:00
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{
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2016-06-19 02:05:04 +08:00
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struct sch_gpio *sch = gpiochip_get_data(gc);
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2020-07-21 22:51:04 +08:00
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2016-06-19 02:05:04 +08:00
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return sch_gpio_reg_get(sch, gpio_num, GLV);
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2010-03-02 17:48:55 +08:00
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}
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2020-07-21 22:51:03 +08:00
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static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
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2010-03-02 17:48:55 +08:00
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{
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2015-12-07 21:21:49 +08:00
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struct sch_gpio *sch = gpiochip_get_data(gc);
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2021-03-17 23:19:27 +08:00
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unsigned long flags;
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2010-03-02 17:48:55 +08:00
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2021-03-17 23:19:27 +08:00
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spin_lock_irqsave(&sch->lock, flags);
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2016-06-19 02:05:04 +08:00
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sch_gpio_reg_set(sch, gpio_num, GLV, val);
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2021-03-17 23:19:27 +08:00
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spin_unlock_irqrestore(&sch->lock, flags);
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2010-03-02 17:48:55 +08:00
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}
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2020-07-21 22:51:03 +08:00
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static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
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2014-10-21 19:33:56 +08:00
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int val)
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2010-03-02 17:48:55 +08:00
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{
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2015-12-07 21:21:49 +08:00
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struct sch_gpio *sch = gpiochip_get_data(gc);
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2021-03-17 23:19:27 +08:00
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unsigned long flags;
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2010-03-02 17:48:55 +08:00
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2021-03-17 23:19:27 +08:00
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spin_lock_irqsave(&sch->lock, flags);
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2016-06-19 02:05:04 +08:00
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sch_gpio_reg_set(sch, gpio_num, GIO, 0);
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2021-03-17 23:19:27 +08:00
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spin_unlock_irqrestore(&sch->lock, flags);
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2014-04-07 20:20:32 +08:00
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/*
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2014-10-21 19:33:56 +08:00
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* according to the datasheet, writing to the level register has no
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* effect when GPIO is programmed as input.
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2021-12-12 11:11:08 +08:00
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* Actually the level register is read-only when configured as input.
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2014-10-21 19:33:56 +08:00
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* Thus presetting the output level before switching to output is _NOT_ possible.
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* Hence we set the level after configuring the GPIO as output.
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* But we cannot prevent a short low pulse if direction is set to high
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* and an external pull-up is connected.
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*/
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sch_gpio_set(gc, gpio_num, val);
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2010-03-02 17:48:55 +08:00
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return 0;
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}
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2020-07-21 22:51:03 +08:00
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static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
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2018-06-27 16:39:31 +08:00
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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2019-11-06 16:54:12 +08:00
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if (sch_gpio_reg_get(sch, gpio_num, GIO))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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2018-06-27 16:39:31 +08:00
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}
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2016-09-11 20:14:37 +08:00
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static const struct gpio_chip sch_gpio_chip = {
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2014-10-21 19:33:56 +08:00
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.label = "sch_gpio",
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2010-03-02 17:48:55 +08:00
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.owner = THIS_MODULE,
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2014-10-21 19:33:56 +08:00
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.direction_input = sch_gpio_direction_in,
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.get = sch_gpio_get,
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.direction_output = sch_gpio_direction_out,
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.set = sch_gpio_set,
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2018-06-27 16:39:31 +08:00
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.get_direction = sch_gpio_get_direction,
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2010-03-02 17:48:55 +08:00
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};
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2021-03-17 23:19:27 +08:00
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static int sch_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sch_gpio *sch = gpiochip_get_data(gc);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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unsigned long flags;
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int rising, falling;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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rising = 1;
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falling = 0;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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rising = 0;
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falling = 1;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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rising = 1;
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falling = 1;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
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sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
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irq_set_handler_locked(d, handle_edge_irq);
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spin_unlock_irqrestore(&sch->lock, flags);
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return 0;
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}
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static void sch_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sch_gpio *sch = gpiochip_get_data(gc);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GTS, 1);
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spin_unlock_irqrestore(&sch->lock, flags);
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}
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2022-06-01 23:36:56 +08:00
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static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
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2021-03-17 23:19:27 +08:00
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{
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struct sch_gpio *sch = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&sch->lock, flags);
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sch_gpio_reg_set(sch, gpio_num, GGPE, val);
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spin_unlock_irqrestore(&sch->lock, flags);
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}
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static void sch_irq_mask(struct irq_data *d)
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{
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2022-06-01 23:36:56 +08:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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sch_irq_mask_unmask(gc, gpio_num, 0);
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gpiochip_disable_irq(gc, gpio_num);
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2021-03-17 23:19:27 +08:00
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}
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static void sch_irq_unmask(struct irq_data *d)
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{
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2022-06-01 23:36:56 +08:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t gpio_num = irqd_to_hwirq(d);
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gpiochip_enable_irq(gc, gpio_num);
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sch_irq_mask_unmask(gc, gpio_num, 1);
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2021-03-17 23:19:27 +08:00
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}
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2022-06-01 23:36:56 +08:00
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static const struct irq_chip sch_irqchip = {
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.name = "sch_gpio",
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.irq_ack = sch_irq_ack,
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.irq_mask = sch_irq_mask,
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.irq_unmask = sch_irq_unmask,
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.irq_set_type = sch_irq_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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2021-03-17 23:19:28 +08:00
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static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
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{
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struct sch_gpio *sch = context;
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struct gpio_chip *gc = &sch->chip;
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unsigned long core_status, resume_status;
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unsigned long pending;
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unsigned long flags;
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int offset;
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u32 ret;
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spin_lock_irqsave(&sch->lock, flags);
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core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
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resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
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spin_unlock_irqrestore(&sch->lock, flags);
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pending = (resume_status << sch->resume_base) | core_status;
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for_each_set_bit(offset, &pending, sch->chip.ngpio)
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2021-05-05 00:42:18 +08:00
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generic_handle_domain_irq(gc->irq.domain, offset);
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2021-03-17 23:19:28 +08:00
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/* Set returning value depending on whether we handled an interrupt */
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ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
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/* Acknowledge GPE to ACPICA */
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ret |= ACPI_REENABLE_GPE;
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return ret;
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}
|
|
|
|
|
|
|
|
static void sch_gpio_remove_gpe_handler(void *data)
|
|
|
|
{
|
|
|
|
struct sch_gpio *sch = data;
|
|
|
|
|
|
|
|
acpi_disable_gpe(NULL, sch->gpe);
|
|
|
|
acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
|
|
|
|
{
|
|
|
|
struct device *dev = sch->chip.parent;
|
|
|
|
acpi_status status;
|
|
|
|
|
|
|
|
status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
|
|
|
|
sch->gpe_handler, sch);
|
|
|
|
if (ACPI_FAILURE(status)) {
|
|
|
|
dev_err(dev, "Failed to install GPE handler for %u: %s\n",
|
|
|
|
sch->gpe, acpi_format_exception(status));
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
status = acpi_enable_gpe(NULL, sch->gpe);
|
|
|
|
if (ACPI_FAILURE(status)) {
|
|
|
|
dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
|
|
|
|
sch->gpe, acpi_format_exception(status));
|
|
|
|
acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
|
|
|
|
}
|
|
|
|
|
2012-11-20 02:22:34 +08:00
|
|
|
static int sch_gpio_probe(struct platform_device *pdev)
|
2010-03-02 17:48:55 +08:00
|
|
|
{
|
2021-03-17 23:19:27 +08:00
|
|
|
struct gpio_irq_chip *girq;
|
2014-10-21 19:33:56 +08:00
|
|
|
struct sch_gpio *sch;
|
2010-03-02 17:48:55 +08:00
|
|
|
struct resource *res;
|
2021-03-17 23:19:28 +08:00
|
|
|
int ret;
|
2011-03-14 18:53:05 +08:00
|
|
|
|
2014-10-21 19:33:56 +08:00
|
|
|
sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
|
|
|
|
if (!sch)
|
|
|
|
return -ENOMEM;
|
2010-03-02 17:48:55 +08:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
|
|
|
if (!res)
|
|
|
|
return -EBUSY;
|
|
|
|
|
2014-10-21 19:33:56 +08:00
|
|
|
if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
|
|
|
|
pdev->name))
|
2010-03-02 17:48:55 +08:00
|
|
|
return -EBUSY;
|
|
|
|
|
2014-10-21 19:33:56 +08:00
|
|
|
spin_lock_init(&sch->lock);
|
|
|
|
sch->iobase = res->start;
|
|
|
|
sch->chip = sch_gpio_chip;
|
|
|
|
sch->chip.label = dev_name(&pdev->dev);
|
2015-11-04 16:56:26 +08:00
|
|
|
sch->chip.parent = &pdev->dev;
|
2010-03-02 17:48:55 +08:00
|
|
|
|
2014-10-21 19:33:56 +08:00
|
|
|
switch (pdev->id) {
|
2013-03-20 20:16:00 +08:00
|
|
|
case PCI_DEVICE_ID_INTEL_SCH_LPC:
|
2014-10-21 19:33:56 +08:00
|
|
|
sch->resume_base = 10;
|
|
|
|
sch->chip.ngpio = 14;
|
|
|
|
|
2013-03-20 20:16:00 +08:00
|
|
|
/*
|
|
|
|
* GPIO[6:0] enabled by default
|
|
|
|
* GPIO7 is configured by the CMC as SLPIOVR
|
|
|
|
* Enable GPIO[9:8] core powered gpios explicitly
|
|
|
|
*/
|
2016-06-19 02:05:04 +08:00
|
|
|
sch_gpio_reg_set(sch, 8, GEN, 1);
|
|
|
|
sch_gpio_reg_set(sch, 9, GEN, 1);
|
2013-03-20 20:16:00 +08:00
|
|
|
/*
|
|
|
|
* SUS_GPIO[2:0] enabled by default
|
|
|
|
* Enable SUS_GPIO3 resume powered gpio explicitly
|
|
|
|
*/
|
2016-06-19 02:05:04 +08:00
|
|
|
sch_gpio_reg_set(sch, 13, GEN, 1);
|
2013-03-20 20:16:00 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_DEVICE_ID_INTEL_ITC_LPC:
|
2014-10-21 19:33:56 +08:00
|
|
|
sch->resume_base = 5;
|
|
|
|
sch->chip.ngpio = 14;
|
2013-03-20 20:16:00 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
|
2014-10-21 19:33:56 +08:00
|
|
|
sch->resume_base = 21;
|
|
|
|
sch->chip.ngpio = 30;
|
2013-03-20 20:16:00 +08:00
|
|
|
break;
|
|
|
|
|
2014-12-08 17:38:10 +08:00
|
|
|
case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
|
|
|
|
sch->resume_base = 2;
|
|
|
|
sch->chip.ngpio = 8;
|
|
|
|
break;
|
|
|
|
|
2013-03-20 20:16:00 +08:00
|
|
|
default:
|
2014-10-21 19:33:56 +08:00
|
|
|
return -ENODEV;
|
2011-03-14 18:53:05 +08:00
|
|
|
}
|
2010-03-02 17:48:55 +08:00
|
|
|
|
2014-10-21 19:33:56 +08:00
|
|
|
platform_set_drvdata(pdev, sch);
|
2010-03-02 17:48:55 +08:00
|
|
|
|
2021-03-17 23:19:27 +08:00
|
|
|
girq = &sch->chip.irq;
|
2022-06-01 23:36:56 +08:00
|
|
|
gpio_irq_chip_set_chip(girq, &sch_irqchip);
|
2021-03-17 23:19:27 +08:00
|
|
|
girq->num_parents = 0;
|
|
|
|
girq->parents = NULL;
|
|
|
|
girq->parent_handler = NULL;
|
|
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
|
|
girq->handler = handle_bad_irq;
|
|
|
|
|
2021-03-17 23:19:28 +08:00
|
|
|
/* GPE setup is optional */
|
|
|
|
sch->gpe = GPE0E_GPIO;
|
|
|
|
sch->gpe_handler = sch_gpio_gpe_handler;
|
|
|
|
|
|
|
|
ret = sch_gpio_install_gpe_handler(sch);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(&pdev->dev, "Can't setup GPE, no IRQ support\n");
|
|
|
|
|
2016-02-22 20:13:28 +08:00
|
|
|
return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
|
2010-03-02 17:48:55 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver sch_gpio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "sch_gpio",
|
|
|
|
},
|
|
|
|
.probe = sch_gpio_probe,
|
|
|
|
};
|
|
|
|
|
2011-12-08 00:24:00 +08:00
|
|
|
module_platform_driver(sch_gpio_driver);
|
2010-03-02 17:48:55 +08:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
|
|
|
|
MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
|
2018-11-06 20:11:42 +08:00
|
|
|
MODULE_LICENSE("GPL v2");
|
2010-03-02 17:48:55 +08:00
|
|
|
MODULE_ALIAS("platform:sch_gpio");
|