License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
2010-04-14 06:29:51 +08:00
|
|
|
/*
|
|
|
|
|
* Common Intel AGPGART and GTT definitions.
|
|
|
|
|
*/
|
2010-08-27 11:06:48 +08:00
|
|
|
#ifndef _INTEL_AGP_H
|
|
|
|
|
#define _INTEL_AGP_H
|
2010-04-14 06:29:51 +08:00
|
|
|
|
|
|
|
|
/* Intel registers */
|
|
|
|
|
#define INTEL_APSIZE 0xb4
|
|
|
|
|
#define INTEL_ATTBASE 0xb8
|
|
|
|
|
#define INTEL_AGPCTRL 0xb0
|
|
|
|
|
#define INTEL_NBXCFG 0x50
|
|
|
|
|
#define INTEL_ERRSTS 0x91
|
|
|
|
|
|
|
|
|
|
/* Intel i830 registers */
|
|
|
|
|
#define I830_GMCH_CTRL 0x52
|
|
|
|
|
#define I830_GMCH_ENABLED 0x4
|
|
|
|
|
#define I830_GMCH_MEM_MASK 0x1
|
|
|
|
|
#define I830_GMCH_MEM_64M 0x1
|
|
|
|
|
#define I830_GMCH_MEM_128M 0
|
|
|
|
|
#define I830_GMCH_GMS_MASK 0x70
|
|
|
|
|
#define I830_GMCH_GMS_DISABLED 0x00
|
|
|
|
|
#define I830_GMCH_GMS_LOCAL 0x10
|
|
|
|
|
#define I830_GMCH_GMS_STOLEN_512 0x20
|
|
|
|
|
#define I830_GMCH_GMS_STOLEN_1024 0x30
|
|
|
|
|
#define I830_GMCH_GMS_STOLEN_8192 0x40
|
|
|
|
|
#define I830_RDRAM_CHANNEL_TYPE 0x03010
|
|
|
|
|
#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
|
|
|
|
|
#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
|
|
|
|
|
|
|
|
|
|
/* This one is for I830MP w. an external graphic card */
|
|
|
|
|
#define INTEL_I830_ERRSTS 0x92
|
|
|
|
|
|
|
|
|
|
/* Intel 855GM/852GM registers */
|
|
|
|
|
#define I855_GMCH_GMS_MASK 0xF0
|
|
|
|
|
#define I855_GMCH_GMS_STOLEN_0M 0x0
|
|
|
|
|
#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
|
|
|
|
|
#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
|
|
|
|
|
#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
|
|
|
|
|
#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
|
|
|
|
|
#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
|
|
|
|
|
#define I85X_CAPID 0x44
|
|
|
|
|
#define I85X_VARIANT_MASK 0x7
|
|
|
|
|
#define I85X_VARIANT_SHIFT 5
|
|
|
|
|
#define I855_GME 0x0
|
|
|
|
|
#define I855_GM 0x4
|
|
|
|
|
#define I852_GME 0x2
|
|
|
|
|
#define I852_GM 0x5
|
|
|
|
|
|
|
|
|
|
/* Intel i845 registers */
|
|
|
|
|
#define INTEL_I845_AGPM 0x51
|
|
|
|
|
#define INTEL_I845_ERRSTS 0xc8
|
|
|
|
|
|
|
|
|
|
/* Intel i860 registers */
|
|
|
|
|
#define INTEL_I860_MCHCFG 0x50
|
|
|
|
|
#define INTEL_I860_ERRSTS 0xc8
|
|
|
|
|
|
|
|
|
|
/* Intel i810 registers */
|
2014-01-04 09:28:06 +08:00
|
|
|
#define I810_GMADR_BAR 0
|
2014-01-04 09:28:31 +08:00
|
|
|
#define I810_MMADR_BAR 1
|
2010-04-14 06:29:51 +08:00
|
|
|
#define I810_PTE_BASE 0x10000
|
|
|
|
|
#define I810_PTE_MAIN_UNCACHED 0x00000000
|
|
|
|
|
#define I810_PTE_LOCAL 0x00000002
|
|
|
|
|
#define I810_PTE_VALID 0x00000001
|
|
|
|
|
#define I830_PTE_SYSTEM_CACHED 0x00000006
|
2010-07-10 01:45:17 +08:00
|
|
|
|
2010-04-14 06:29:51 +08:00
|
|
|
#define I810_SMRAM_MISCC 0x70
|
|
|
|
|
#define I810_GFX_MEM_WIN_SIZE 0x00010000
|
|
|
|
|
#define I810_GFX_MEM_WIN_32M 0x00010000
|
|
|
|
|
#define I810_GMS 0x000000c0
|
|
|
|
|
#define I810_GMS_DISABLE 0x00000000
|
|
|
|
|
#define I810_PGETBL_CTL 0x2020
|
|
|
|
|
#define I810_PGETBL_ENABLED 0x00000001
|
2010-09-25 00:25:59 +08:00
|
|
|
/* Note: PGETBL_CTL2 has a different offset on G33. */
|
|
|
|
|
#define I965_PGETBL_CTL2 0x20c4
|
2010-04-14 06:29:51 +08:00
|
|
|
#define I965_PGETBL_SIZE_MASK 0x0000000e
|
|
|
|
|
#define I965_PGETBL_SIZE_512KB (0 << 1)
|
|
|
|
|
#define I965_PGETBL_SIZE_256KB (1 << 1)
|
|
|
|
|
#define I965_PGETBL_SIZE_128KB (2 << 1)
|
|
|
|
|
#define I965_PGETBL_SIZE_1MB (3 << 1)
|
|
|
|
|
#define I965_PGETBL_SIZE_2MB (4 << 1)
|
|
|
|
|
#define I965_PGETBL_SIZE_1_5MB (5 << 1)
|
2010-09-25 00:25:59 +08:00
|
|
|
#define G33_GMCH_SIZE_MASK (3 << 8)
|
|
|
|
|
#define G33_GMCH_SIZE_1M (1 << 8)
|
|
|
|
|
#define G33_GMCH_SIZE_2M (2 << 8)
|
|
|
|
|
#define G4x_GMCH_SIZE_MASK (0xf << 8)
|
|
|
|
|
#define G4x_GMCH_SIZE_1M (0x1 << 8)
|
|
|
|
|
#define G4x_GMCH_SIZE_2M (0x3 << 8)
|
2011-07-13 06:38:18 +08:00
|
|
|
#define G4x_GMCH_SIZE_VT_EN (0x8 << 8)
|
|
|
|
|
#define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
|
|
|
|
|
#define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
|
|
|
|
|
#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
|
2010-04-14 06:29:51 +08:00
|
|
|
|
2010-12-23 18:40:38 +08:00
|
|
|
#define GFX_FLSH_CNTL 0x2170 /* 915+ */
|
|
|
|
|
|
2010-04-14 06:29:51 +08:00
|
|
|
#define I810_DRAM_CTL 0x3000
|
|
|
|
|
#define I810_DRAM_ROW_0 0x00000001
|
|
|
|
|
#define I810_DRAM_ROW_0_SDRAM 0x00000001
|
|
|
|
|
|
|
|
|
|
/* Intel 815 register */
|
|
|
|
|
#define INTEL_815_APCONT 0x51
|
|
|
|
|
#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
|
|
|
|
|
|
|
|
|
|
/* Intel i820 registers */
|
|
|
|
|
#define INTEL_I820_RDCR 0x51
|
|
|
|
|
#define INTEL_I820_ERRSTS 0xc8
|
|
|
|
|
|
|
|
|
|
/* Intel i840 registers */
|
|
|
|
|
#define INTEL_I840_MCHCFG 0x50
|
|
|
|
|
#define INTEL_I840_ERRSTS 0xc8
|
|
|
|
|
|
|
|
|
|
/* Intel i850 registers */
|
|
|
|
|
#define INTEL_I850_MCHCFG 0x50
|
|
|
|
|
#define INTEL_I850_ERRSTS 0xc8
|
|
|
|
|
|
|
|
|
|
/* intel 915G registers */
|
2014-01-04 09:28:06 +08:00
|
|
|
#define I915_GMADR_BAR 2
|
2014-01-04 09:28:31 +08:00
|
|
|
#define I915_MMADR_BAR 0
|
2014-01-04 09:29:00 +08:00
|
|
|
#define I915_PTE_BAR 3
|
2010-04-14 06:29:51 +08:00
|
|
|
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
|
|
|
|
|
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
|
|
|
|
|
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
|
|
|
|
|
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
|
|
|
|
|
#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
|
|
|
|
|
#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
|
|
|
|
|
#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
|
|
|
|
|
#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
|
|
|
|
|
|
|
|
|
|
#define I915_IFPADDR 0x60
|
2010-12-22 19:37:09 +08:00
|
|
|
#define I830_HIC 0x70
|
2010-04-14 06:29:51 +08:00
|
|
|
|
|
|
|
|
/* Intel 965G registers */
|
|
|
|
|
#define I965_MSAC 0x62
|
|
|
|
|
#define I965_IFPADDR 0x70
|
|
|
|
|
|
|
|
|
|
/* Intel 7505 registers */
|
|
|
|
|
#define INTEL_I7505_APSIZE 0x74
|
|
|
|
|
#define INTEL_I7505_NCAPID 0x60
|
|
|
|
|
#define INTEL_I7505_NISTAT 0x6c
|
|
|
|
|
#define INTEL_I7505_ATTBASE 0x78
|
|
|
|
|
#define INTEL_I7505_ERRSTS 0x42
|
|
|
|
|
#define INTEL_I7505_AGPCTRL 0x70
|
|
|
|
|
#define INTEL_I7505_MCHCFG 0x50
|
|
|
|
|
|
|
|
|
|
/* pci devices ids */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
|
2010-09-17 15:22:30 +08:00
|
|
|
#define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92
|
2010-04-14 06:29:51 +08:00
|
|
|
#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
|
2012-06-06 22:59:06 +08:00
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069
|
2010-04-14 06:29:51 +08:00
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
|
|
|
|
|
|
2010-08-27 11:06:48 +08:00
|
|
|
#endif
|