2018-11-14 02:14:04 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* FPGA Manager Driver for Intel Stratix10 SoC
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*
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* Copyright (C) 2018 Intel Corporation
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*/
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#include <linux/completion.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/firmware/intel/stratix10-svc-client.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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/*
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* FPGA programming requires a higher level of privilege (EL3), per the SoC
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* design.
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*/
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#define NUM_SVC_BUFS 4
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#define SVC_BUF_SIZE SZ_512K
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/* Indicates buffer is in use if set */
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#define SVC_BUF_LOCK 0
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#define S10_BUFFER_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_BUFFER_TIMEOUT_MS))
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#define S10_RECONFIG_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_REQUEST_TIMEOUT_MS))
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/*
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* struct s10_svc_buf
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* buf: virtual address of buf provided by service layer
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* lock: locked if buffer is in use
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*/
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struct s10_svc_buf {
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char *buf;
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unsigned long lock;
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};
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struct s10_priv {
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struct stratix10_svc_chan *chan;
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struct stratix10_svc_client client;
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struct completion status_return_completion;
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struct s10_svc_buf svc_bufs[NUM_SVC_BUFS];
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unsigned long status;
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};
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static int s10_svc_send_msg(struct s10_priv *priv,
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enum stratix10_svc_command_code command,
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void *payload, u32 payload_length)
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{
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struct stratix10_svc_chan *chan = priv->chan;
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struct device *dev = priv->client.dev;
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struct stratix10_svc_client_msg msg;
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int ret;
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dev_dbg(dev, "%s cmd=%d payload=%p length=%d\n",
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__func__, command, payload, payload_length);
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msg.command = command;
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msg.payload = payload;
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msg.payload_length = payload_length;
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ret = stratix10_svc_send(chan, &msg);
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dev_dbg(dev, "stratix10_svc_send returned status %d\n", ret);
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return ret;
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}
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/*
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* Free buffers allocated from the service layer's pool that are not in use.
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* Return true when all buffers are freed.
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*/
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static bool s10_free_buffers(struct fpga_manager *mgr)
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{
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struct s10_priv *priv = mgr->priv;
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uint num_free = 0;
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uint i;
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for (i = 0; i < NUM_SVC_BUFS; i++) {
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if (!priv->svc_bufs[i].buf) {
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num_free++;
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continue;
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}
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if (!test_and_set_bit_lock(SVC_BUF_LOCK,
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&priv->svc_bufs[i].lock)) {
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stratix10_svc_free_memory(priv->chan,
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priv->svc_bufs[i].buf);
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priv->svc_bufs[i].buf = NULL;
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num_free++;
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}
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}
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return num_free == NUM_SVC_BUFS;
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}
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/*
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* Returns count of how many buffers are not in use.
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*/
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static uint s10_free_buffer_count(struct fpga_manager *mgr)
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{
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struct s10_priv *priv = mgr->priv;
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uint num_free = 0;
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uint i;
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for (i = 0; i < NUM_SVC_BUFS; i++)
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if (!priv->svc_bufs[i].buf)
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num_free++;
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return num_free;
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}
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/*
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* s10_unlock_bufs
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* Given the returned buffer address, match that address to our buffer struct
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* and unlock that buffer. This marks it as available to be refilled and sent
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* (or freed).
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* priv: private data
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* kaddr: kernel address of buffer that was returned from service layer
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*/
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static void s10_unlock_bufs(struct s10_priv *priv, void *kaddr)
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{
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uint i;
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if (!kaddr)
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return;
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for (i = 0; i < NUM_SVC_BUFS; i++)
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if (priv->svc_bufs[i].buf == kaddr) {
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clear_bit_unlock(SVC_BUF_LOCK,
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&priv->svc_bufs[i].lock);
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return;
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}
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WARN(1, "Unknown buffer returned from service layer %p\n", kaddr);
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}
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/*
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* s10_receive_callback - callback for service layer to use to provide client
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* (this driver) messages received through the mailbox.
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* client: service layer client struct
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* data: message from service layer
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*/
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static void s10_receive_callback(struct stratix10_svc_client *client,
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struct stratix10_svc_cb_data *data)
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{
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struct s10_priv *priv = client->priv;
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u32 status;
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int i;
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WARN_ONCE(!data, "%s: stratix10_svc_rc_data = NULL", __func__);
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status = data->status;
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/*
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* Here we set status bits as we receive them. Elsewhere, we always use
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* test_and_clear_bit() to check status in priv->status
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*/
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2020-04-15 04:47:54 +08:00
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for (i = 0; i <= SVC_STATUS_ERROR; i++)
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2018-11-14 02:14:04 +08:00
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if (status & (1 << i))
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set_bit(i, &priv->status);
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2020-04-15 04:47:54 +08:00
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if (status & BIT(SVC_STATUS_BUFFER_DONE)) {
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2018-11-14 02:14:04 +08:00
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s10_unlock_bufs(priv, data->kaddr1);
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s10_unlock_bufs(priv, data->kaddr2);
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s10_unlock_bufs(priv, data->kaddr3);
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}
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complete(&priv->status_return_completion);
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}
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/*
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* s10_ops_write_init - prepare for FPGA reconfiguration by requesting
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* partial reconfig and allocating buffers from the service layer.
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*/
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static int s10_ops_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct s10_priv *priv = mgr->priv;
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struct device *dev = priv->client.dev;
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struct stratix10_svc_command_config_type ctype;
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char *kbuf;
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uint i;
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int ret;
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ctype.flags = 0;
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if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
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dev_dbg(dev, "Requesting partial reconfiguration.\n");
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ctype.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
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} else {
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dev_dbg(dev, "Requesting full reconfiguration.\n");
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}
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reinit_completion(&priv->status_return_completion);
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ret = s10_svc_send_msg(priv, COMMAND_RECONFIG,
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&ctype, sizeof(ctype));
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if (ret < 0)
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goto init_done;
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ret = wait_for_completion_interruptible_timeout(
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&priv->status_return_completion, S10_RECONFIG_TIMEOUT);
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if (!ret) {
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dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n");
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ret = -ETIMEDOUT;
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goto init_done;
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}
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if (ret < 0) {
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dev_err(dev, "error (%d) waiting for RECONFIG_REQUEST\n", ret);
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goto init_done;
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}
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ret = 0;
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2020-04-15 04:47:54 +08:00
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if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) {
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2018-11-14 02:14:04 +08:00
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ret = -ETIMEDOUT;
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goto init_done;
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}
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/* Allocate buffers from the service layer's pool. */
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for (i = 0; i < NUM_SVC_BUFS; i++) {
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kbuf = stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE);
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if (!kbuf) {
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s10_free_buffers(mgr);
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ret = -ENOMEM;
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goto init_done;
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}
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priv->svc_bufs[i].buf = kbuf;
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priv->svc_bufs[i].lock = 0;
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}
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init_done:
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stratix10_svc_done(priv->chan);
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return ret;
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}
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/*
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* s10_send_buf - send a buffer to the service layer queue
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* mgr: fpga manager struct
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* buf: fpga image buffer
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* count: size of buf in bytes
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* Returns # of bytes transferred or -ENOBUFS if the all the buffers are in use
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* or if the service queue is full. Never returns 0.
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*/
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static int s10_send_buf(struct fpga_manager *mgr, const char *buf, size_t count)
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{
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struct s10_priv *priv = mgr->priv;
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struct device *dev = priv->client.dev;
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void *svc_buf;
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size_t xfer_sz;
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int ret;
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uint i;
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/* get/lock a buffer that that's not being used */
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for (i = 0; i < NUM_SVC_BUFS; i++)
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if (!test_and_set_bit_lock(SVC_BUF_LOCK,
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&priv->svc_bufs[i].lock))
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break;
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if (i == NUM_SVC_BUFS)
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return -ENOBUFS;
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xfer_sz = count < SVC_BUF_SIZE ? count : SVC_BUF_SIZE;
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svc_buf = priv->svc_bufs[i].buf;
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memcpy(svc_buf, buf, xfer_sz);
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ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_DATA_SUBMIT,
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svc_buf, xfer_sz);
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if (ret < 0) {
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dev_err(dev,
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"Error while sending data to service layer (%d)", ret);
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clear_bit_unlock(SVC_BUF_LOCK, &priv->svc_bufs[i].lock);
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return ret;
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}
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return xfer_sz;
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}
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/*
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* Send a FPGA image to privileged layers to write to the FPGA. When done
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* sending, free all service layer buffers we allocated in write_init.
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*/
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static int s10_ops_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct s10_priv *priv = mgr->priv;
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struct device *dev = priv->client.dev;
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long wait_status;
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int sent = 0;
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int ret = 0;
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/*
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* Loop waiting for buffers to be returned. When a buffer is returned,
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* reuse it to send more data or free if if all data has been sent.
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*/
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while (count > 0 || s10_free_buffer_count(mgr) != NUM_SVC_BUFS) {
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reinit_completion(&priv->status_return_completion);
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if (count > 0) {
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sent = s10_send_buf(mgr, buf, count);
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if (sent < 0)
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continue;
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count -= sent;
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buf += sent;
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} else {
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if (s10_free_buffers(mgr))
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return 0;
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ret = s10_svc_send_msg(
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priv, COMMAND_RECONFIG_DATA_CLAIM,
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NULL, 0);
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if (ret < 0)
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break;
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}
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/*
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* If callback hasn't already happened, wait for buffers to be
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* returned from service layer
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*/
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wait_status = 1; /* not timed out */
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if (!priv->status)
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wait_status = wait_for_completion_interruptible_timeout(
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&priv->status_return_completion,
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S10_BUFFER_TIMEOUT);
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2020-04-15 04:47:54 +08:00
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if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) ||
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test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED,
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2018-11-14 02:14:04 +08:00
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&priv->status)) {
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ret = 0;
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continue;
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}
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2020-04-15 04:47:54 +08:00
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if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) {
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dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n");
|
2018-11-14 02:14:04 +08:00
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ret = -EFAULT;
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break;
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}
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if (!wait_status) {
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dev_err(dev, "timeout waiting for svc layer buffers\n");
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ret = -ETIMEDOUT;
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break;
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}
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if (wait_status < 0) {
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ret = wait_status;
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dev_err(dev,
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"error (%d) waiting for svc layer buffers\n",
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ret);
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break;
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}
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}
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if (!s10_free_buffers(mgr))
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dev_err(dev, "%s not all buffers were freed\n", __func__);
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return ret;
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}
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static int s10_ops_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct s10_priv *priv = mgr->priv;
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struct device *dev = priv->client.dev;
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unsigned long timeout;
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int ret;
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timeout = usecs_to_jiffies(info->config_complete_timeout_us);
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do {
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reinit_completion(&priv->status_return_completion);
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ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_STATUS, NULL, 0);
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|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ret = wait_for_completion_interruptible_timeout(
|
|
|
|
&priv->status_return_completion, timeout);
|
|
|
|
if (!ret) {
|
|
|
|
dev_err(dev,
|
|
|
|
"timeout waiting for RECONFIG_COMPLETED\n");
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev,
|
|
|
|
"error (%d) waiting for RECONFIG_COMPLETED\n",
|
|
|
|
ret);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Not error or timeout, so ret is # of jiffies until timeout */
|
|
|
|
timeout = ret;
|
|
|
|
ret = 0;
|
|
|
|
|
2020-04-15 04:47:54 +08:00
|
|
|
if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status))
|
2018-11-14 02:14:04 +08:00
|
|
|
break;
|
|
|
|
|
2020-04-15 04:47:54 +08:00
|
|
|
if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) {
|
|
|
|
dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n");
|
2018-11-14 02:14:04 +08:00
|
|
|
ret = -EFAULT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} while (1);
|
|
|
|
|
|
|
|
stratix10_svc_done(priv->chan);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum fpga_mgr_states s10_ops_state(struct fpga_manager *mgr)
|
|
|
|
{
|
|
|
|
return FPGA_MGR_STATE_UNKNOWN;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct fpga_manager_ops s10_ops = {
|
|
|
|
.state = s10_ops_state,
|
|
|
|
.write_init = s10_ops_write_init,
|
|
|
|
.write = s10_ops_write,
|
|
|
|
.write_complete = s10_ops_write_complete,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int s10_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct s10_priv *priv;
|
|
|
|
struct fpga_manager *mgr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
priv->client.dev = dev;
|
|
|
|
priv->client.receive_cb = s10_receive_callback;
|
|
|
|
priv->client.priv = priv;
|
|
|
|
|
|
|
|
priv->chan = stratix10_svc_request_channel_byname(&priv->client,
|
|
|
|
SVC_CLIENT_FPGA);
|
|
|
|
if (IS_ERR(priv->chan)) {
|
|
|
|
dev_err(dev, "couldn't get service channel (%s)\n",
|
|
|
|
SVC_CLIENT_FPGA);
|
|
|
|
return PTR_ERR(priv->chan);
|
|
|
|
}
|
|
|
|
|
|
|
|
init_completion(&priv->status_return_completion);
|
|
|
|
|
|
|
|
mgr = fpga_mgr_create(dev, "Stratix10 SOC FPGA Manager",
|
|
|
|
&s10_ops, priv);
|
|
|
|
if (!mgr) {
|
|
|
|
dev_err(dev, "unable to create FPGA manager\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto probe_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = fpga_mgr_register(mgr);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "unable to register FPGA manager\n");
|
|
|
|
fpga_mgr_free(mgr);
|
|
|
|
goto probe_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, mgr);
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
probe_err:
|
|
|
|
stratix10_svc_free_channel(priv->chan);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int s10_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct fpga_manager *mgr = platform_get_drvdata(pdev);
|
|
|
|
struct s10_priv *priv = mgr->priv;
|
|
|
|
|
|
|
|
fpga_mgr_unregister(mgr);
|
|
|
|
stratix10_svc_free_channel(priv->chan);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id s10_of_match[] = {
|
2020-02-15 00:00:48 +08:00
|
|
|
{.compatible = "intel,stratix10-soc-fpga-mgr"},
|
|
|
|
{.compatible = "intel,agilex-soc-fpga-mgr"},
|
2018-11-14 02:14:04 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, s10_of_match);
|
|
|
|
|
|
|
|
static struct platform_driver s10_driver = {
|
|
|
|
.probe = s10_probe,
|
|
|
|
.remove = s10_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "Stratix10 SoC FPGA manager",
|
|
|
|
.of_match_table = of_match_ptr(s10_of_match),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init s10_init(void)
|
|
|
|
{
|
|
|
|
struct device_node *fw_np;
|
|
|
|
struct device_node *np;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
fw_np = of_find_node_by_name(NULL, "svc");
|
|
|
|
if (!fw_np)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2019-05-10 05:08:26 +08:00
|
|
|
of_node_get(fw_np);
|
2018-11-14 02:14:04 +08:00
|
|
|
np = of_find_matching_node(fw_np, s10_of_match);
|
2019-05-10 05:08:26 +08:00
|
|
|
if (!np) {
|
|
|
|
of_node_put(fw_np);
|
2018-11-14 02:14:04 +08:00
|
|
|
return -ENODEV;
|
2019-05-10 05:08:26 +08:00
|
|
|
}
|
2018-11-14 02:14:04 +08:00
|
|
|
|
|
|
|
of_node_put(np);
|
|
|
|
ret = of_platform_populate(fw_np, s10_of_match, NULL, NULL);
|
2019-05-10 05:08:26 +08:00
|
|
|
of_node_put(fw_np);
|
2018-11-14 02:14:04 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return platform_driver_register(&s10_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit s10_exit(void)
|
|
|
|
{
|
|
|
|
return platform_driver_unregister(&s10_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(s10_init);
|
|
|
|
module_exit(s10_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
|
|
|
|
MODULE_DESCRIPTION("Intel Stratix 10 SOC FPGA Manager");
|
|
|
|
MODULE_LICENSE("GPL v2");
|