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OpenCloudOS-Kernel/arch/arm/boot/dts/tegra20.dtsi

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ARM: tegra: use #include for all device trees Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as the IDs and flags in GPIO specifiers. Use of those features will increase the readability of the device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-18 06:38:21 +08:00
#include "skeleton.dtsi"
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
/ {
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
aliases {
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartc;
serial3 = &uartd;
serial4 = &uarte;
};
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */
0 67 0x04>; /* mpcore general */
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 28>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x04000000>;
mpe {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 60>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
};
vi {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 100>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
};
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 19>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
};
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 23>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
};
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 21>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
};
gr3d {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 24>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
};
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 27>, <&tegra_car 121>;
clock-names = "disp1", "parent";
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
rgb {
status = "disabled";
};
};
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 26>, <&tegra_car 121>;
clock-names = "disp2", "parent";
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
rgb {
status = "disabled";
};
};
hdmi {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 51>, <&tegra_car 117>;
clock-names = "hdmi", "parent";
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
status = "disabled";
};
tvo {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 102>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
status = "disabled";
};
dsi {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 48>;
ARM: tegra: Add Tegra20 host1x support Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16 05:07:54 +08:00
status = "disabled";
};
};
ARM: tegra: add TWD to device tree This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 04:17:24 +08:00
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
interrupts = <1 13 0x304>;
ARM: Tegra: Add clock entry for smp_twd clock As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-03-02 02:32:24 +08:00
clocks = <&tegra_car 132>;
ARM: tegra: add TWD to device tree This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 04:17:24 +08:00
};
ARM: dt: tegra: remove unnecessary unit addresses DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:17:47 +08:00
intc: interrupt-controller {
arm/tegra: convert tegra20 to GIC devicetree binding Convert tegra20 IRQ intialization to the GIC devicetree binding. Modify the interrupt definitions in the dts files according to Documentation/devicetree/bindings/arm/gic.txt v3 (swarren): * Moved of_irq_init() call into board-dt.c to avoid ifdef'ing it. - Even with a dummy replacement if !CONFIG_OF, the reference from tegra_dt_irq_match[] to gic_of_init() would still have to be ifdef'd - It's plausible that tegra_dt_irq_match[] may need to contain more entries in the future, and defining what they are seems more suitable for board-dt.c than irq.c v2 (swarren): * Removed some stale GIC init code from board-dt.c * Undid some accidental 0x -> 0x0 search/replace. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> [olof: added include of <asm/hardware/gic.h> for compile to pass] Signed-off-by: Olof Johansson <olof@lixom.net>
2011-11-30 09:29:19 +08:00
compatible = "arm,cortex-a9-gic";
ARM: dt: tegra: format regs properties consistently Place each reg "entry" on its own line, and wrap the whole list in <> rather than each individual entry. The convention chosen here is slightly arbitrary, but is not consistent throughout all Tegra files. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:26:03 +08:00
reg = <0x50041000 0x1000
0x50040100 0x0100>;
ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:12:52 +08:00
interrupt-controller;
#interrupt-cells = <3>;
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-15 01:09:16 +08:00
cache-controller {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};
ARM: tegra: define DT bindings for and instantiate timer The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 02:02:31 +08:00
timer@60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
interrupts = <0 0 0x04
0 1 0x04
0 41 0x04
0 42 0x04>;
clocksource: tegra: move to of_clk_get The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-04 21:40:30 +08:00
clocks = <&tegra_car 5>;
ARM: tegra: define DT bindings for and instantiate timer The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 02:02:31 +08:00
};
ARM: tegra: define Tegra20 CAR binding The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 15:46:22 +08:00
tegra_car: clock {
compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
};
ARM: dt: tegra: remove unnecessary unit addresses DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:17:47 +08:00
apbdma: dma {
ARM: dt: tegra: Add Tegra APB DMA device tree binding Document binding, and add the node to tegra*.dtsi. The driver isn't actually instantiated from this node yet, but the I2S binding will rely on being able to refer to the APB DMA node using a phandle. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-12 07:09:54 +08:00
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 34>;
ARM: dt: tegra: Add Tegra APB DMA device tree binding Document binding, and add the node to tegra*.dtsi. The driver isn't actually instantiated from this node yet, but the I2S binding will rely on being able to refer to the APB DMA node using a phandle. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-12 07:09:54 +08:00
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
ahb {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: dt: tegra: remove unnecessary unit addresses DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:17:47 +08:00
gpio: gpio {
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
compatible = "nvidia,tegra20-gpio";
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04>;
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
#gpio-cells = <2>;
gpio-controller;
gpio: tegra: Dynamically allocate IRQ base, and support DT Enhance the driver to dynamically allocate the base IRQ number, and create an IRQ domain for itself. The use of an IRQ domain ensures that any device tree node interrupts properties are correctly parsed. Describe interrupt-related properties in the device tree binding docs, and the contents of "child" node interrupts property. Update tegra*.dtsi to specify the required interrupt-related properties. Finally, remove the definition of TEGRA_GPIO_TO_IRQ; this macro no longer gives correct results since the IRQ numbers for GPIOs are dynamically allocated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-04 16:39:37 +08:00
#interrupt-cells = <2>;
interrupt-controller;
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: dt: tegra: remove unnecessary unit addresses DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:17:47 +08:00
pinmux: pinmux {
arm/dt: Tegra: Add pinmux node to tegra20.dtsi Add a pinmux node to tegra20.dtsi in order to instantiate the future pinmux device. v2: Specify reg property precisely; don't just point at the whole APB_MISC register range. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2011-10-12 06:16:13 +08:00
compatible = "nvidia,tegra20-pinmux";
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
reg = <0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
0x700000a0 0x14 /* Pull-up/down registers */
0x70000868 0xa8>; /* Pad control registers */
arm/dt: Tegra: Add pinmux node to tegra20.dtsi Add a pinmux node to tegra20.dtsi in order to instantiate the future pinmux device. v2: Specify reg property precisely; don't just point at the whole APB_MISC register range. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2011-10-12 06:16:13 +08:00
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
das {
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
ARM: tegra: device tree whitespace cleanup Remove white-space from empty line; triggers checkpatch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:32 +08:00
ASoC: tegra: add ac97 host controller to device tree Add default entry for the AC97 host controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-05 09:18:44 +08:00
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
interrupts = <0 81 0x04>;
nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car 3>;
status = "disabled";
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
interrupts = <0 13 0x04>;
nvidia,dma-request-selector = <&apbdma 2>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 11>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
};
tegra_i2s2: i2s@70002a00 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>;
interrupts = <0 3 0x04>;
nvidia,dma-request-selector = <&apbdma 1>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 18>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
};
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
* driver, the comptible is "nvidia,tegra20-hsuart".
*/
uarta: serial@70006000 {
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 36 0x04>;
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
nvidia,dma-request-selector = <&apbdma 8>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 6>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
uartb: serial@70006040 {
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 37 0x04>;
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
nvidia,dma-request-selector = <&apbdma 9>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 96>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
uartc: serial@70006200 {
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 46 0x04>;
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
nvidia,dma-request-selector = <&apbdma 10>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 55>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
uartd: serial@70006300 {
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 90 0x04>;
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
nvidia,dma-request-selector = <&apbdma 19>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 65>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
uarte: serial@70006400 {
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 91 0x04>;
ARM: tegra: dts: add aliases and DMA requestor for serial controller Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-19 14:31:11 +08:00
nvidia,dma-request-selector = <&apbdma 20>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 66>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: dts: Add pwm label PWM devices can be referenced in the DT by phandle and per-chip index. In order for this to work properly, the PWM controller needs to have a label attached to it. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 23:06:05 +08:00
pwm: pwm {
pwm: tegra: Add device tree support Add auxdata to instantiate the PWFM controller from a device tree, include the corresponding nodes in the dtsi files for Tegra 20 and Tegra 30 and add binding documentation. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2011-12-21 15:04:13 +08:00
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 17>;
ARM: tegra: fix the status of PWM DT nodes We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: Andrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-13 07:40:51 +08:00
status = "disabled";
pwm: tegra: Add device tree support Add auxdata to instantiate the PWFM controller from a device tree, include the corresponding nodes in the dtsi files for Tegra 20 and Tegra 30 and add binding documentation. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2011-12-21 15:04:13 +08:00
};
ARM: tegra: define DT bindings for and instantiate RTC The Tegra RTC maintains seconds and milliseconds counters, and five alarm registers. The alarms and other interrupts may wake the system from low-power state. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 02:13:16 +08:00
rtc {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
clocksource: tegra: move to of_clk_get The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-04 21:40:30 +08:00
clocks = <&tegra_car 4>;
ARM: tegra: define DT bindings for and instantiate RTC The Tegra RTC maintains seconds and milliseconds counters, and five alarm registers. The alarms and other interrupts may wake the system from low-power state. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-09-20 02:13:16 +08:00
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:12:52 +08:00
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 12>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: tegra: emc: device tree bindings Device tree bindings for the EMC tables on tegra. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca>
2011-10-13 17:14:55 +08:00
};
ARM: tegra: dts: add sflash controller dt entry Nvidia's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add DT entry for this controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: move sflash node to keep file sorted] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-13 13:03:39 +08:00
spi@7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
interrupts = <0 39 0x04>;
nvidia,dma-request-selector = <&apbdma 11>;
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 43>;
ARM: tegra: dts: add sflash controller dt entry Nvidia's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add DT entry for this controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: move sflash node to keep file sorted] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-13 13:03:39 +08:00
status = "disabled";
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
i2c@7000c400 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:12:52 +08:00
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 54>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
i2c@7000c500 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:12:52 +08:00
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 67>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
i2c@7000d000 {
compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000d000 0x200>;
interrupts = <0 53 0x04>;
ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:12:52 +08:00
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 47>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 15:05:23 +08:00
spi@7000d400 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 41>;
ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 15:05:23 +08:00
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 44>;
ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 15:05:23 +08:00
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra20-slink";
ARM: tegra: fix register address of slink controller Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-03-23 02:35:06 +08:00
reg = <0x7000d800 0x200>;
ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 15:05:23 +08:00
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 46>;
ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 15:05:23 +08:00
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 68>;
ARM: tegra: dts: add slink controller dt entry Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 15:05:23 +08:00
status = "disabled";
};
ARM: tegra: add DT entry for KBC controller NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 21:33:03 +08:00
kbc {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
status = "disabled";
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
ARM: tegra: add clock source of PMC to device trees Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-03 19:31:27 +08:00
clocks = <&tegra_car 110>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
};
ARM: tegra: fix invalid unit-address in tegra*.dtsi Unit addresses, whilst written in hex, don't contain a 0x prefix. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-10-03 03:10:47 +08:00
memory-controller@7000f000 {
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
interrupts = <0 77 0x04>;
};
ARM: dt: tegra20: Rename "gart" to "iommu" Use functional name for DT entry instead of h/w name. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-29 16:30:30 +08:00
iommu {
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
compatible = "nvidia,tegra20-gart";
reg = <0x7000f024 0x00000018 /* controller registers */
0x58000000 0x02000000>; /* GART aperture */
};
ARM: tegra: fix invalid unit-address in tegra*.dtsi Unit addresses, whilst written in hex, don't contain a 0x prefix. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-10-03 03:10:47 +08:00
memory-controller@7000f400 {
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
compatible = "nvidia,tegra20-emc";
reg = <0x7000f400 0x200>;
ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:12:52 +08:00
#address-cells = <1>;
#size-cells = <0>;
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 20 0x04>;
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
phy_type = "utmi";
arm: tegra: dts: Add legacy mode support to Tegra2x USB1 port Tegra's USB1 port supports legacy mode, so mark it as such. Even if we don't use it, we must turn it off in the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-03-07 13:04:33 +08:00
nvidia,has-legacy-mode;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 22>;
ARM: tegra: Add new DT property to USB node. As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-14 04:59:07 +08:00
nvidia,needs-double-reset;
ARM: tegra: add DT nodes for Tegra USB PHY Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 11:30:19 +08:00
nvidia,phy = <&phy1>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
};
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
phy1: usb-phy@c5000000 {
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
compatible = "nvidia,tegra20-usb-phy";
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
phy_type = "utmi";
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
clocks = <&tegra_car 22>,
<&tegra_car 127>,
<&tegra_car 106>,
<&tegra_car 22>;
clock-names = "reg", "pll_u", "timer", "utmi-pads";
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
nvidia,has-legacy-mode;
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
hssync_start_delay = <9>;
idle_wait_delay = <17>;
elastic_limit = <16>;
term_range_adj = <6>;
xcvr_setup = <9>;
xcvr_lsfslew = <1>;
xcvr_lsrslew = <1>;
status = "disabled";
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
};
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 21 0x04>;
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
phy_type = "ulpi";
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 58>;
ARM: tegra: add DT nodes for Tegra USB PHY Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 11:30:19 +08:00
nvidia,phy = <&phy2>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
};
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
phy2: usb-phy@c5004000 {
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
compatible = "nvidia,tegra20-usb-phy";
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
reg = <0xc5004000 0x4000>;
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
phy_type = "ulpi";
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
clocks = <&tegra_car 58>,
<&tegra_car 127>,
<&tegra_car 93>;
clock-names = "reg", "pll_u", "ulpi-link";
status = "disabled";
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
};
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 06:11:38 +08:00
interrupts = <0 97 0x04>;
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
phy_type = "utmi";
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 59>;
ARM: tegra: add DT nodes for Tegra USB PHY Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 11:30:19 +08:00
nvidia,phy = <&phy3>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Stephen Warren <swarren@nvidia.com>
2011-11-04 17:12:39 +08:00
};
ARM: dt: tegra: Add device tree support for AHB Add AHB entry for tegra20/30. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-07 14:43:47 +08:00
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
phy3: usb-phy@c5008000 {
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
compatible = "nvidia,tegra20-usb-phy";
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
phy_type = "utmi";
ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-16 22:12:57 +08:00
clocks = <&tegra_car 59>,
<&tegra_car 127>,
<&tegra_car 106>,
<&tegra_car 22>;
clock-names = "reg", "pll_u", "timer", "utmi-pads";
hssync_start_delay = <9>;
idle_wait_delay = <17>;
elastic_limit = <16>;
term_range_adj = <6>;
xcvr_setup = <9>;
xcvr_lsfslew = <2>;
xcvr_lsrslew = <2>;
status = "disabled";
ARM: tegra: fix sort order of USB PHY nodes The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-07 02:28:33 +08:00
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
interrupts = <0 14 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 14>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: dt: tegra: Add device tree support for AHB Add AHB entry for tegra20/30. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-07 14:43:47 +08:00
};
ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes Add Tegra MC(Memory Controller) nodes for tegra20.dtsi. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-10 05:42:31 +08:00
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
interrupts = <0 15 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 9>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes Add Tegra MC(Memory Controller) nodes for tegra20.dtsi. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-10 05:42:31 +08:00
};
ARM: dt: tegra20.dtsi: Add GART node Add a node for the Tegra20 GART Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-10 05:45:33 +08:00
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
interrupts = <0 19 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 69>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
};
sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
interrupts = <0 31 0x04>;
ARM: tegra: add clock properties to Tegra20 DT Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:01:21 +08:00
clocks = <&tegra_car 15>;
ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled" This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-12 03:09:45 +08:00
status = "disabled";
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
};
ARM: tegra: Add CPU nodes to Tegra20 device tree Add CPU node for Tegra20. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 21:26:55 +08:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-12 07:03:26 +08:00
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 56 0x04
0 57 0x04>;
ARM: dt: tegra20.dtsi: Add GART node Add a node for the Tegra20 GART Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-10 05:45:33 +08:00
};
arm/dt: tegra devicetree support Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-20 07:26:54 +08:00
};