UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenCloudOS-Kernel/arch/arm/mach-bcm/Makefile

58 lines
1.5 KiB
Makefile
Raw Normal View History

Add support for generic BCM SoC chipsets In order to start upstreaming Broadcom SoC support, create a starting hierarchy, arch and dts files. The first support SoC family that is planned is the BCM281XX (BCM11130/11140/11351/28145/28155) family of dual A9 mobile SoC cores. This code is just the skeleton code for get the machine upstreamed. It has been made MULTIPLATFORM compatible. Next steps ---------- Upstream a basic set of drivers - sufficient for a console boot to ramdisk. These will includer timer, gpio, i2c drivers. After this basic set, we will proceed with a more comprehensive set of drivers for the 281XX SoC family. v2 patch mods -------- - Remove l2x0_of_init call as there were problems with the code. A separate patch will be submitted with cache init code - Rename capri files and refs to bcm281xx-based names - Add bcm281xx binding doc - various misc cleanups v3 patch mods ------------- - Remove extra #include lines - Remove remaining references to capri - dt uart chipset string added - cleaned up chip # references v4 patch mods ------------- - swap order of compatible definitions for uart - fix typo v5 patch mods ------------- - Rename bcm281xx to bcm11351 in dts+code, leaving references to bcm281xx only in help+comments. v6 patch mods ------------- - fix typo in uart 'compatible' string Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-11-20 01:46:10 +08:00
#
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC Broadcom Northstar Plus family of SoCs are used for switching control and management applications as well as residential router/gateway applications. The SoC features dual core Cortex A9 ARM CPUs, integrating several peripheral interfaces including multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, SATA and several other IO controllers. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Jon Mason <jonmason@broadcom.com> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-08-27 06:35:28 +08:00
# Copyright (C) 2012-2015 Broadcom Corporation
Add support for generic BCM SoC chipsets In order to start upstreaming Broadcom SoC support, create a starting hierarchy, arch and dts files. The first support SoC family that is planned is the BCM281XX (BCM11130/11140/11351/28145/28155) family of dual A9 mobile SoC cores. This code is just the skeleton code for get the machine upstreamed. It has been made MULTIPLATFORM compatible. Next steps ---------- Upstream a basic set of drivers - sufficient for a console boot to ramdisk. These will includer timer, gpio, i2c drivers. After this basic set, we will proceed with a more comprehensive set of drivers for the 281XX SoC family. v2 patch mods -------- - Remove l2x0_of_init call as there were problems with the code. A separate patch will be submitted with cache init code - Rename capri files and refs to bcm281xx-based names - Add bcm281xx binding doc - various misc cleanups v3 patch mods ------------- - Remove extra #include lines - Remove remaining references to capri - dt uart chipset string added - cleaned up chip # references v4 patch mods ------------- - swap order of compatible definitions for uart - fix typo v5 patch mods ------------- - Rename bcm281xx to bcm11351 in dts+code, leaving references to bcm281xx only in help+comments. v6 patch mods ------------- - fix typo in uart 'compatible' string Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-11-20 01:46:10 +08:00
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation version 2.
#
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
# kind, whether express or implied; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
ARM: cygnus: Initial support for Broadcom Cygnus SoC Adds initial support for the Cygnus SoC based on Broadcom’s iProc series. Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Desmond Liu <desmondl@broadcom.com> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com> Tested-by: Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-08-16 03:52:00 +08:00
# Cygnus
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC Broadcom Northstar Plus family of SoCs are used for switching control and management applications as well as residential router/gateway applications. The SoC features dual core Cortex A9 ARM CPUs, integrating several peripheral interfaces including multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, SATA and several other IO controllers. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Jon Mason <jonmason@broadcom.com> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-08-27 06:35:28 +08:00
# Northstar Plus
ARM: BCM: Add SMP support for Broadcom NSP Add SMP support for Broadcom's Northstar Plus SoC cpu enable method. This changes also consolidates iProc family's - BCM NSP and BCM Kona, platform SMP handling in a common file. Northstar Plus SoC is based on ARM Cortex-A9 revision r3p0 which requires configuration for ARM Errata 764369 for SMP. This change adds the needed configuration option. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-12-02 00:24:08 +08:00
obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
ifeq ($(CONFIG_ARCH_BCM_NSP),y)
obj-$(CONFIG_SMP) += platsmp.o
endif
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC Broadcom Northstar Plus family of SoCs are used for switching control and management applications as well as residential router/gateway applications. The SoC features dual core Cortex A9 ARM CPUs, integrating several peripheral interfaces including multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, SATA and several other IO controllers. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Jon Mason <jonmason@broadcom.com> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-08-27 06:35:28 +08:00
ARM: bcm: clean up config and build targets Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both) Broadcom mobile SoC families. Instead, use that only as a config menu switch, and define specific symbols like ARCH_BCM_281XX to select a particular SoC family. If ARCH_BCM_MOBILE is selected, all of the SoCs will be selected by default, but this way each can be disabled individually as well. Note that BCM281xx and BCM21664 both require the SMC and L2 cache control code, so that code will be built based on ARCH_BCM_MOBILE. Signed-off-by: Alex Elder <elder@linaro.org> [mporter: added ARM: to the description] Signed-off-by: Matt Porter <mporter@linaro.org>
2014-04-15 20:37:19 +08:00
# BCM281XX
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
# BCM21664
obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
ARM: bcm2835: Move to mach-bcm directory Move the bcm2835 board file into the mach-bcm directory. This allows us to get rid of the mach-bcm2835 directory with the associated Kconfig and Makefile. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> [swarren, adjust defconfig so ARCH_BCM2835 still gets enabled] Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-02-21 08:16:11 +08:00
ARM: add SMP support for Broadcom mobile SoCs This patch adds SMP support for BCM281XX and BCM21664 family SoCs. This feature is controlled with a distinct config option such that an SMP-enabled multi-v7 binary can be configured to run these SoCs in uniprocessor mode. Since this SMP functionality is used for multiple Broadcom mobile chip families the config option is called ARCH_BCM_MOBILE_SMP (for lack of a better name). On SoCs of this type, the secondary core is not held in reset on power-on. Instead it loops in a ROM-based holding pen. To release it, one must write into a special register a jump address whose low-order bits have been replaced with a secondary core's id, then trigger an event with SEV. On receipt of an event, the ROM code will examine the register's contents, and if the low-order bits match its cpu id, it will clear them and write the value back to the register just prior to jumping to the address specified. The location of the special register is defined in the device tree using a "secondary-boot-reg" property in a node whose "enable-method" matches. Derived from code originally provided by Ray Jui <rjui@broadcom.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-07-01 06:15:37 +08:00
# BCM281XX and BCM21664 SMP support
ARM: BCM: Add SMP support for Broadcom NSP Add SMP support for Broadcom's Northstar Plus SoC cpu enable method. This changes also consolidates iProc family's - BCM NSP and BCM Kona, platform SMP handling in a common file. Northstar Plus SoC is based on ARM Cortex-A9 revision r3p0 which requires configuration for ARM Errata 764369 for SMP. This change adds the needed configuration option. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-12-02 00:24:08 +08:00
obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
ARM: add SMP support for Broadcom mobile SoCs This patch adds SMP support for BCM281XX and BCM21664 family SoCs. This feature is controlled with a distinct config option such that an SMP-enabled multi-v7 binary can be configured to run these SoCs in uniprocessor mode. Since this SMP functionality is used for multiple Broadcom mobile chip families the config option is called ARCH_BCM_MOBILE_SMP (for lack of a better name). On SoCs of this type, the secondary core is not held in reset on power-on. Instead it loops in a ROM-based holding pen. To release it, one must write into a special register a jump address whose low-order bits have been replaced with a secondary core's id, then trigger an event with SEV. On receipt of an event, the ROM code will examine the register's contents, and if the low-order bits match its cpu id, it will clear them and write the value back to the register just prior to jumping to the address specified. The location of the special register is defined in the device tree using a "secondary-boot-reg" property in a node whose "enable-method" matches. Derived from code originally provided by Ray Jui <rjui@broadcom.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-07-01 06:15:37 +08:00
ARM: bcm: clean up config and build targets Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both) Broadcom mobile SoC families. Instead, use that only as a config menu switch, and define specific symbols like ARCH_BCM_281XX to select a particular SoC family. If ARCH_BCM_MOBILE is selected, all of the SoCs will be selected by default, but this way each can be disabled individually as well. Note that BCM281xx and BCM21664 both require the SMC and L2 cache control code, so that code will be built based on ARCH_BCM_MOBILE. Signed-off-by: Alex Elder <elder@linaro.org> [mporter: added ARM: to the description] Signed-off-by: Matt Porter <mporter@linaro.org>
2014-04-15 20:37:19 +08:00
# BCM281XX and BCM21664 L2 cache control
ARM: bcm: rename "kona.h" and "kona.c" These source files contain only level-2 cache initialization code, so rename them to make that fact more obvious. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-04-22 05:53:11 +08:00
obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
ARM: bcm: config option for l2 cache support Add a new config option ARCH_BCM_MOBILE_L2_CACHE that allows support for level-2 cache to be enabled or disabled at build time for BCM218XX and BCM21664 family SoCs. Build support for SMC only if it's required (currently it's only required for to support level 2 cache control). If arch/arm/mach-bcm/kona.c gets compiled, ARCH_BCM_MOBILE_L2_CACHE must have been selected, which implies CONFIG_CACHE_L2X0 is set. There is therefore no need to check CONFIG_CACHE_L2X0 at the top of kona_l2_cache_init(), so get rid of that check. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-04-22 05:53:07 +08:00
# Support for secure monitor traps
ARM: bcm: use inline assembly for "smc" request Move the code that implements the "smc" call into a C function that uses inline assembly. This allows us to make that function private, and enables us to get rid of "arch/arm/mach-bcm/bcm_kona_smc_asm.S". Rename what had been the "buffer_addr" argument to be "buffer_phys" so it's consistent with other usage in this file. Since it's now easy to do, verify that r12 contains SEC_EXIT_NORMAL upon completion of the SMC. There really isn't a good way to handle the abnormal completion of a secure monitor request. Since "bcm_kona_smc.h" is now only included from C files, eliminate the #ifndef __ASSEMBLY__. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-04-22 05:53:09 +08:00
obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec)
CFLAGS_bcm_kona_smc.o += -Wa,-march=armv7-a+sec -DREQUIRES_SEC
endif
ARM: bcm: clean up config and build targets Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both) Broadcom mobile SoC families. Instead, use that only as a config menu switch, and define specific symbols like ARCH_BCM_281XX to select a particular SoC family. If ARCH_BCM_MOBILE is selected, all of the SoCs will be selected by default, but this way each can be disabled individually as well. Note that BCM281xx and BCM21664 both require the SMC and L2 cache control code, so that code will be built based on ARCH_BCM_MOBILE. Signed-off-by: Alex Elder <elder@linaro.org> [mporter: added ARM: to the description] Signed-off-by: Matt Porter <mporter@linaro.org>
2014-04-15 20:37:19 +08:00
# BCM2835
obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
# BCM5301X
ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU This patch adds support for the BCM5301X/BCM470X SoCs with an ARM CPUs. Currently just booting to a shell is working and nothing else, no Ethernet, wifi, flash, ... I have some pending patches to make Ethernet work for this device. Mostly device tree support for bcma is missing. This SoC is used in small office and home router with Broadcom SoCs it's internal name is Northstar. This code should support the BCM4707, BCM4708, BCM4709, BCM53010, BCM53011 and BCM53012 SoC. It uses one or two ARM Cortex A9 Cores, some highlights are 2 PCIe 2.0 controllers, 4 Gigabit Ethernet MACs and a USB 3.0 host controller. This SoC uses a dual core CPU, but this is currently not implemented. More information about this SoC can be found here: http://www.anandtech.com/show/5925/broadcom-announces-bcm4708x-and-bcm5301x-socs-for-80211ac-routers Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-04 07:01:43 +08:00
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes. This patch adds machine support for the ARM-based Broadcom SoCs. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-01-17 07:00:42 +08:00
ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-02-21 07:53:13 +08:00
# BCM63XXx
ARM: BCM63xx: Add SMP support for BCM63138 Add support for booting the secondary CPU on BCM63138, this involves: - locating the bootlut to write the reset vector - powering up the second CPU when we need to using the DT-supplied PMB references - disabling VFP when enabled such that we can keep having SMP Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-08-15 10:37:45 +08:00
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
obj-y += bcm63xx.o
ARM: BCM63xx: Remove custom secondary_startup function With commit 02b4e2756e01c623cc4dbceae4b07be75252db5b ("ARM: v7 setup function should invalidate L1 cache"), the default secondary_startup function for ARMv7 CPUs does invalidate the L1 cache, which was the sole reason why BCM63xx had to have its own secondary_startup implementation. Now that the secondary_startup takes care of this, we can completely remove that code. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-07-08 09:17:01 +08:00
obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o
ARM: BCM63xx: Add SMP support for BCM63138 Add support for booting the secondary CPU on BCM63138, this involves: - locating the bootlut to write the reset vector - powering up the second CPU when we need to using the DT-supplied PMB references - disabling VFP when enabled such that we can keep having SMP Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-08-15 10:37:45 +08:00
endif
ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-02-21 07:53:13 +08:00
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes. This patch adds machine support for the ARM-based Broadcom SoCs. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-01-17 07:00:42 +08:00
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
ARM: brcmstb: reintroduce SMP support Support for SMP bringup of the B15 CPUs on Broadcom STB chips was added in commit 4fbe66d9903425156c193ae44c81c0f7557755c4 but was reverted in commit fc3e825fa91636a5d1b992e769b2d8279877bfad to address some late review comments. This reintroduces SMP support. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-09-06 07:31:04 +08:00
CFLAGS_platsmp-brcmstb.o += -march=armv7-a
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes. This patch adds machine support for the ARM-based Broadcom SoCs. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-01-17 07:00:42 +08:00
obj-y += brcmstb.o
ARM: v7 setup function should invalidate L1 cache All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-05-20 00:06:44 +08:00
obj-$(CONFIG_SMP) += platsmp-brcmstb.o
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes. This patch adds machine support for the ARM-based Broadcom SoCs. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-01-17 07:00:42 +08:00
endif