2005-04-17 06:20:36 +08:00
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#include <linux/init.h>
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#include <linux/mm.h>
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2009-07-04 10:20:44 +08:00
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2005-04-17 06:20:36 +08:00
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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2009-07-04 10:20:44 +08:00
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2005-04-17 06:20:36 +08:00
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#include "mtrr.h"
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static struct {
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unsigned long high;
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unsigned long low;
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} centaur_mcr[8];
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static u8 centaur_mcr_reserved;
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static u8 centaur_mcr_type; /* 0 for winchip, 1 for winchip2 */
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2009-07-04 10:20:44 +08:00
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/**
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* centaur_get_free_region - Get a free MTRR.
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*
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* @base: The starting (base) address of the region.
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* @size: The size (in bytes) of the region.
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*
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* Returns: the index of the region on success, else -1 on error.
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2005-04-17 06:20:36 +08:00
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*/
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static int
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[PATCH] i386: fix MTRR code
Until not so long ago, there were system log messages pointing to
inconsistent MTRR setup of the video frame buffer caused by the way vesafb
and X worked. While vesafb was fixed meanwhile, I believe fixing it there
only hides a shortcoming in the MTRR code itself, in that that code is not
symmetric with respect to the ordering of attempts to set up two (or more)
regions where one contains the other. In the current shape, it permits
only setting up sub-regions of pre-exisiting ones. The patch below makes
this symmetric.
While working on that I noticed a few more inconsistencies in that code,
namely
- use of 'unsigned int' for sizes in many, but not all places (the patch
is converting this to use 'unsigned long' everywhere, which specifically
might be necessary for x86-64 once a processor supporting more than 44
physical address bits would become available)
- the code to correct inconsistent settings during secondary processor
startup tried (if necessary) to correct, among other things, the value
in IA32_MTRR_DEF_TYPE, however the newly computed value would never get
used (i.e. stored in the respective MSR)
- the generic range validation code checked that the end of the
to-be-added range would be above 1MB; the value checked should have been
the start of the range
- when contained regions are detected, previously this was allowed only
when the old region was uncacheable; this can be symmetric (i.e. the new
region can also be uncacheable) and even further as per Intel's
documentation write-trough and write-back for either region is also
compatible with the respective opposite in the other
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andi Kleen <ak@suse.de>
2006-12-07 09:14:09 +08:00
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centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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2005-04-17 06:20:36 +08:00
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{
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[PATCH] i386: fix MTRR code
Until not so long ago, there were system log messages pointing to
inconsistent MTRR setup of the video frame buffer caused by the way vesafb
and X worked. While vesafb was fixed meanwhile, I believe fixing it there
only hides a shortcoming in the MTRR code itself, in that that code is not
symmetric with respect to the ordering of attempts to set up two (or more)
regions where one contains the other. In the current shape, it permits
only setting up sub-regions of pre-exisiting ones. The patch below makes
this symmetric.
While working on that I noticed a few more inconsistencies in that code,
namely
- use of 'unsigned int' for sizes in many, but not all places (the patch
is converting this to use 'unsigned long' everywhere, which specifically
might be necessary for x86-64 once a processor supporting more than 44
physical address bits would become available)
- the code to correct inconsistent settings during secondary processor
startup tried (if necessary) to correct, among other things, the value
in IA32_MTRR_DEF_TYPE, however the newly computed value would never get
used (i.e. stored in the respective MSR)
- the generic range validation code checked that the end of the
to-be-added range would be above 1MB; the value checked should have been
the start of the range
- when contained regions are detected, previously this was allowed only
when the old region was uncacheable; this can be symmetric (i.e. the new
region can also be uncacheable) and even further as per Intel's
documentation write-trough and write-back for either region is also
compatible with the respective opposite in the other
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andi Kleen <ak@suse.de>
2006-12-07 09:14:09 +08:00
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unsigned long lbase, lsize;
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2009-07-04 10:20:44 +08:00
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mtrr_type ltype;
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int i, max;
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2005-04-17 06:20:36 +08:00
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max = num_var_ranges;
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[PATCH] i386: fix MTRR code
Until not so long ago, there were system log messages pointing to
inconsistent MTRR setup of the video frame buffer caused by the way vesafb
and X worked. While vesafb was fixed meanwhile, I believe fixing it there
only hides a shortcoming in the MTRR code itself, in that that code is not
symmetric with respect to the ordering of attempts to set up two (or more)
regions where one contains the other. In the current shape, it permits
only setting up sub-regions of pre-exisiting ones. The patch below makes
this symmetric.
While working on that I noticed a few more inconsistencies in that code,
namely
- use of 'unsigned int' for sizes in many, but not all places (the patch
is converting this to use 'unsigned long' everywhere, which specifically
might be necessary for x86-64 once a processor supporting more than 44
physical address bits would become available)
- the code to correct inconsistent settings during secondary processor
startup tried (if necessary) to correct, among other things, the value
in IA32_MTRR_DEF_TYPE, however the newly computed value would never get
used (i.e. stored in the respective MSR)
- the generic range validation code checked that the end of the
to-be-added range would be above 1MB; the value checked should have been
the start of the range
- when contained regions are detected, previously this was allowed only
when the old region was uncacheable; this can be symmetric (i.e. the new
region can also be uncacheable) and even further as per Intel's
documentation write-trough and write-back for either region is also
compatible with the respective opposite in the other
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andi Kleen <ak@suse.de>
2006-12-07 09:14:09 +08:00
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if (replace_reg >= 0 && replace_reg < max)
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return replace_reg;
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2009-07-04 10:20:44 +08:00
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2005-04-17 06:20:36 +08:00
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for (i = 0; i < max; ++i) {
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if (centaur_mcr_reserved & (1 << i))
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continue;
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (lsize == 0)
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return i;
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}
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2009-07-04 10:20:44 +08:00
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2005-04-17 06:20:36 +08:00
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return -ENOSPC;
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}
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2009-07-04 10:20:44 +08:00
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/*
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* Report boot time MCR setups
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*/
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void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
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2005-04-17 06:20:36 +08:00
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{
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centaur_mcr[mcr].low = lo;
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centaur_mcr[mcr].high = hi;
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}
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static void
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centaur_get_mcr(unsigned int reg, unsigned long *base,
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[PATCH] i386: fix MTRR code
Until not so long ago, there were system log messages pointing to
inconsistent MTRR setup of the video frame buffer caused by the way vesafb
and X worked. While vesafb was fixed meanwhile, I believe fixing it there
only hides a shortcoming in the MTRR code itself, in that that code is not
symmetric with respect to the ordering of attempts to set up two (or more)
regions where one contains the other. In the current shape, it permits
only setting up sub-regions of pre-exisiting ones. The patch below makes
this symmetric.
While working on that I noticed a few more inconsistencies in that code,
namely
- use of 'unsigned int' for sizes in many, but not all places (the patch
is converting this to use 'unsigned long' everywhere, which specifically
might be necessary for x86-64 once a processor supporting more than 44
physical address bits would become available)
- the code to correct inconsistent settings during secondary processor
startup tried (if necessary) to correct, among other things, the value
in IA32_MTRR_DEF_TYPE, however the newly computed value would never get
used (i.e. stored in the respective MSR)
- the generic range validation code checked that the end of the
to-be-added range would be above 1MB; the value checked should have been
the start of the range
- when contained regions are detected, previously this was allowed only
when the old region was uncacheable; this can be symmetric (i.e. the new
region can also be uncacheable) and even further as per Intel's
documentation write-trough and write-back for either region is also
compatible with the respective opposite in the other
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andi Kleen <ak@suse.de>
2006-12-07 09:14:09 +08:00
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unsigned long *size, mtrr_type * type)
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2005-04-17 06:20:36 +08:00
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{
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*base = centaur_mcr[reg].high >> PAGE_SHIFT;
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*size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
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2009-07-04 10:20:44 +08:00
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*type = MTRR_TYPE_WRCOMB; /* write-combining */
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2005-04-17 06:20:36 +08:00
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if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
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*type = MTRR_TYPE_UNCACHABLE;
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if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
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*type = MTRR_TYPE_WRBACK;
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if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
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*type = MTRR_TYPE_WRBACK;
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}
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2009-07-04 10:20:44 +08:00
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static void
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centaur_set_mcr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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2005-04-17 06:20:36 +08:00
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{
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unsigned long low, high;
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if (size == 0) {
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2009-07-04 10:20:44 +08:00
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/* Disable */
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2005-04-17 06:20:36 +08:00
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high = low = 0;
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} else {
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high = base << PAGE_SHIFT;
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2009-07-04 10:20:44 +08:00
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if (centaur_mcr_type == 0) {
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/* Only support write-combining... */
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low = -size << PAGE_SHIFT | 0x1f;
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} else {
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2005-04-17 06:20:36 +08:00
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if (type == MTRR_TYPE_UNCACHABLE)
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2009-07-04 10:20:44 +08:00
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low = -size << PAGE_SHIFT | 0x02; /* NC */
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2005-04-17 06:20:36 +08:00
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else
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2009-07-04 10:20:44 +08:00
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low = -size << PAGE_SHIFT | 0x09; /* WWO, WC */
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2005-04-17 06:20:36 +08:00
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}
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}
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centaur_mcr[reg].high = high;
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centaur_mcr[reg].low = low;
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wrmsr(MSR_IDT_MCR0 + reg, low, high);
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}
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2009-07-04 10:20:44 +08:00
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static int
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centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
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2005-04-17 06:20:36 +08:00
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{
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/*
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2009-07-04 10:20:44 +08:00
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* FIXME: Winchip2 supports uncached
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2005-04-17 06:20:36 +08:00
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*/
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2009-07-04 10:20:44 +08:00
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if (type != MTRR_TYPE_WRCOMB &&
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2005-04-17 06:20:36 +08:00
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(centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
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2009-07-04 10:20:44 +08:00
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pr_warning("mtrr: only write-combining%s supported\n",
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centaur_mcr_type ? " and uncacheable are" : " is");
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2005-04-17 06:20:36 +08:00
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return -EINVAL;
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}
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return 0;
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}
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static struct mtrr_ops centaur_mtrr_ops = {
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.vendor = X86_VENDOR_CENTAUR,
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.set = centaur_set_mcr,
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.get = centaur_get_mcr,
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.get_free_region = centaur_get_free_region,
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.validate_add_page = centaur_validate_add_page,
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.have_wrcomb = positive_have_wrcomb,
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};
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int __init centaur_init_mtrr(void)
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{
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set_mtrr_ops(¢aur_mtrr_ops);
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return 0;
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}
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