607 lines
15 KiB
C
607 lines
15 KiB
C
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/*
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* OMAP3 Power Management Routines
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*
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* Copyright (C) 2006-2008 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Jouni Hogander
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <mach/sram.h>
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#include <mach/clockdomain.h>
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#include <mach/powerdomain.h>
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#include <mach/control.h>
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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#include "prm.h"
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#include "pm.h"
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
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u32 saved_state;
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struct list_head node;
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};
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static LIST_HEAD(pwrst_list);
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static void (*_omap_sram_idle)(u32 *addr, int save_state);
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static struct powerdomain *mpu_pwrdm;
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/* PRCM Interrupt Handler for wakeups */
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static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
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{
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u32 wkst, irqstatus_mpu;
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u32 fclk, iclk;
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/* WKUP */
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wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
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if (wkst) {
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iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
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fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
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cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
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cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
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prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
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while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
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cpu_relax();
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cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
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cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
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}
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/* CORE */
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wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
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if (wkst) {
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iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
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fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
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cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
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prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
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while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
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cpu_relax();
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cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
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cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
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}
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wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
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if (wkst) {
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iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
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fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
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cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
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while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
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cpu_relax();
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cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
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cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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}
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/* PER */
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wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
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if (wkst) {
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iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
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fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
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prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
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while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
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cpu_relax();
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cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
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cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
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}
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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/* USBHOST */
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wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
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if (wkst) {
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iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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CM_ICLKEN);
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fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
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CM_ICLKEN);
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cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
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PM_WKST);
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while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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PM_WKST))
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cpu_relax();
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cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
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CM_ICLKEN);
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cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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}
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}
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irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
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cpu_relax();
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return IRQ_HANDLED;
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}
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static void omap_sram_idle(void)
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{
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/* Variable to tell what needs to be saved and restored
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* in omap_sram_idle*/
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/* save_state = 0 => Nothing to save and restored */
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/* save_state = 1 => Only L1 and logic lost */
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/* save_state = 2 => Only L2 lost */
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/* save_state = 3 => L1, L2 and logic lost */
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int save_state = 0, mpu_next_state;
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if (!_omap_sram_idle)
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return;
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mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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switch (mpu_next_state) {
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case PWRDM_POWER_RET:
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/* No need to save context */
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save_state = 0;
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break;
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default:
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/* Invalid state */
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printk(KERN_ERR "Invalid mpu state in sram_idle\n");
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return;
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}
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omap2_gpio_prepare_for_retention();
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_omap_sram_idle(NULL, save_state);
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cpu_init();
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omap2_gpio_resume_after_retention();
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}
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/*
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* Check if functional clocks are enabled before entering
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* sleep. This function could be behind CONFIG_PM_DEBUG
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* when all drivers are configuring their sysconfig registers
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* properly and using their clocks properly.
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*/
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static int omap3_fclks_active(void)
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{
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u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
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fck_cam = 0, fck_per = 0, fck_usbhost = 0;
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fck_core1 = cm_read_mod_reg(CORE_MOD,
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CM_FCLKEN1);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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fck_core3 = cm_read_mod_reg(CORE_MOD,
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OMAP3430ES2_CM_FCLKEN3);
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fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
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CM_FCLKEN);
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fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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CM_FCLKEN);
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} else
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fck_sgx = cm_read_mod_reg(GFX_MOD,
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OMAP3430ES2_CM_FCLKEN3);
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fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
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CM_FCLKEN);
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fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
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CM_FCLKEN);
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fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
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CM_FCLKEN);
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if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
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fck_cam | fck_per | fck_usbhost)
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return 1;
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return 0;
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}
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static int omap3_can_sleep(void)
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{
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if (omap3_fclks_active())
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return 0;
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return 1;
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}
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/* This sets pwrdm state (other than mpu & core. Currently only ON &
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* RET are supported. Function is assuming that clkdm doesn't have
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* hw_sup mode enabled. */
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static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
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{
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u32 cur_state;
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int sleep_switch = 0;
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int ret = 0;
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if (pwrdm == NULL || IS_ERR(pwrdm))
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return -EINVAL;
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while (!(pwrdm->pwrsts & (1 << state))) {
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if (state == PWRDM_POWER_OFF)
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return ret;
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state--;
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}
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cur_state = pwrdm_read_next_pwrst(pwrdm);
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if (cur_state == state)
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return ret;
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if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
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omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
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sleep_switch = 1;
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pwrdm_wait_transition(pwrdm);
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}
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ret = pwrdm_set_next_pwrst(pwrdm, state);
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if (ret) {
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printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
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pwrdm->name);
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goto err;
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}
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if (sleep_switch) {
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omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
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pwrdm_wait_transition(pwrdm);
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}
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err:
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return ret;
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}
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static void omap3_pm_idle(void)
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{
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local_irq_disable();
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local_fiq_disable();
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if (!omap3_can_sleep())
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goto out;
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if (omap_irq_pending())
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goto out;
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omap_sram_idle();
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out:
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local_fiq_enable();
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local_irq_enable();
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}
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static int omap3_pm_prepare(void)
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{
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disable_hlt();
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return 0;
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}
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static int omap3_pm_suspend(void)
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{
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struct power_state *pwrst;
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int state, ret = 0;
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/* Read current next_pwrsts */
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list_for_each_entry(pwrst, &pwrst_list, node)
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pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
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/* Set ones wanted by suspend */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
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goto restore;
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if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
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goto restore;
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}
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omap_sram_idle();
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restore:
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/* Restore next_pwrsts */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
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state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
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if (state > pwrst->next_state) {
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printk(KERN_INFO "Powerdomain (%s) didn't enter "
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"target state %d\n",
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pwrst->pwrdm->name, pwrst->next_state);
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ret = -1;
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}
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}
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if (ret)
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printk(KERN_ERR "Could not enter target state in pm_suspend\n");
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else
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printk(KERN_INFO "Successfully put all powerdomains "
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"to target state\n");
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return ret;
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}
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static int omap3_pm_enter(suspend_state_t state)
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{
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int ret = 0;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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ret = omap3_pm_suspend();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static void omap3_pm_finish(void)
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{
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enable_hlt();
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}
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static struct platform_suspend_ops omap_pm_ops = {
|
||
|
|
.prepare = omap3_pm_prepare,
|
||
|
|
.enter = omap3_pm_enter,
|
||
|
|
.finish = omap3_pm_finish,
|
||
|
|
.valid = suspend_valid_only_mem,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void __init prcm_setup_regs(void)
|
||
|
|
{
|
||
|
|
/* reset modem */
|
||
|
|
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
|
||
|
|
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
|
||
|
|
CORE_MOD, RM_RSTCTRL);
|
||
|
|
prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
|
||
|
|
|
||
|
|
/* XXX Reset all wkdeps. This should be done when initializing
|
||
|
|
* powerdomains */
|
||
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
|
||
|
|
prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
|
||
|
|
prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
|
||
|
|
prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
|
||
|
|
prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
|
||
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
|
||
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
||
|
|
prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
|
||
|
|
prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
||
|
|
} else
|
||
|
|
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable interface clock autoidle for all modules.
|
||
|
|
* Note that in the long run this should be done by clockfw
|
||
|
|
*/
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430ES2_AUTO_MMC3 |
|
||
|
|
OMAP3430ES2_AUTO_ICR |
|
||
|
|
OMAP3430_AUTO_AES2 |
|
||
|
|
OMAP3430_AUTO_SHA12 |
|
||
|
|
OMAP3430_AUTO_DES2 |
|
||
|
|
OMAP3430_AUTO_MMC2 |
|
||
|
|
OMAP3430_AUTO_MMC1 |
|
||
|
|
OMAP3430_AUTO_MSPRO |
|
||
|
|
OMAP3430_AUTO_HDQ |
|
||
|
|
OMAP3430_AUTO_MCSPI4 |
|
||
|
|
OMAP3430_AUTO_MCSPI3 |
|
||
|
|
OMAP3430_AUTO_MCSPI2 |
|
||
|
|
OMAP3430_AUTO_MCSPI1 |
|
||
|
|
OMAP3430_AUTO_I2C3 |
|
||
|
|
OMAP3430_AUTO_I2C2 |
|
||
|
|
OMAP3430_AUTO_I2C1 |
|
||
|
|
OMAP3430_AUTO_UART2 |
|
||
|
|
OMAP3430_AUTO_UART1 |
|
||
|
|
OMAP3430_AUTO_GPT11 |
|
||
|
|
OMAP3430_AUTO_GPT10 |
|
||
|
|
OMAP3430_AUTO_MCBSP5 |
|
||
|
|
OMAP3430_AUTO_MCBSP1 |
|
||
|
|
OMAP3430ES1_AUTO_FAC | /* This is es1 only */
|
||
|
|
OMAP3430_AUTO_MAILBOXES |
|
||
|
|
OMAP3430_AUTO_OMAPCTRL |
|
||
|
|
OMAP3430ES1_AUTO_FSHOSTUSB |
|
||
|
|
OMAP3430_AUTO_HSOTGUSB |
|
||
|
|
OMAP3430ES1_AUTO_D2D | /* This is es1 only */
|
||
|
|
OMAP3430_AUTO_SSI,
|
||
|
|
CORE_MOD, CM_AUTOIDLE1);
|
||
|
|
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430_AUTO_PKA |
|
||
|
|
OMAP3430_AUTO_AES1 |
|
||
|
|
OMAP3430_AUTO_RNG |
|
||
|
|
OMAP3430_AUTO_SHA11 |
|
||
|
|
OMAP3430_AUTO_DES1,
|
||
|
|
CORE_MOD, CM_AUTOIDLE2);
|
||
|
|
|
||
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430ES2_AUTO_USBTLL,
|
||
|
|
CORE_MOD, CM_AUTOIDLE3);
|
||
|
|
}
|
||
|
|
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430_AUTO_WDT2 |
|
||
|
|
OMAP3430_AUTO_WDT1 |
|
||
|
|
OMAP3430_AUTO_GPIO1 |
|
||
|
|
OMAP3430_AUTO_32KSYNC |
|
||
|
|
OMAP3430_AUTO_GPT12 |
|
||
|
|
OMAP3430_AUTO_GPT1 ,
|
||
|
|
WKUP_MOD, CM_AUTOIDLE);
|
||
|
|
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430_AUTO_DSS,
|
||
|
|
OMAP3430_DSS_MOD,
|
||
|
|
CM_AUTOIDLE);
|
||
|
|
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430_AUTO_CAM,
|
||
|
|
OMAP3430_CAM_MOD,
|
||
|
|
CM_AUTOIDLE);
|
||
|
|
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430_AUTO_GPIO6 |
|
||
|
|
OMAP3430_AUTO_GPIO5 |
|
||
|
|
OMAP3430_AUTO_GPIO4 |
|
||
|
|
OMAP3430_AUTO_GPIO3 |
|
||
|
|
OMAP3430_AUTO_GPIO2 |
|
||
|
|
OMAP3430_AUTO_WDT3 |
|
||
|
|
OMAP3430_AUTO_UART3 |
|
||
|
|
OMAP3430_AUTO_GPT9 |
|
||
|
|
OMAP3430_AUTO_GPT8 |
|
||
|
|
OMAP3430_AUTO_GPT7 |
|
||
|
|
OMAP3430_AUTO_GPT6 |
|
||
|
|
OMAP3430_AUTO_GPT5 |
|
||
|
|
OMAP3430_AUTO_GPT4 |
|
||
|
|
OMAP3430_AUTO_GPT3 |
|
||
|
|
OMAP3430_AUTO_GPT2 |
|
||
|
|
OMAP3430_AUTO_MCBSP4 |
|
||
|
|
OMAP3430_AUTO_MCBSP3 |
|
||
|
|
OMAP3430_AUTO_MCBSP2,
|
||
|
|
OMAP3430_PER_MOD,
|
||
|
|
CM_AUTOIDLE);
|
||
|
|
|
||
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
||
|
|
cm_write_mod_reg(
|
||
|
|
OMAP3430ES2_AUTO_USBHOST,
|
||
|
|
OMAP3430ES2_USBHOST_MOD,
|
||
|
|
CM_AUTOIDLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set all plls to autoidle. This is needed until autoidle is
|
||
|
|
* enabled by clockfw
|
||
|
|
*/
|
||
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
|
||
|
|
OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
|
||
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
|
||
|
|
MPU_MOD,
|
||
|
|
CM_AUTOIDLE2);
|
||
|
|
cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
|
||
|
|
(1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
|
||
|
|
PLL_MOD,
|
||
|
|
CM_AUTOIDLE);
|
||
|
|
cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
|
||
|
|
PLL_MOD,
|
||
|
|
CM_AUTOIDLE2);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable control of expternal oscillator through
|
||
|
|
* sys_clkreq. In the long run clock framework should
|
||
|
|
* take care of this.
|
||
|
|
*/
|
||
|
|
prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
||
|
|
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
||
|
|
OMAP3430_GR_MOD,
|
||
|
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||
|
|
|
||
|
|
/* setup wakup source */
|
||
|
|
prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
|
||
|
|
OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
|
||
|
|
WKUP_MOD, PM_WKEN);
|
||
|
|
/* No need to write EN_IO, that is always enabled */
|
||
|
|
prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
|
||
|
|
OMAP3430_EN_GPT12,
|
||
|
|
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
||
|
|
/* For some reason IO doesn't generate wakeup event even if
|
||
|
|
* it is selected to mpu wakeup goup */
|
||
|
|
prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
|
||
|
|
OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init pwrdms_setup(struct powerdomain *pwrdm)
|
||
|
|
{
|
||
|
|
struct power_state *pwrst;
|
||
|
|
|
||
|
|
if (!pwrdm->pwrsts)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
|
||
|
|
if (!pwrst)
|
||
|
|
return -ENOMEM;
|
||
|
|
pwrst->pwrdm = pwrdm;
|
||
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
||
|
|
list_add(&pwrst->node, &pwrst_list);
|
||
|
|
|
||
|
|
if (pwrdm_has_hdwr_sar(pwrdm))
|
||
|
|
pwrdm_enable_hdwr_sar(pwrdm);
|
||
|
|
|
||
|
|
return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable hw supervised mode for all clockdomains if it's
|
||
|
|
* supported. Initiate sleep transition for other clockdomains, if
|
||
|
|
* they are not used
|
||
|
|
*/
|
||
|
|
static int __init clkdms_setup(struct clockdomain *clkdm)
|
||
|
|
{
|
||
|
|
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
|
||
|
|
omap2_clkdm_allow_idle(clkdm);
|
||
|
|
else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
|
||
|
|
atomic_read(&clkdm->usecount) == 0)
|
||
|
|
omap2_clkdm_sleep(clkdm);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int __init omap3_pm_init(void)
|
||
|
|
{
|
||
|
|
struct power_state *pwrst, *tmp;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!cpu_is_omap34xx())
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
printk(KERN_ERR "Power Management for TI OMAP3.\n");
|
||
|
|
|
||
|
|
/* XXX prcm_setup_regs needs to be before enabling hw
|
||
|
|
* supervised mode for powerdomains */
|
||
|
|
prcm_setup_regs();
|
||
|
|
|
||
|
|
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
|
||
|
|
(irq_handler_t)prcm_interrupt_handler,
|
||
|
|
IRQF_DISABLED, "prcm", NULL);
|
||
|
|
if (ret) {
|
||
|
|
printk(KERN_ERR "request_irq failed to register for 0x%x\n",
|
||
|
|
INT_34XX_PRCM_MPU_IRQ);
|
||
|
|
goto err1;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = pwrdm_for_each(pwrdms_setup);
|
||
|
|
if (ret) {
|
||
|
|
printk(KERN_ERR "Failed to setup powerdomains\n");
|
||
|
|
goto err2;
|
||
|
|
}
|
||
|
|
|
||
|
|
(void) clkdm_for_each(clkdms_setup);
|
||
|
|
|
||
|
|
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
|
||
|
|
if (mpu_pwrdm == NULL) {
|
||
|
|
printk(KERN_ERR "Failed to get mpu_pwrdm\n");
|
||
|
|
goto err2;
|
||
|
|
}
|
||
|
|
|
||
|
|
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
|
||
|
|
omap34xx_cpu_suspend_sz);
|
||
|
|
|
||
|
|
suspend_set_ops(&omap_pm_ops);
|
||
|
|
|
||
|
|
pm_idle = omap3_pm_idle;
|
||
|
|
|
||
|
|
err1:
|
||
|
|
return ret;
|
||
|
|
err2:
|
||
|
|
free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
|
||
|
|
list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
|
||
|
|
list_del(&pwrst->node);
|
||
|
|
kfree(pwrst);
|
||
|
|
}
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
late_initcall(omap3_pm_init);
|