2008-04-11 05:28:10 +08:00
|
|
|
/*
|
|
|
|
* Definitions for the wakeup data structure at the head of the
|
|
|
|
* wakeup code.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H
|
|
|
|
#define ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#include <linux/types.h>
|
|
|
|
|
|
|
|
/* This must match data at wakeup.S */
|
|
|
|
struct wakeup_header {
|
|
|
|
u16 video_mode; /* Video mode number */
|
|
|
|
u32 pmode_entry; /* Protected mode resume point, 32-bit only */
|
2012-05-09 02:22:29 +08:00
|
|
|
u16 pmode_cs;
|
2008-04-11 05:28:10 +08:00
|
|
|
u32 pmode_cr0; /* Protected mode cr0 */
|
|
|
|
u32 pmode_cr3; /* Protected mode cr3 */
|
|
|
|
u32 pmode_cr4; /* Protected mode cr4 */
|
|
|
|
u32 pmode_efer_low; /* Protected mode EFER */
|
|
|
|
u32 pmode_efer_high;
|
|
|
|
u64 pmode_gdt;
|
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae723d8a8fc2f7abce5ec18b688b791d7. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)
The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)
[ hpa: Consider for stable if OK in mainline ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
2011-07-07 09:10:34 +08:00
|
|
|
u32 pmode_misc_en_low; /* Protected mode MISC_ENABLE */
|
|
|
|
u32 pmode_misc_en_high;
|
|
|
|
u32 pmode_behavior; /* Wakeup routine behavior flags */
|
2008-04-11 05:28:10 +08:00
|
|
|
u32 realmode_flags;
|
|
|
|
u32 real_magic;
|
|
|
|
u32 signature; /* To check we have correct structure */
|
|
|
|
} __attribute__((__packed__));
|
|
|
|
|
|
|
|
extern struct wakeup_header wakeup_header;
|
|
|
|
#endif
|
|
|
|
|
2011-02-15 07:42:46 +08:00
|
|
|
#define WAKEUP_HEADER_OFFSET 8
|
|
|
|
#define WAKEUP_HEADER_SIGNATURE 0x51ee1111
|
2008-04-11 05:28:10 +08:00
|
|
|
|
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae723d8a8fc2f7abce5ec18b688b791d7. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)
The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)
[ hpa: Consider for stable if OK in mainline ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
2011-07-07 09:10:34 +08:00
|
|
|
/* Wakeup behavior bits */
|
|
|
|
#define WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE 0
|
2012-09-27 06:02:34 +08:00
|
|
|
#define WAKEUP_BEHAVIOR_RESTORE_CR4 1
|
|
|
|
#define WAKEUP_BEHAVIOR_RESTORE_EFER 2
|
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae723d8a8fc2f7abce5ec18b688b791d7. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)
The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)
[ hpa: Consider for stable if OK in mainline ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
2011-07-07 09:10:34 +08:00
|
|
|
|
2008-04-11 05:28:10 +08:00
|
|
|
#endif /* ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H */
|